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Rev 28 → Rev 29

/trunk/rtl/ADDR_UNIT.v
1,15 → 1,16
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ADDR_UNIT.v
// Version: 2.0
// History: 1.1 bug fix of 7 October 2015
// Version: 3.0
// History: 2.0 of 11 August 2016
// 1.1 bug fix of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
32,7 → 33,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// ADDR_UNIT generates data access addresses and controls data cache operation
41,7 → 42,7
 
module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,
NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, CTRL_QW, BITSEL,
QWATWO );
 
input BCLK,BRESET;
75,7 → 76,7
output [3:0] PACKET;
output ACC_DONE;
output ABORT;
output REG_OUT;
output [1:0] CTRL_QW;
output [2:0] BITSEL;
output reg QWATWO;
104,6 → 105,7
reg [2:0] u_ddt;
reg pg_op;
reg do_wr;
reg irdy_flag;
wire acc_ok,acc_err,io_acc;
wire acc_pass;
159,7 → 161,7
always @(index_sel or sign_ext_src1 or SRC1)
casex (index_sel)
 
4'b1_0xx : index_val = sign_ext_src1; // f�r CASE
4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
4'b0_100 : index_val = SRC1;
4'b0_101 : index_val = {SRC1[30:0],1'b0};
345,11 → 347,12
// Bugfix of 7.October 2015
always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
 
always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & ~io_rdy & ~ca_hit & acc_ok) | reg_out_i);
always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
always @(posedge BCLK) irdy_flag <= (READ_OUT & io_acc) | (irdy_flag & ~IO_READY); // new 25.6.2018
always @(posedge BCLK) io_rdy <= IO_READY & irdy_flag;
always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
assign REG_OUT = reg_out_i | next_reg;
always @(posedge BCLK) next_reg <= acc_step & (qwa_flag ? io_rdy : 1'b1) & (SIZE == 2'b11);
assign CTRL_QW = {qwa_flag,(reg_out_i | next_reg)};
endmodule
/trunk/rtl/ALIGNER.v
1,14 → 1,14
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ALIGNER.v
// Version: 2.0
// Version: 3.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 31,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. WR_ALINGER alignes write data to cache and external devices
/trunk/rtl/CACHE_LOGIK.v
1,15 → 1,16
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: CACHE_LOGIK.v
// Version: 2.0
// History: 1.1 bug fix of 7 October 2015
// Version: 3.0
// History: 2.0 of 11 August 2016
// 1.1 bug fix of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
32,25 → 33,66
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. NEU_VALID Cache Valid RAM
// 2. DEBUG_AE Debug unit for address compare in data cache
// 3. MMU_UP MMU memory update and initalization controller
// 4. DCA_CONTROL Data cache valid memory update and initalization controller
// 5. MMU_MATCH MMU virtual address match detector
// 6. CA_MATCH Cache tag match detector
// 7. FILTCMP Address Filter and Comparator
// 8. DCACHE_SM Data cache state machine
// 1. WRPORT Write Port
// 2. NEU_VALID Cache Valid RAM
// 3. DEBUG_AE Debug unit for address compare in data cache
// 4. MMU_UP MMU memory update and initalization controller
// 5. DCA_CONTROL Data cache valid memory update and initalization controller
// 6. MMU_MATCH MMU virtual address match detector
// 7. CA_MATCH Cache tag match detector
// 8. FILTCMP Address Filter and Comparator
// 9. DCACHE_SM Data cache state machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 1. NEU_VALID Cache Valid RAM
// 1. WRPORT Write Port
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module WRPORT ( WRITE, DRAM_Q, WRDATA, ENBYTE, VADDR, DADDR, WDAT, CAP_Q, ENB );
 
input WRITE;
input [127:0] DRAM_Q;
input [31:0] WRDATA;
input [3:0] ENBYTE;
input [3:2] VADDR;
input [3:2] DADDR;
output [127:0] WDAT;
output reg [31:0] CAP_Q;
output reg [15:0] ENB;
assign WDAT = WRITE ? {WRDATA,WRDATA,WRDATA,WRDATA} : DRAM_Q;
always @(DADDR or DRAM_Q)
case (DADDR)
2'b00 : CAP_Q = DRAM_Q[31:0];
2'b01 : CAP_Q = DRAM_Q[63:32];
2'b10 : CAP_Q = DRAM_Q[95:64];
2'b11 : CAP_Q = DRAM_Q[127:96];
endcase
always @(WRITE or VADDR or ENBYTE)
case ({WRITE,VADDR})
3'b100 : ENB = {4'd0 ,4'd0 ,4'd0 ,ENBYTE};
3'b101 : ENB = {4'd0 ,4'd0 ,ENBYTE,4'd0 };
3'b110 : ENB = {4'd0 ,ENBYTE,4'd0 ,4'd0 };
3'b111 : ENB = {ENBYTE,4'd0 ,4'd0 ,4'd0 };
default : ENB = 16'hFFFF;
endcase
endmodule
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. NEU_VALID Cache Valid RAM
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module NEU_VALID ( BCLK, VALIN, WADR, WREN, RADR, VALOUT );
 
input BCLK;
78,7 → 120,7
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. DEBUG_AE Debug unit for address compare in data cache
// 3. DEBUG_AE Debug unit for address compare in data cache
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DEBUG_AE ( DBG_IN, READ, WRITE, USER, VIRTUELL, ACC_OK, VADR_R, MMU_Q, ENBYTE, DBG_HIT );
125,7 → 167,7
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 3. MMU_UP MMU memory update and initalization controller
// 4. MMU_UP MMU memory update and initalization controller
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module MMU_UP ( BCLK, BRESET, NEW_PTB, PTB1, IVAR, WR_MRAM, VADR, VADR_R, MVALID, UPDATE,
176,25 → 218,25
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 4. DCA_CONTROL Data cache valid memory update and initalization controller
// 5. DCA_CONTROL Data cache valid memory update and initalization controller
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DCA_CONTROL ( BCLK, MCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, WRCFG, VADR_R, UPDATE, INVAL_A, WRITE,
WCTRL, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );
module DCA_CONTROL ( BCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, VADR_R, UPDATE, INVAL_A, WRITE, MDONE, USE_CA,
INHIBIT, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );
 
input BCLK;
input MCLK;
input BRESET;
input CUPDATE; // State CUPDATE : Cache is filled from DRAM
input DRAM_ACC;
input CA_SET;
input HIT_ALL; // a complete cache hit !
input WRCFG; // static signal : GND or VDD
input [11:7] VADR_R;
input [23:0] UPDATE;
input INVAL_A;
input WRITE;
input [1:0] WCTRL; // [1] : Read Burst Signal from DRAM controller, MCLK aligned. [0] : Cache inhibit
input MDONE; // Signal from DRAM : Access Done
input USE_CA; // Signal use cache
input INHIBIT; // Signal cache inhibit - no write in cache
input KILL; // valid Ram must be updated because of collision ... or CINV
output WRCRAM0,WRCRAM1;
208,9 → 250,6
reg [4:0] acount;
reg ca_set_d;
 
reg dly_bclk,zero,wr_puls;
reg [2:0] count,refer;
wire countf;
always @(posedge BCLK) if (DRAM_ACC) ca_set_d <= CA_SET; // Store for whole access
217,12 → 256,12
 
// physical address is stored in TAG-RAM
 
assign WRCRAM0 = (CUPDATE & ~WCTRL[0]) & ~ca_set_d;
assign WRCRAM1 = (CUPDATE & ~WCTRL[0]) & ca_set_d;
assign WRCRAM0 = (CUPDATE & ~INHIBIT) & ~ca_set_d;
assign WRCRAM1 = (CUPDATE & ~INHIBIT) & ca_set_d;
// Load Valid RAM :
assign WE_CV = state[1] | HIT_ALL | (CUPDATE & ~WCTRL[0]) | KILL; // Hit All for "Last" Update
assign WE_CV = state[1] | HIT_ALL | (CUPDATE & ~INHIBIT) | KILL; // Hit All for "Last" Update
assign WADR_CV = state[1] ? acount : VADR_R;
assign DAT_CV = state[1] ? 24'h0 : UPDATE;
 
246,31 → 285,14
assign INIT_CA_RUN = state[1];
// WRITE Control in data RAMs
assign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ~ca_set_d);
assign WRSET1 = ( CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ca_set_d);
assign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL) | (MDONE & USE_CA & ~ca_set_d);
assign WRSET1 = ( CA_SET & WRITE & HIT_ALL) | (MDONE & USE_CA & ca_set_d);
// ++++++++++++ Special circuit for Timing of write pulse for data RAM of data cache +++++++++
always @(negedge MCLK) dly_bclk <= BCLK;
always @(negedge MCLK) zero <= BCLK & ~dly_bclk;
always @(posedge MCLK) if (zero) count <= 3'd0; else count <= count + 3'd1;
// count at zero , ref Wert
// 1 : --- always on 5 : 100 001
// 2 : 001 000 6 : 101 010
// 3 : 010 010 7 : 110 011
// 4 : 011 000 8 : 111 100
always @(posedge MCLK) if (zero) refer <= {(count == 3'd7),((count == 3'd5) | (count[1:0] == 2'b10)),(count[2] & ~count[0])};
always @(posedge MCLK) wr_puls <= (count == refer) | WRCFG;
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 5. MMU_MATCH MMU virtual address match detector
// 6. MMU_MATCH MMU virtual address match detector
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module MMU_MATCH ( USER, READ, WRITE, RMW, MCR_FLAGS, MVALID, VADR_R, MMU_VA, IVAR,
357,7 → 379,7
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 6. CA_MATCH Cache tag match detector
// 7. CA_MATCH Cache tag match detector
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module CA_MATCH ( CVALID, DRAMSZ, ADDR, TAG0, TAG1, CFG, WRITE, MMU_HIT, CI, INVAL_L, KDET, ENDRAM, DC_ILO,
366,7 → 388,7
input [23:0] CVALID;
input [2:0] DRAMSZ;
input [31:4] ADDR;
input [27:12] TAG0,TAG1;
input [28:12] TAG0,TAG1;
input [1:0] CFG; // LDC , DC
input WRITE;
input MMU_HIT;
385,7 → 407,7
output KILL;
reg [7:0] maske;
reg [4:0] szmaske;
reg acc_dram;
wire match_0,match_1;
wire valid_0,valid_1;
392,7 → 414,7
wire select;
wire clear;
wire [7:0] update_0,update_1,lastinfo;
wire sel_dram,filter;
wire sel_dram;
always @(ADDR)
case (ADDR[6:4])
409,10 → 431,10
assign valid_0 = (( CVALID[7:0] & maske) != 8'h00);
assign valid_1 = ((CVALID[15:8] & maske) != 8'h00);
assign match_0 = ( TAG0 == ADDR[27:12] ); // 4KB
assign match_1 = ( TAG1 == ADDR[27:12] ); // 4KB
assign match_0 = ( TAG0 == ADDR[28:12] ); // 4KB
assign match_1 = ( TAG1 == ADDR[28:12] ); // 4KB
 
assign CA_HIT = ((valid_0 & match_0) | (valid_1 & match_1)) & ~DC_ILO & CFG[0];
assign CA_HIT = ((valid_0 & match_0) | (valid_1 & match_1)) & ~DC_ILO & CFG[0] & (sel_dram | KDET);
// which SET is written in cache miss ? If both are valid the last used is not taken
assign select = (valid_1 & valid_0) ? ~((CVALID[23:16] & maske) != 8'h00) : valid_0; // Last-used field = CVALID[23:16]
430,16 → 452,19
assign KILL = clear & CA_HIT & ~CFG[1]; // only if cache is not locked
always @(DRAMSZ) // Size of DRAM
casex (DRAMSZ)
3'b00x : szmaske = 5'h1F; // 8 MB 32016 Second Processor
// 3'b001 reserved for Ceres III
3'b01x : szmaske = 5'h10; // 128 MB MCUBE
default : szmaske = 5'h00; // 256 MB NetBSD
always @(DRAMSZ or ADDR) // Size of DRAM
case (DRAMSZ)
3'b000 : acc_dram = (ADDR[28:23] == 6'd0); // 8 MB 32016 Second Processor
3'b001 : acc_dram = (ADDR[28:24] == 5'd0); // 16 MB
3'b010 : acc_dram = (ADDR[28:25] == 4'd0); // 32 MB
3'b011 : acc_dram = (ADDR[28:26] == 3'd0); // 64 MB
3'b100 : acc_dram = (ADDR[28:27] == 2'd0); // 128 MB
3'b101 : acc_dram = ~ADDR[28]; // 256 MB
3'b110 : acc_dram = 1'b1; // 512 MB
3'b111 : acc_dram = ~(ADDR[28:27] == 2'b10); // 256 MB NetBSD + 128 MB
endcase
assign filter = ((ADDR[27:23] & szmaske) == 5'd0);
assign sel_dram = (ADDR[31:28] == 4'd0) & filter & ENDRAM;
assign sel_dram = (ADDR[31:29] == 3'd0) & acc_dram & ENDRAM;
assign IO_SPACE = ~sel_dram; // not DRAM or DRAM ist off
assign USE_CA = ~CI & ~DC_ILO & CFG[0] & ~CFG[1]; // CI ? ILO ? Cache on ? Locked Cache ?
449,35 → 474,39
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 7. FILTCMP Address Filter and Comparator
// 8. FILTCMP Address Filter and Comparator
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module FILTCMP ( DRAMSZ, RADR, DRAM_A, ADR_EQU, TAGDAT );
 
input [2:0] DRAMSZ;
input [27:4] RADR,DRAM_A;
input [28:4] RADR,DRAM_A;
output ADR_EQU;
output reg [27:12] TAGDAT;
output reg [28:12] TAGDAT;
 
reg [27:23] adram;
reg [28:23] adram;
always @(DRAMSZ or RADR)
casex (DRAMSZ)
3'b00x : TAGDAT = {5'd0,RADR[22:12]}; // 8 MB
3'bx10 : TAGDAT = {3'd0,RADR[24:12]}; // 32 MB
3'bx11 : TAGDAT = {2'd0,RADR[25:12]}; // 64 MB
3'b100 : TAGDAT = {1'd0,RADR[26:12]}; // 128 MB
3'b101 : TAGDAT = RADR[27:12] ; // 256 MB
3'b000 : TAGDAT = {6'd0,RADR[22:12]}; // 8 MB
3'b001 : TAGDAT = {5'd0,RADR[23:12]}; // 16 MB
3'b010 : TAGDAT = {4'd0,RADR[24:12]}; // 32 MB
3'b011 : TAGDAT = {3'd0,RADR[25:12]}; // 64 MB
3'b100 : TAGDAT = {2'd0,RADR[26:12]}; // 128 MB
3'b101 : TAGDAT = {1'b0,RADR[27:12]}; // 256 MB
3'b11x : TAGDAT = RADR[28:12] ; // 512 MB
endcase
always @(DRAMSZ or DRAM_A) // The address comparator is only used in the data cache.
casex (DRAMSZ)
3'b00x : adram = 5'd0; // 8 MB
3'bx10 : adram = {3'd0,DRAM_A[24:23]}; // 32 MB
3'bx11 : adram = {2'd0,DRAM_A[25:23]}; // 64 MB
3'b100 : adram = {1'd0,DRAM_A[26:23]}; // 128 MB
3'b101 : adram = DRAM_A[27:23] ; // 256 MB
3'b000 : adram = 6'd0; // 8 MB
3'b001 : adram = {5'd0,DRAM_A[23]}; // 16 MB
3'b010 : adram = {4'd0,DRAM_A[24:23]}; // 32 MB
3'b011 : adram = {3'd0,DRAM_A[25:23]}; // 64 MB
3'b100 : adram = {2'd0,DRAM_A[26:23]}; // 128 MB
3'b101 : adram = {1'd0,DRAM_A[27:23]}; // 256 MB
3'b11x : adram = DRAM_A[28:23] ; // 512 MB
endcase
 
assign ADR_EQU = {TAGDAT,RADR[11:4]} == {adram,DRAM_A[22:4]};
486,7 → 515,7
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 8. DCACHE_SM Data cache state machine
// 9. DCACHE_SM Data cache state machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,
508,7 → 537,7
input USE_CA;
input PTB_WR,PTB_SEL;
input SEL_PTB1;
input [27:12] CPU_OUT; // used for PTB0/1
input [28:12] CPU_OUT; // used for PTB0/1
input USER;
input PROT_ERROR;
input WB_ACC;
524,7 → 553,7
output reg DRAM_ACC,DRAM_WR;
output IO_ACC,IO_RD,IO_WR;
output PTE_MUX,PD_MUX,PKEEP;
output [27:0] PTE_ADR;
output [28:0] PTE_ADR;
output [19:0] PTE_DAT;
output HIT_ALL;
output ACC_OK;
548,7 → 577,6
reg IO_WR,IO_RD;
reg [1:0] pl_dat;
reg [6:0] new_state;
reg [2:0] cap_dat; // only for analyse of timing
reg mem_done;
reg rd_done;
reg [2:0] pstate;
555,10 → 583,9
reg pte_run_wr;
reg [1:0] prot_level1;
reg card_flag;
reg [27:12] ptb0,ptb1;
reg [28:12] ptb0,ptb1;
reg write_ok;
reg icp_acc;
reg pte_modi;
reg [2:0] ko_state;
reg dma_run;
reg dma_kdet;
566,7 → 593,7
reg prot_i;
reg rd_rdy;
wire [27:12] ptb10;
wire [28:12] ptb10;
wire [31:12] virtual_adr;
wire io_busy;
wire dram_go;
594,8 → 621,6
wire user_ptw,wr_ptw;
wire pte_puls;
always @(posedge BCLK) cap_dat <= CAPDAT[2:0];
// if USER not virtual then ZTEST is quickly done
assign zugriff = READ | WRITE | (ZTEST & VIRTUELL);
assign mmu_hit_i = MMU_HIT & ~ZTEST;
654,12 → 679,12
assign do_zt = ZTEST & ~icp_acc;
// 0 is pass , 1 is blocked. RWVAL[0] is 1 if WRVAL. Level 1 can only be blocked, otherwise ABORT or Level 2 is following.
always @(posedge BCLK) if (mem_done) rwv_bit <= level2 ? ~(cap_dat[2] & (~RWVAL[0] | cap_dat[1])) : 1'b1;
always @(posedge BCLK) if (mem_done) rwv_bit <= level2 ? ~(CAPDAT[2] & (~RWVAL[0] | CAPDAT[1])) : 1'b1;
assign RWVFLAG = VIRTUELL & rwv_bit;
assign zt_ok = mem_done & (RWVAL[1] ? (~cap_dat[2] | (RWVAL[0] & ~cap_dat[1]) | level2) // Level 2 always ok
: (cap_dat[0] & ~prot_i & level2) ); // "normal" access
assign zt_ok = mem_done & (RWVAL[1] ? (~CAPDAT[2] | (RWVAL[0] & ~CAPDAT[1]) | level2) // Level 2 always ok
: (CAPDAT[0] & ~prot_i & level2) ); // "normal" access
 
// PTE access logic, normal state machine
// Updates to the PTEs are normal WRITE request to DRAM, therefore no MDONE at Write
666,8 → 691,8
assign modi = ~CAPDAT[8] & WRITE & write_ok & ~icp_acc; // is "1" if the Modified Bit must be set
assign refer = CAPDAT[7] | do_zt; // Assumption "R" Bit is set if RDVAL/WRVAL and page border test
assign valid = (do_zt & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & cap_dat[0] & level1)
: (cap_dat[0] & ~prot_i);
assign valid = (do_zt & RWVAL[1]) ? (CAPDAT[2] & (CAPDAT[1] | ~RWVAL[0]) & CAPDAT[0] & level1)
: (CAPDAT[0] & ~prot_i);
always @(posedge BCLK) mem_done <= MDONE & pte_acc;
697,13 → 722,13
assign level1 = ~pstate[1];
assign level2 = pstate[1];
assign valid_a = (ZTEST & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & ~cap_dat[0] & level1)
: ~cap_dat[0]; // not do_zt because of icp_acc in ABORT
assign valid_a = (ZTEST & RWVAL[1]) ? (CAPDAT[2] & (CAPDAT[1] | ~RWVAL[0]) & ~CAPDAT[0] & level1)
: ~CAPDAT[0]; // not do_zt because of icp_acc in ABORT
 
assign ABORT = mem_done & valid_a & ~icp_acc;
assign PROTECT = ((mem_done & prot_i & ~icp_acc) | PROT_ERROR) & ~(ZTEST & RWVAL[1]); // no Protection-Error at RDVAL/WRVAL
 
assign IACC_STAT[1] = mem_done & ~cap_dat[0] & icp_acc;
assign IACC_STAT[1] = mem_done & ~CAPDAT[0] & icp_acc;
assign IACC_STAT[2] = level1;
assign IACC_STAT[3] = mem_done & prot_i & icp_acc;
 
801,8 → 826,8
// PTB1 and PTB0
always @(posedge BCLK) if (PTB_WR && !PTB_SEL) ptb0 <= CPU_OUT[27:12];
always @(posedge BCLK) if (PTB_WR && PTB_SEL) ptb1 <= CPU_OUT[27:12];
always @(posedge BCLK) if (PTB_WR && !PTB_SEL) ptb0 <= CPU_OUT;
always @(posedge BCLK) if (PTB_WR && PTB_SEL) ptb1 <= CPU_OUT;
always @(posedge BCLK) NEW_PTB <= PTB_WR; // to MMU Update Block
always @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;
817,12 → 842,11
assign virtual_adr = pte_sel ? IC_VA : VADR_R;
// The 2 Address-LSB's : no full access : USE_CA = 0
assign PTE_ADR = rd_level2 ? {CAPDAT[27:12],virtual_adr[21:12],2'b00} : {ptb10,virtual_adr[31:22],2'b00};
assign PTE_ADR = rd_level2 ? {CAPDAT[28:12],virtual_adr[21:12],2'b00} : {ptb10,virtual_adr[31:22],2'b00};
// PTE_DAT[8] is used for update of MMU_RAM.
assign pte_dat_8 = (level2 & WRITE & write_ok & ~icp_acc) | CAPDAT[8];
always @(posedge BCLK) pte_modi = pte_dat_8;
assign PTE_DAT = {4'h3,CAPDAT[15:9],pte_modi,1'b1,CAPDAT[6:0]}; // the top 4 bits are Byte-Enable
assign PTE_DAT = {4'h3,CAPDAT[15:9],pte_dat_8,1'b1,CAPDAT[6:0]}; // the top 4 bits are Byte-Enable
// The data for the MMU-RAM : 24 Bits , [6]=Cache Inhibit
assign MMU_DIN = {pl_dat,pte_dat_8,CAPDAT[6],CAPDAT[31:12]};
829,15 → 853,15
// Protection field
always @(posedge BCLK) if (mem_done && (pstate[2:0] == 3'd4)) prot_level1 <= cap_dat[2:1];
always @(posedge BCLK) if (mem_done && (pstate[2:0] == 3'd4)) prot_level1 <= CAPDAT[2:1];
 
always @(prot_level1 or cap_dat)
casex ({prot_level1,cap_dat[2]})
3'b11_x : pl_dat = cap_dat[2:1];
always @(prot_level1 or CAPDAT)
casex ({prot_level1,CAPDAT[2]})
3'b11_x : pl_dat = CAPDAT[2:1];
3'b10_1 : pl_dat = 2'b10;
3'b10_0 : pl_dat = cap_dat[2:1];
3'b10_0 : pl_dat = CAPDAT[2:1];
3'b01_1 : pl_dat = 2'b01;
3'b01_0 : pl_dat = cap_dat[2:1];
3'b01_0 : pl_dat = CAPDAT[2:1];
3'b00_x : pl_dat = 2'b00;
endcase
849,7 → 873,7
default : write_ok = 1'b0;
endcase
assign acc_level = level2 ? pl_dat : cap_dat[2:1];
assign acc_level = level2 ? pl_dat : CAPDAT[2:1];
assign user_ptw = icp_acc ? ICTODC[3] : USER;
assign wr_ptw = ~icp_acc & (WRITE | RMW | (ZTEST & ~RWVAL[1])); // only data cache can write
/trunk/rtl/DATENPFAD.v
1,15 → 1,16
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: DATENPFAD.v
// Version: 2.0
// History: 1.1 bug fix of 7 October 2015
// Version: 3.0 Cache Interface reworked
// History: 2.1 bug fix of 26 November 2016
// 1.1 bug fix of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
32,7 → 33,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// DATENPFAD the data path of M32632
41,7 → 42,7
 
module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, REG_OUT, PTB_SEL, PTB_WR, ACB_ZERO,
WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
 
85,7 → 86,7
output RMW;
output QWATWO;
output ACC_DONE;
output REG_OUT;
output [1:0] CTRL_QW;
output PTB_SEL;
output PTB_WR;
output reg ACB_ZERO;
118,7 → 119,7
wire [31:0] ERGEBNIS; // the result bus
wire FL;
wire [31:0] FSR;
wire [63:0] MRESULT;
wire [32:0] MRESULT;
wire [7:0] OPCODE;
wire SELI_A;
wire SELI_B;
217,19 → 218,12
 
assign SRC2 = SELI_B ? OUT_I : OUT_B;
 
MULFILTER M_FILTER(
.FLOAT(OPCODE[2]),
MULFILTER M_FILTER( // signed multiplier 32 * 32 bits = 64 bits
.BWD(BWD),
.SRC1(SRC1),
.SRC2(SRC2),
.DEST1(DEST1),
.DEST2(DEST2));
.MRESULT(MRESULT));
 
SIGNMUL S_MULTI( // signed multiplier 32 * 32 bits = 64 bits
.dataa(DEST1),
.datab(DEST2),
.result(MRESULT));
BITMASK BITM_U(
.AA(BMCODE),
.DOUT(BMASKE));
301,7 → 295,7
.SRC1(SRC1),
.SRC2(SRC2),
.SRC2SEL(ACC_FELD[1:0]),
.REG_OUT(REG_OUT),
.CTRL_QW(CTRL_QW),
.ACC_DONE(ACC_DONE),
.READ_OUT(READ_OUT),
.WRITE_OUT(WRITE_OUT),
382,7 → 376,6
.BCLK(BCLK),
.BWD(BWD),
.FSR(FSR[8:3]),
.MRESULT(MRESULT[47:0]),
.OPCODE(OPCODE),
.SRC1(SRC1),
.SRC2(SRC2),
393,7 → 386,7
.I_OUT(SFP_DAT),
.SP_CMP(SP_CMP),
.TT_SP(TT_SP),
.START(START[1]) );
.START(START[1]) ); // Aenderung
 
FP_STAT_REG FPS_REG(
.BCLK(BCLK),
402,7 → 395,7
.WREN(ENWR),
.WRADR(WRADR[5:4]),
.UP_DP(UP_DP),
.UP_SP(UP_SP),
.UP_SP(UP_SP), // & LD_OUT[1]), Aenderung
.DIN(SRC1[16:0]),
.TT_DP(TT_DP),
.TT_SP(TT_SP),
/trunk/rtl/DCACHE.v
1,15 → 1,17
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: DCACHE.v
// Version: 2.0
// History: 1.1 bug fix of 7 October 2015
// Version: 3.0 Cache Interface reworked
// History: 2.1 bug fix of November 2016
// 2.0 50 MHz release of 14 August 2016
// 1.1 bug fix of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
32,7 → 34,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// DCACHE the data cache of M32632
39,15 → 41,13
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
module DCACHE( BCLK, MCLK, WRCFG, DRAMSZ, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW,
QWATWO, WAMUX, ENWR, IC_PREQ, DMA_CHK, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR,
MCR_FLAGS, PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET,
module DCACHE( BCLK, DRAMSZ, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, CTRL_QW, PSR_USER, WRITE, READ, RMW,
QWATWO, ENWR, IC_PREQ, DMA_CHK, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR,
MCR_FLAGS, PACKET, SIZE, VADR, INHIBIT, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET,
HLDA, ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
 
input BCLK;
input MCLK;
input WRCFG;
input [2:0] DRAMSZ;
input MDONE;
input BRESET;
54,7 → 54,7
input PTB_WR;
input PTB_SEL;
input IO_READY;
input REG_OUT;
input [1:0] CTRL_QW;
input PSR_USER;
input WRITE;
input READ;
61,15 → 61,14
input ZTEST;
input RMW;
input QWATWO;
input WAMUX;
input ENWR;
input IC_PREQ;
input DMA_CHK;
input [1:0] CFG;
input [1:0] CINVAL;
input [27:4] DMA_AA;
input [28:4] DMA_AA;
input [63:0] DP_Q;
input [31:0] DRAM_Q;
input [127:0] DRAM_Q;
input [31:12] IC_VA;
input [3:0] ICTODC;
input [31:0] IO_Q;
78,8 → 77,7
input [3:0] PACKET;
input [1:0] SIZE;
input [31:0] VADR;
input [11:2] WADDR;
input [2:0] WCTRL;
input INHIBIT;
input [2:0] RWVAL;
input [40:2] DBG_IN;
input ENDRAM;
97,9 → 95,9
output [31:0] DP_DI;
output [3:1] IACC_STAT;
output [1:0] IC_SIGS;
output [27:4] KOLLI_A;
output [28:4] KOLLI_A;
output [23:0] MMU_DIN;
output reg [27:0] DRAM_A;
output reg [28:0] DRAM_A;
output reg [35:0] DRAM_DI;
output reg [31:0] IO_A;
output reg [3:0] IO_BE;
111,8 → 109,9
reg [31:0] VADR_R;
reg AUX_ALT;
reg DFF_QWEXT;
reg [11:4] KOLLI_AR;
 
wire [27:4] ADDR;
wire [28:4] ADDR;
wire ADR_EQU;
wire AUX_DAT;
wire CA_HIT;
128,7 → 127,7
wire MMU_HIT;
wire NEW_PTB;
wire PTB_ONE;
wire [27:0] PTE_ADR;
wire [28:0] PTE_ADR;
wire [31:12] RADR;
wire [11:4] TAGA;
wire [23:0] UPDATE_C;
145,13 → 144,13
wire [23:0] DAT_CV;
wire [4:0] WADR_CV;
wire WRSET0;
wire [3:0] BE_SET;
wire [31:0] DAT_SET;
wire [9:0] A_SET;
wire [15:0] BE_SET;
wire [127:0] DAT_SET;
wire [31:0] CAP_Q;
wire WRSET1;
wire SEL_PTB1;
wire CI;
wire [27:0] ADR_MX;
wire [28:0] ADR_MX;
wire LD_DRAM_A;
wire VIRTUELL;
wire NEW_PTB_RUN;
170,26 → 169,54
wire PD_MUX;
wire [19:0] PTE_DAT;
wire PKEEP;
wire XADDR2;
wire [28:12] TAGDAT;
 
// +++++++++++++++++++ Memories ++++++++++++++++++++
 
reg [7:0] DATA0_D [0:1023]; // Data Set 0 : 4 kBytes
reg [7:0] DATA0_C [0:1023];
reg [7:0] DATA0_B [0:1023];
reg [7:0] DATA0_A [0:1023];
reg [7:0] DATA0_P [0:255]; // Data Set 0 : 4 kBytes
reg [7:0] DATA0_O [0:255];
reg [7:0] DATA0_N [0:255];
reg [7:0] DATA0_M [0:255];
reg [7:0] DATA0_L [0:255]; // Data Set 0 : 4 kBytes
reg [7:0] DATA0_K [0:255];
reg [7:0] DATA0_J [0:255];
reg [7:0] DATA0_I [0:255];
reg [7:0] DATA0_H [0:255]; // Data Set 0 : 4 kBytes
reg [7:0] DATA0_G [0:255];
reg [7:0] DATA0_F [0:255];
reg [7:0] DATA0_E [0:255];
reg [7:0] DATA0_D [0:255]; // Data Set 0 : 4 kBytes
reg [7:0] DATA0_C [0:255];
reg [7:0] DATA0_B [0:255];
reg [7:0] DATA0_A [0:255];
reg [127:0] RDDATA0;
reg [31:0] SET_DAT0;
 
reg [7:0] DATA1_D [0:1023]; // Data Set 1 : 4 kBytes
reg [7:0] DATA1_C [0:1023];
reg [7:0] DATA1_B [0:1023];
reg [7:0] DATA1_A [0:1023];
reg [7:0] DATA1_P [0:255]; // Data Set 1 : 4 kBytes
reg [7:0] DATA1_O [0:255];
reg [7:0] DATA1_N [0:255];
reg [7:0] DATA1_M [0:255];
reg [7:0] DATA1_L [0:255]; // Data Set 1 : 4 kBytes
reg [7:0] DATA1_K [0:255];
reg [7:0] DATA1_J [0:255];
reg [7:0] DATA1_I [0:255];
reg [7:0] DATA1_H [0:255]; // Data Set 1 : 4 kBytes
reg [7:0] DATA1_G [0:255];
reg [7:0] DATA1_F [0:255];
reg [7:0] DATA1_E [0:255];
reg [7:0] DATA1_D [0:255]; // Data Set 1 : 4 kBytes
reg [7:0] DATA1_C [0:255];
reg [7:0] DATA1_B [0:255];
reg [7:0] DATA1_A [0:255];
reg [127:0] RDDATA1;
reg [31:0] SET_DAT1;
 
reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
reg [15:0] TAG0;
reg [16:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 17 bits
reg [16:0] TAG0;
 
reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
reg [15:0] TAG1;
reg [16:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 17 bits
reg [16:0] TAG1;
 
wire [23:0] CVALID;
 
199,15 → 226,13
reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
reg [31:0] MVALID;
 
assign ADR_EQU = ({RADR[27:12],VADR_R[11:4]} == DRAM_A[27:4]); // Limited to 256 MB
 
assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
 
assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
 
assign ADR_MX = PTE_MUX ? PTE_ADR : {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET} ;
assign ADR_MX = PTE_MUX ? PTE_ADR : {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET} ;
 
assign KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[27:4] ;
assign KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[28:4] ;
 
assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
 
215,14 → 240,8
 
assign USER = ~MCR_FLAGS[3] & PSR_USER;
 
assign DAT_SET = WRITE ? WRDATA : DRAM_Q ;
assign ADDR = KDET ? {KOLLI_A[28:12],KOLLI_AR} : {RADR[28:12],VADR_R[11:4]} ;
 
assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
 
assign ADDR = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
 
assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ;
 
assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
 
assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
236,15 → 255,19
assign ACC_STAT[4] = IO_ACC;
assign ACC_STAT[5] = CA_HIT;
 
assign XADDR2 = VADR_R[2] ^ CTRL_QW[1];
 
always @(posedge BCLK) KOLLI_AR <= KOLLI_A[11:4];
 
always @(posedge BCLK)
if (IO_ACC)
begin
IO_BE <= ENBYTE;
IO_DI <= WRDATA;
IO_A <= {RADR[31:12],VADR_R[11:0]};
IO_A <= {RADR[31:12],VADR_R[11:3],XADDR2,VADR_R[1:0]};
end
 
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= ADR_MX[27:0];
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[28:0] <= ADR_MX[28:0];
 
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
 
257,7 → 280,7
VADR_R <= VADR;
end
 
always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
 
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
 
273,31 → 296,76
 
always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
 
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
 
always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
 
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++ DIN MUX +++++++++++++++++++++++
 
WRPORT DINMUX(
.WRITE(WRITE),
.DRAM_Q(DRAM_Q),
.DADDR(DRAM_A[3:2]),
.VADDR(VADR_R[3:2]),
.WRDATA(WRDATA),
.ENBYTE(ENBYTE),
.CAP_Q(CAP_Q),
.WDAT(DAT_SET),
.ENB(BE_SET) );
// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
 
always @(posedge BCLK)
begin
SET_DAT0[31:24] <= DATA0_D[VADR[11:2]];
SET_DAT0[23:16] <= DATA0_C[VADR[11:2]];
SET_DAT0[15:8] <= DATA0_B[VADR[11:2]];
SET_DAT0[7:0] <= DATA0_A[VADR[11:2]];
RDDATA0[127:120] <= DATA0_P[VADR[11:4]];
RDDATA0[119:112] <= DATA0_O[VADR[11:4]];
RDDATA0[111:104] <= DATA0_N[VADR[11:4]];
RDDATA0[103:96] <= DATA0_M[VADR[11:4]];
RDDATA0[95:88] <= DATA0_L[VADR[11:4]];
RDDATA0[87:80] <= DATA0_K[VADR[11:4]];
RDDATA0[79:72] <= DATA0_J[VADR[11:4]];
RDDATA0[71:64] <= DATA0_I[VADR[11:4]];
RDDATA0[63:56] <= DATA0_H[VADR[11:4]];
RDDATA0[55:48] <= DATA0_G[VADR[11:4]];
RDDATA0[47:40] <= DATA0_F[VADR[11:4]];
RDDATA0[39:32] <= DATA0_E[VADR[11:4]];
RDDATA0[31:24] <= DATA0_D[VADR[11:4]];
RDDATA0[23:16] <= DATA0_C[VADR[11:4]];
RDDATA0[15:8] <= DATA0_B[VADR[11:4]];
RDDATA0[7:0] <= DATA0_A[VADR[11:4]];
end
always @(posedge MCLK)
always @(RDDATA0 or VADR_R)
case (VADR_R[3:2])
2'b00 : SET_DAT0 <= RDDATA0[31:0];
2'b01 : SET_DAT0 <= RDDATA0[63:32];
2'b10 : SET_DAT0 <= RDDATA0[95:64];
2'b11 : SET_DAT0 <= RDDATA0[127:96];
endcase
always @(posedge BCLK)
if (WRSET0)
begin
if (BE_SET[3]) DATA0_D[A_SET] <= DAT_SET[31:24];
if (BE_SET[2]) DATA0_C[A_SET] <= DAT_SET[23:16];
if (BE_SET[1]) DATA0_B[A_SET] <= DAT_SET[15:8];
if (BE_SET[0]) DATA0_A[A_SET] <= DAT_SET[7:0];
if (BE_SET[15]) DATA0_P[VADR_R[11:4]] <= DAT_SET[127:120];
if (BE_SET[14]) DATA0_O[VADR_R[11:4]] <= DAT_SET[119:112];
if (BE_SET[13]) DATA0_N[VADR_R[11:4]] <= DAT_SET[111:104];
if (BE_SET[12]) DATA0_M[VADR_R[11:4]] <= DAT_SET[103:96];
if (BE_SET[11]) DATA0_L[VADR_R[11:4]] <= DAT_SET[95:88];
if (BE_SET[10]) DATA0_K[VADR_R[11:4]] <= DAT_SET[87:80];
if (BE_SET[9]) DATA0_J[VADR_R[11:4]] <= DAT_SET[79:72];
if (BE_SET[8]) DATA0_I[VADR_R[11:4]] <= DAT_SET[71:64];
if (BE_SET[7]) DATA0_H[VADR_R[11:4]] <= DAT_SET[63:56];
if (BE_SET[6]) DATA0_G[VADR_R[11:4]] <= DAT_SET[55:48];
if (BE_SET[5]) DATA0_F[VADR_R[11:4]] <= DAT_SET[47:40];
if (BE_SET[4]) DATA0_E[VADR_R[11:4]] <= DAT_SET[39:32];
if (BE_SET[3]) DATA0_D[VADR_R[11:4]] <= DAT_SET[31:24];
if (BE_SET[2]) DATA0_C[VADR_R[11:4]] <= DAT_SET[23:16];
if (BE_SET[1]) DATA0_B[VADR_R[11:4]] <= DAT_SET[15:8];
if (BE_SET[0]) DATA0_A[VADR_R[11:4]] <= DAT_SET[7:0];
end
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
304,19 → 372,51
 
always @(posedge BCLK)
begin
SET_DAT1[31:24] <= DATA1_D[VADR[11:2]];
SET_DAT1[23:16] <= DATA1_C[VADR[11:2]];
SET_DAT1[15:8] <= DATA1_B[VADR[11:2]];
SET_DAT1[7:0] <= DATA1_A[VADR[11:2]];
RDDATA1[127:120] <= DATA1_P[VADR[11:4]];
RDDATA1[119:112] <= DATA1_O[VADR[11:4]];
RDDATA1[111:104] <= DATA1_N[VADR[11:4]];
RDDATA1[103:96] <= DATA1_M[VADR[11:4]];
RDDATA1[95:88] <= DATA1_L[VADR[11:4]];
RDDATA1[87:80] <= DATA1_K[VADR[11:4]];
RDDATA1[79:72] <= DATA1_J[VADR[11:4]];
RDDATA1[71:64] <= DATA1_I[VADR[11:4]];
RDDATA1[63:56] <= DATA1_H[VADR[11:4]];
RDDATA1[55:48] <= DATA1_G[VADR[11:4]];
RDDATA1[47:40] <= DATA1_F[VADR[11:4]];
RDDATA1[39:32] <= DATA1_E[VADR[11:4]];
RDDATA1[31:24] <= DATA1_D[VADR[11:4]];
RDDATA1[23:16] <= DATA1_C[VADR[11:4]];
RDDATA1[15:8] <= DATA1_B[VADR[11:4]];
RDDATA1[7:0] <= DATA1_A[VADR[11:4]];
end
always @(posedge MCLK)
always @(RDDATA1 or VADR_R)
case (VADR_R[3:2])
2'b00 : SET_DAT1 <= RDDATA1[31:0];
2'b01 : SET_DAT1 <= RDDATA1[63:32];
2'b10 : SET_DAT1 <= RDDATA1[95:64];
2'b11 : SET_DAT1 <= RDDATA1[127:96];
endcase
always @(posedge BCLK)
if (WRSET1)
begin
if (BE_SET[3]) DATA1_D[A_SET] <= DAT_SET[31:24];
if (BE_SET[2]) DATA1_C[A_SET] <= DAT_SET[23:16];
if (BE_SET[1]) DATA1_B[A_SET] <= DAT_SET[15:8];
if (BE_SET[0]) DATA1_A[A_SET] <= DAT_SET[7:0];
if (BE_SET[15]) DATA1_P[VADR_R[11:4]] <= DAT_SET[127:120];
if (BE_SET[14]) DATA1_O[VADR_R[11:4]] <= DAT_SET[119:112];
if (BE_SET[13]) DATA1_N[VADR_R[11:4]] <= DAT_SET[111:104];
if (BE_SET[12]) DATA1_M[VADR_R[11:4]] <= DAT_SET[103:96];
if (BE_SET[11]) DATA1_L[VADR_R[11:4]] <= DAT_SET[95:88];
if (BE_SET[10]) DATA1_K[VADR_R[11:4]] <= DAT_SET[87:80];
if (BE_SET[9]) DATA1_J[VADR_R[11:4]] <= DAT_SET[79:72];
if (BE_SET[8]) DATA1_I[VADR_R[11:4]] <= DAT_SET[71:64];
if (BE_SET[7]) DATA1_H[VADR_R[11:4]] <= DAT_SET[63:56];
if (BE_SET[6]) DATA1_G[VADR_R[11:4]] <= DAT_SET[55:48];
if (BE_SET[5]) DATA1_F[VADR_R[11:4]] <= DAT_SET[47:40];
if (BE_SET[4]) DATA1_E[VADR_R[11:4]] <= DAT_SET[39:32];
if (BE_SET[3]) DATA1_D[VADR_R[11:4]] <= DAT_SET[31:24];
if (BE_SET[2]) DATA1_C[VADR_R[11:4]] <= DAT_SET[23:16];
if (BE_SET[1]) DATA1_B[VADR_R[11:4]] <= DAT_SET[15:8];
if (BE_SET[0]) DATA1_A[VADR_R[11:4]] <= DAT_SET[7:0];
end
 
DCACHE_SM DC_SM(
345,7 → 445,7
.ADR_EQU(ADR_EQU),
.IC_PREQ(IC_PREQ),
.CAPDAT(CAPDAT[31:0]),
.CPU_OUT(DP_Q[59:44]),
.CPU_OUT(DP_Q[60:44]),
.DMA_CHK(DMA_CHK),
.IC_VA(IC_VA),
.ICTODC(ICTODC),
386,7 → 486,7
.MMU_HIT(MMU_HIT),
.WRITE(WRITE),
.KDET(KDET),
.ADDR({RADR[31:28],ADDR}),
.ADDR({RADR[31:29],ADDR}),
.CFG(CFG),
.ENDRAM(ENDRAM),
.CVALID(CVALID),
404,7 → 504,6
 
DCA_CONTROL DCA_CTRL(
.BCLK(BCLK),
.MCLK(MCLK),
.BRESET(BRESET),
.CA_SET(CA_SET),
.HIT_ALL(HIT_ALL),
414,9 → 513,10
.CUPDATE(CUPDATE),
.KILL(KILL),
.WRITE(WRITE),
.WRCFG(WRCFG),
.WCTRL(WCTRL[1:0]),
.USE_CA(DRAM_A[1]),
.INHIBIT(INHIBIT),
.INVAL_A(CINVAL[1]),
.MDONE(MDONE),
.DAT_CV(DAT_CV),
.WADR_CV(WADR_CV),
.WE_CV(WE_CV),
475,7 → 575,7
RD_ALIGNER RD_ALI(
.BCLK(BCLK),
.ACC_OK(ACC_STAT[0]),
.REG_OUT(REG_OUT),
.REG_OUT(CTRL_QW[0]),
.PACKET(PACKET),
.RDDATA(LAST_DAT),
.SIZE(SIZE),
490,7 → 590,7
.ENBYTE(ENBYTE),
.WRDATA(WRDATA));
DEBUG_AE DBGAE(
DEBUG_AE DBGAE(
.DBG_IN(DBG_IN),
.READ(READ),
.WRITE(WRITE),
501,5 → 601,12
.MMU_Q(MMU_Q[19:0]),
.ENBYTE(ENBYTE),
.DBG_HIT(DBG_HIT));
FILTCMP FILT_CMP(
.RADR({RADR[28:12],VADR_R[11:4]}),
.DRAMSZ(DRAMSZ),
.DRAM_A(DRAM_A[28:4]),
.TAGDAT(TAGDAT),
.ADR_EQU(ADR_EQU));
 
endmodule
/trunk/rtl/DECODER.v
1,14 → 1,15
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: DECODER.v
// Version: 2.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Version: 3.0
// History: 2.0 of 11 August 2016
// 1.0 first release of 30 Mai 2015
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 32,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// DECODER Instruction Decoding and Flow Control
/trunk/rtl/DP_FPU.v
1,14 → 1,15
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: DP_FPU.v
// Version: 2.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Version: 3.0
// History: 2.0 of 14 August 2016
// 1.0 of 30 Mai 2015
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 32,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. PREPDATA Prepare data for the big multiplier
/trunk/rtl/ICACHE.v
1,14 → 1,15
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ICACHE.v
// Version: 2.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Version: 3.0 Cache Interface reworked
// History: 2.0 50 MHz release of 14 August 2016
// 1.0 first release of 30 Mai 2015
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 32,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// ICACHE the instruction cache of M32632
38,13 → 39,12
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
module ICACHE( BCLK, MCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR, WADDR,
WCTRL, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR,
INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
 
input BCLK;
input MCLK;
input [2:0] DRAMSZ;
input MDONE;
input BRESET;
58,17 → 58,16
input KDET;
input HOLD;
input [1:0] CFG;
input [31:0] DRAM_Q;
input [127:0] DRAM_Q;
input [1:0] CINVAL;
input [1:0] IC_SIGS;
input [31:0] IO_Q;
input [1:0] IVAR;
input [27:4] KOLLI_A;
input [28:4] KOLLI_A;
input [3:0] MCR_FLAGS;
input [23:0] MMU_DIN;
input [31:0] VADR;
input [11:2] WADDR;
input [2:0] WCTRL;
input INHIBIT;
input ENA_HK;
input ENDRAM;
 
83,7 → 82,7
output [31:0] IC_DQ;
output [31:12] IC_VA;
output [3:0] ICTODC;
output reg [27:0] DRAM_A;
output reg [28:0] DRAM_A;
output reg [31:0] IO_A;
 
reg [31:0] VADR_R;
142,20 → 141,24
wire [23:0] NEWCVAL;
wire KILL_C,KILL_K;
wire RMW;
wire [31:0] CAP_Q;
wire [28:12] TAGDAT;
 
// +++++++++++++++++++ Memories ++++++++++++++++++++
 
reg [31:0] DATA0 [0:1023]; // Data Set 0 : 4 kBytes
reg [127:0] DATA0 [0:255]; // Data Set 0 : 4 kBytes
reg [127:0] RDDATA0;
reg [31:0] SET_DAT0;
 
reg [31:0] DATA1 [0:1023]; // Data Set 1 : 4 kBytes
reg [127:0] DATA1 [0:255]; // Data Set 1 : 4 kBytes
reg [127:0] RDDATA1;
reg [31:0] SET_DAT1;
 
reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
reg [15:0] TAG0;
reg [16:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 17 bits
reg [16:0] TAG0;
 
reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
reg [15:0] TAG1;
reg [16:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 17 bits
reg [16:0] TAG1;
 
wire [23:0] CVALID;
 
165,11 → 168,11
reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
reg [31:0] MVALID;
 
reg [15:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 16 bits
reg [15:0] KTAG0;
reg [16:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 17 bits
reg [16:0] KTAG0;
 
reg [15:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 16 bits
reg [15:0] KTAG1;
reg [16:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 17 bits
reg [16:0] KTAG1;
 
wire [23:0] KCVALID;
 
215,7 → 218,7
 
always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
 
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET};
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A <= {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET};
 
always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};
 
225,8 → 228,20
if (!BRESET) HOLD_ON <= 1'b0;
else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);
 
always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
DMUX DMUX_4TO1 (
.DRAM_Q(DRAM_Q),
.ADDR(VADR_R[3:2]),
.CAP_Q(CAP_Q) );
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
 
FILTCMP FILT_CMP(
.RADR({RADR[28:12],VADR_R[11:4]}),
.DRAMSZ(DRAMSZ),
.DRAM_A(25'd0),
.TAGDAT(TAGDAT),
.ADR_EQU());
 
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
 
NEU_VALID VALID_RAM(
241,26 → 256,42
 
always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
 
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
 
always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];
 
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
 
always @(posedge BCLK) SET_DAT0 <= DATA0[VADR[11:2]];
always @(posedge BCLK) RDDATA0 <= DATA0[VADR[11:4]];
always @(posedge MCLK) if (WRSET0) DATA0[WADDR] <= DRAM_Q;
always @(RDDATA0 or VADR_R)
case (VADR_R[3:2])
2'b00 : SET_DAT0 <= RDDATA0[31:0];
2'b01 : SET_DAT0 <= RDDATA0[63:32];
2'b10 : SET_DAT0 <= RDDATA0[95:64];
2'b11 : SET_DAT0 <= RDDATA0[127:96];
endcase
always @(posedge BCLK) if (WRSET0) DATA0[VADR_R[11:4]] <= DRAM_Q;
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
 
always @(posedge BCLK) SET_DAT1 <= DATA1[VADR[11:2]];
always @(posedge BCLK) RDDATA1 <= DATA1[VADR[11:4]];
always @(posedge MCLK) if (WRSET1) DATA1[WADDR] <= DRAM_Q;
 
always @(RDDATA1 or VADR_R)
case (VADR_R[3:2])
2'b00 : SET_DAT1 <= RDDATA1[31:0];
2'b01 : SET_DAT1 <= RDDATA1[63:32];
2'b10 : SET_DAT1 <= RDDATA1[95:64];
2'b11 : SET_DAT1 <= RDDATA1[127:96];
endcase
always @(posedge BCLK) if (WRSET1) DATA1[VADR_R[11:4]] <= DRAM_Q;
CA_MATCH DCA_COMPARE(
.INVAL_L(CINVAL[0]),
.CI(CI),
285,8 → 316,6
DCA_CONTROL DCA_CTRL(
.BCLK(BCLK),
.MCLK(1'b0),
.WRCFG(1'b1),
.BRESET(BRESET),
.CA_SET(CA_SET),
.HIT_ALL(HIT_ALL),
296,8 → 325,10
.CUPDATE(CUPDATE),
.KILL(KILL),
.WRITE(WRITE),
.WCTRL(WCTRL[1:0]),
.USE_CA(DRAM_A[1]),
.INHIBIT(INHIBIT),
.INVAL_A(CINVAL[1]),
.MDONE(MDONE),
.DAT_CV(D_CV),
.WADR_CV(A_CV),
.WE_CV(WE_CV),
347,13 → 378,13
 
always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
 
always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= RADR[27:12];
always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++ Kollision Tag Set 1 +++++++++++
 
always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];
 
always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= RADR[27:12];
always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= TAGDAT;
 
KOLDETECT KOLLOGIK(
.DRAM_WR(DRAM_WR),
/trunk/rtl/ICACHE_SM.v
1,14 → 1,14
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ICACHE_SM.v
// Version: 2.0
// Version: 3.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,11 → 31,12
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. KOLDETECT Collision Detection Unit
// 2. ICACHE_SM Instruction Cache State Machine
// 2. DMUX Data Multiplexor
// 3. ICACHE_SM Instruction Cache State Machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
51,8 → 52,8
input BRESET;
input DRAM_WR;
input [23:0] CVALID; // Data from master Valid RAM
input [27:4] ADDR;
input [27:12] TAG0,TAG1;
input [28:4] ADDR;
input [28:12] TAG0,TAG1;
input [1:0] CFG;
input [23:0] C_VALID; // Data from secondary Valid RAM
input READ_I;
71,7 → 72,7
output [2:0] ICTODC;
output STOP_CINV;
reg [27:4] addr_r;
reg [28:4] addr_r;
reg [7:0] clear;
reg do_koll;
reg [2:0] counter;
108,8 → 109,8
assign valid_0 = set_0[addr_r[6:4]];
assign valid_1 = set_1[addr_r[6:4]];
assign match_0 = ( TAG0 == addr_r[27:12] ); // 4KB
assign match_1 = ( TAG1 == addr_r[27:12] ); // 4KB
assign match_0 = ( TAG0 == addr_r[28:12] ); // 4KB
assign match_1 = ( TAG1 == addr_r[28:12] ); // 4KB
assign found_0 = valid_0 & match_0;
assign found_1 = valid_1 & match_1;
246,9 → 247,31
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. ICACHE_SM Instruction Cache State Machine
// 2. DMUX Data Multiplexor
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DMUX ( DRAM_Q, ADDR, CAP_Q );
 
input [127:0] DRAM_Q;
input [3:2] ADDR;
output reg [31:0] CAP_Q;
always @(ADDR or DRAM_Q)
case (ADDR)
2'b00 : CAP_Q = DRAM_Q[31:0];
2'b01 : CAP_Q = DRAM_Q[63:32];
2'b10 : CAP_Q = DRAM_Q[95:64];
2'b11 : CAP_Q = DRAM_Q[127:96];
endcase
endmodule
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 3. ICACHE_SM Instruction Cache State Machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
/trunk/rtl/I_PFAD.v
1,15 → 1,15
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: I_PFAD.v
// Version: 2.0
// Version: 3.0
// History: 1.1 bug fix of 7 November 2015
// 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
32,16 → 32,15
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. BITMASK Mask Generator , was a ROM on falling edge in early days
// 2. MULFILTER Filter for Multiplier Input Data
// 3. SIGNMUL Signed Multiplier for Integer Multiplication
// 4. SHIFTER Barrel Shifter for all Shift Opcodes
// 5. FFS_LOGIK Logic for FFS opcode
// 6. SCHALE Enclosure for Adder/Subtractor
// 7. I_PFAD The Integer Datapath
// 3. SHIFTER Barrel Shifter for all Shift Opcodes
// 4. FFS_LOGIK Logic for FFS opcode
// 5. SCHALE Enclosure for Adder/Subtractor
// 6. I_PFAD The Integer Datapath
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
115,50 → 114,31
// 2. MULFILTER Filter for Multiplier Input Data
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module MULFILTER (BWD, FLOAT, SRC1, SRC2, DEST1, DEST2);
module MULFILTER (BWD, SRC1, SRC2, MRESULT);
 
input [1:0] BWD;
input FLOAT;
input [31:0] SRC1,SRC2;
output [31:0] DEST1,DEST2;
input signed [31:0] SRC1,SRC2;
output [32:0] MRESULT;
 
reg [31:0] DEST1,DEST2;
wire signed [63:0] muld;
wire signed [31:0] mulw;
always @(FLOAT or BWD or SRC1)
casex ({FLOAT,BWD})
3'b0_00 : DEST1 = {{24{SRC1[7]}}, SRC1[7:0]};
3'b0_01 : DEST1 = {{16{SRC1[15]}},SRC1[15:0]};
3'b1_xx : DEST1 = { 9'h001,SRC1[22:0]};
default : DEST1 = SRC1;
endcase
always @(FLOAT or BWD or SRC2)
casex ({FLOAT,BWD})
3'b0_00 : DEST2 = {{24{SRC2[7]}}, SRC2[7:0]};
3'b0_01 : DEST2 = {{16{SRC2[15]}},SRC2[15:0]};
3'b1_xx : DEST2 = { 9'h001,SRC2[22:0]};
default : DEST2 = SRC2;
endcase
endmodule
wire no_ovf;
assign muld = SRC1 * SRC2;
assign mulw = {(BWD[0] ? SRC1[15:8] : {8{SRC1[7]}}),SRC1[7:0]} * {(BWD[0] ? SRC2[15:8] : {8{SRC2[7]}}),SRC2[7:0]};
assign no_ovf = BWD[1] ? (muld[63:32] == {32{muld[31]}})
: ( BWD[0] ? (mulw[31:16] == {16{mulw[15]}})
: (mulw[15:8] == {8{mulw[7]}}) );
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 3. SIGNMUL Signed Multiplier for Integer Multiplication
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module SIGNMUL (dataa, datab, result);
 
input signed [31:0] dataa,datab;
output signed [63:0] result;
assign MRESULT = {~no_ovf,muld[31:16],(BWD[1] ? muld[15:0] : mulw[15:0])};
assign result = dataa * datab;
endmodule
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 4. SHIFTER Barrel Shifter for all Shift Opcodes
// 3. SHIFTER Barrel Shifter for all Shift Opcodes
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);
233,7 → 213,7
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 5. FFS_LOGIK Logic for FFS opcode
// 4. FFS_LOGIK Logic for FFS opcode
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module FFS_LOGIK (SRC1, SRC2, BWD, FLAG, DOUT);
309,7 → 289,7
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 6. SCHALE Enclosure for Adder/Subtractor
// 5. SCHALE Enclosure for Adder/Subtractor
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);
351,7 → 331,7
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 7. I_PFAD The Integer Datapath
// 6. I_PFAD The Integer Datapath
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD, FL, SP_CMP, DP_CMP, LD_OUT,
362,7 → 342,7
input [31:0] SRC1,SRC2;
input [31:0] BMASKE;
input [31:0] ADDR;
input [63:0] MRESULT;
input [32:0] MRESULT;
input [7:0] OPCODE;
input [1:0] BWD;
input FL;
530,7 → 510,7
// ++++++++++++++ Overflow Detection ++++++++++++++++++++++++++++++++++++++
 
reg ovf_mul,ovf_ash;
reg ovf_ash;
wire [31:0] shdat;
always @(posedge BCLK or negedge BRESET)
540,19 → 520,12
else
if (LD_OUT)
case (OPCODE)
8'h78 : OV_FLAG <= ovf_mul;
8'h78 : OV_FLAG <= MRESULT[32];
8'h61 : OV_FLAG <= ovf_ash;
8'h40 : OV_FLAG <= over_flow & acb_reg; // ADD Opcode at ACB
default : OV_FLAG <= 1'b0;
endcase
always @(BWD or MRESULT)
casex (BWD)
2'b00 : ovf_mul = ~((MRESULT[15:7] == 9'd0) | (MRESULT[15:7] == 9'h1FF));
2'b01 : ovf_mul = ~((MRESULT[31:15] == 17'd0) | (MRESULT[31:15] == 17'h1FFFF));
default : ovf_mul = ~((MRESULT[63:31] == 33'd0) | (MRESULT[63:31] == 33'h1FFFFFFFF));
endcase
always @(BWD or SRC2 or shdat)
casex (BWD)
2'b00 : ovf_ash = (SRC2[7] != shdat[7]);
/trunk/rtl/M32632.v
1,15 → 1,17
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: M32632.v
// Version: 2.0
// History: 1.1 bug fix of 7 October 2015
// Version: 3.0 Cache Interface reworked
// History: 2.1 bug fix of 26 November 2016
// 2.0 50 MHz release of 14 August 2016
// 1.1 bug fix of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
32,7 → 34,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// M32632 The top level of M32632
39,9 → 41,9
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
module M32632( BCLK, MCLK, WRCFG, DRAMSZ, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
module M32632( BCLK, DRAMSZ, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,
ENDRAM, IC_MDONE, DC_MDONE, ENWR, WAMUX, WADDR, DRAM_Q, DWCTRL, IWCTRL,
ENDRAM, IC_MDONE, DC_MDONE, ENWR, DRAM_Q, DC_INHIBIT, IC_INHIBIT,
IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,
HOLD, HLDA, DMA_CHK, DMA_AA,
COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );
48,8 → 50,6
 
// ++++++++++ Basic Signals
input BCLK; // Basic Clock for everything
input MCLK; // Memory Clock, used in Caches
input WRCFG;
input [2:0] DRAMSZ;
input BRESET;
input NMI_N;
70,23 → 70,21
input IC_MDONE;
input DC_MDONE;
input ENWR;
input WAMUX;
input [11:2] WADDR;
input [31:0] DRAM_Q;
input [2:0] DWCTRL;
input [2:0] IWCTRL;
input [127:0] DRAM_Q;
input DC_INHIBIT;
input IC_INHIBIT;
// +++++++++ DRAM Interface Out
output IC_ACC;
output [27:0] IDRAM_ADR;
output [28:0] IDRAM_ADR;
output DC_ACC;
output DC_WR;
output [27:0] DRAM_ADR;
output [28:0] DRAM_ADR;
output [35:0] DRAM_DI;
// ++++++++++ DMA Interface
input HOLD;
output HLDA;
input DMA_CHK;
input [27:4] DMA_AA;
input [28:4] DMA_AA;
// ++++++++++ Coprocessor Interface
output COP_GO;
output [23:0] COP_OP;
116,7 → 114,7
wire [6:0] INFO_AU;
wire [1:0] IVAR;
wire KDET;
wire [27:4] KOLLI_A;
wire [28:4] KOLLI_A;
wire [3:0] MCR;
wire [23:0] MMU_DIN;
wire [11:0] PSR;
131,7 → 129,7
wire RWVFLAG;
wire [3:0] D_IOBE;
wire D_IORDY;
wire REG_OUT;
wire [1:0] CTRL_QW;
wire [3:0] PACKET;
wire [1:0] SIZE;
wire [31:0] VADR;
180,9 → 178,7
// The Data Cache
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
DCACHE ARMS(
.MCLK(MCLK),
.BCLK(BCLK),
.WRCFG(WRCFG),
.DRAMSZ(DRAMSZ),
.BRESET(BRESET),
.PTB_WR(PTB_WR),
189,7 → 185,7
.PTB_SEL(PTB_SEL),
.MDONE(DC_MDONE),
.IO_READY(D_IORDY),
.REG_OUT(REG_OUT),
.CTRL_QW(CTRL_QW),
.PSR_USER(INFO_AU[1]),
.WRITE(WRITE),
.READ(READ),
196,7 → 192,6
.ZTEST(ZTEST),
.RMW(RMW),
.QWATWO(QWATWO),
.WAMUX(WAMUX),
.ENWR(ENWR),
.IC_PREQ(IC_PREQ),
.DMA_CHK(DMA_CHK),
214,8 → 209,7
.PACKET(PACKET),
.SIZE(SIZE),
.VADR(VADR),
.WADDR(WADDR),
.WCTRL(DWCTRL),
.INHIBIT(DC_INHIBIT),
.DRAM_ACC(DC_ACC),
.DRAM_WR(DC_WR),
.IO_RD(D_IORD),
276,7 → 270,7
.RMW(RMW),
.QWATWO(QWATWO),
.ACC_DONE(ACC_DONE),
.REG_OUT(REG_OUT),
.CTRL_QW(CTRL_QW),
.Y_INIT(Y_INIT),
.DONE(DONE),
.PTB_WR(PTB_WR),
309,7 → 303,6
// The Instruction Cache
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ICACHE LEGS(
.MCLK(MCLK),
.BCLK(BCLK),
.DRAMSZ(DRAMSZ),
.BRESET(BRESET),
334,8 → 327,7
.MCR_FLAGS(MCR),
.MMU_DIN(MMU_DIN),
.VADR(PC_ICACHE),
.WADDR(WADDR),
.WCTRL(IWCTRL),
.INHIBIT(IC_INHIBIT),
.DRAM_ACC(IC_ACC),
.IO_RD(I_IORD),
.INIT_RUN(IC_INIT),
/trunk/rtl/REGISTERS.v
1,14 → 1,14
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: REGISTERS.v
// Version: 2.0
// Version: 3.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 31,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. CONFIG_REGS Configuration and Debug Registers
/trunk/rtl/SP_FPU.v
1,14 → 1,14
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: SP_FPU.v
// Version: 2.0
// Version: 3.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 31,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Testversion mit Pipeline Register in SFPU_ADDSUB **************
//
347,32 → 347,34
// 3. SFPU_MUL Single Precision Floating Point Multiplier
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module SFPU_MUL ( BCLK, SRC1, SRC2, MRESULT, NZEXP, OUT);
module SFPU_MUL ( BCLK, SRC1, SRC2, NZEXP, OUT);
 
input BCLK;
input [31:0] SRC1,SRC2; // only exponent of input data used
input [47:0] MRESULT;
input [2:1] NZEXP; // Flags of input data
output reg [36:0] OUT; // The result
 
wire [9:0] exponent,expoh,expol;
wire [1:0] restlow,resthigh;
wire zero,sign,orlow;
wire [47:0] mresult;
wire [9:0] exponent,expoh,expol;
wire [1:0] restlow,resthigh;
wire zero,sign,orlow;
assign mresult = {1'b1,SRC1[22:0]} * {1'b1,SRC2[22:0]}; // Unsigned Multiplier
 
assign zero = ~NZEXP[2] | ~NZEXP[1]; // one of both NULL -> NULL is the result
assign sign = (SRC1[31] ^ SRC2[31]) & ~zero;
assign orlow = (MRESULT[21:0] != 22'b0);
assign orlow = (mresult[21:0] != 22'b0);
assign restlow = {MRESULT[22],orlow};
assign resthigh = {MRESULT[23],(MRESULT[22] | orlow)};
assign restlow = {mresult[22],orlow};
assign resthigh = {mresult[23],(mresult[22] | orlow)};
assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
assign expoh = exponent - 10'h07E;
assign expol = exponent - 10'h07F; // for MSB if MRESULT=0
assign expol = exponent - 10'h07F; // for MSB if mresult=0
always @(posedge BCLK) OUT <= MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
: {zero,sign,expol,MRESULT[45:23],restlow};
always @(posedge BCLK) OUT <= mresult[47] ? {zero,sign,expoh,mresult[46:24],resthigh}
: {zero,sign,expol,mresult[45:23],restlow};
endmodule
 
381,7 → 383,7
// 4. SP_FPU Top Level of Single Precision Floating Point Unit
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module SP_FPU (BCLK, START, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
module SP_FPU (BCLK, START, OPCODE, SRC1, SRC2, FSR, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
 
input BCLK; // is not used !
input START;
388,7 → 390,6
input [7:0] OPCODE;
input [31:0] SRC1,SRC2; // Input data
input [8:3] FSR; // Floating Point Status Register
input [47:0] MRESULT; // Multiplier result
input [1:0] BWD; // Size of integer
input FL;
 
445,7 → 446,7
.SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
// 100 : MULF
SFPU_MUL IMUL ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .MRESULT(MRESULT), .OUT(mulout), .NZEXP(nzexp) );
SFPU_MUL IMUL ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .OUT(mulout) );
// FP - Pfad : selection of result and rounding :
 
/trunk/rtl/STEUERUNG.v
1,14 → 1,13
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: STEUERUNG.v
// Version: 2.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Version: 3.0
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 30,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// STEUERUNG The control logic of M32632
/trunk/rtl/STEUER_MISC.v
1,14 → 1,14
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: STEUER_MISC.v
// Version: 2.0
// Version: 3.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 31,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. OPDEC_REG Central Instruction Register
/trunk/rtl/TOP_MISC.v
1,14 → 1,14
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: TOP_MISC.v
// Version: 2.0
// Version: 3.0
// History: 1.0 first release of 30 Mai 2015
// Date: 14 August 2016
// Date: 2 December 2018
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
31,7 → 31,7
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
107,7 → 107,7
assign IO_BE = sel_dp ? D_IOBE : 4'b1111; // Instruction read always 32 Bit
assign D_IORDY = sel_dp & IO_READY;
assign I_IORDY = ~sel_dp & IO_READY;
assign I_IORDY = ~sel_dp & IO_READY & I_IORD;
 
assign interrupt = GENSTAT[1] | GENSTAT[0];

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