Subversion Repositories pdp8

/trunk/de0_nano/pdp8_top.qpf

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/trunk/de0_nano/pdp8_top.sof

trunk/de0_nano/pdp8_top.sof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/de0_nano/pdp8_top.qsf =================================================================== --- trunk/de0_nano/pdp8_top.qsf (nonexistent) +++ trunk/de0_nano/pdp8_top.qsf (revision 5) @@ -0,0 +1,294 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2011 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 11.1 Build 173 11/01/2011 SJ Full Version +# Date created = 19:28:47 October 30, 2013 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# pdp8_top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name TOP_LEVEL_ENTITY pdp8_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:28:47 OCTOBER 30, 2013" +set_global_assignment -name LAST_QUARTUS_VERSION 11.1 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VHDL_FILE ../pdp8/uart/uart_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/uart/uart_tx.vhd +set_global_assignment -name VHDL_FILE ../pdp8/uart/uart_rx.vhd +set_global_assignment -name VHDL_FILE ../pdp8/uart/uart_brg.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e/sdspi_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e/sdspi.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e/sd_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e/sd.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e/rk05_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e/rk05.vhd +set_global_assignment -name VHDL_FILE ../pdp8/kl8e/kl8e_tx.vhd +set_global_assignment -name VHDL_FILE ../pdp8/kl8e/kl8e_rx.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/xma.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/usrtrp.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/uf.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/ub.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/sr.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/sp.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/sf.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/sc.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/pwrtrp.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/pnltrp.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/pex.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/pdf.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/pc.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/mqa.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/mq.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/mb.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/ma.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/ir.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/ii.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/if.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/ie.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/id.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/ib.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/hlttrp.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/gtf.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/fz.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/emode.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/eae.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/df.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/ctrlff.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/cpu_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/cpu.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/btstrp.vhd +set_global_assignment -name VHDL_FILE ../pdp8/cpu/alu.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/rk8e.vhd +set_global_assignment -name VHDL_FILE ../pdp8/pr8e_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/pr8e.vhd +set_global_assignment -name VHDL_FILE ../pdp8/pdp8.vhd +set_global_assignment -name VHDL_FILE ../pdp8/ms8c.vhd +set_global_assignment -name VHDL_FILE ../pdp8/ls8e_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/ls8e.vhd +set_global_assignment -name VHDL_FILE ../pdp8/kl8e_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/kl8e.vhd +set_global_assignment -name VHDL_FILE ../pdp8/kc8e_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/kc8e.vhd +set_global_assignment -name VHDL_FILE ../pdp8/dk8e_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/dk8e.vhd +set_global_assignment -name VHDL_FILE ../pdp8/dev_types.vhd +set_global_assignment -name VHDL_FILE ../pdp8/busmux.vhd +set_global_assignment -name VHDL_FILE ../pdp8/busmon.vhd +set_global_assignment -name VHDL_FILE pdp8_top.vhd +set_global_assignment -name VHDL_FILE oct_7seg.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_R8 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_location_assignment PIN_A15 -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_location_assignment PIN_A13 -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_location_assignment PIN_B13 -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_location_assignment PIN_A11 -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_location_assignment PIN_D1 -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_location_assignment PIN_F3 -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_location_assignment PIN_B1 -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_location_assignment PIN_L3 -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_J15 -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_location_assignment PIN_E1 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_M1 -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_location_assignment PIN_T8 -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_location_assignment PIN_B9 -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_location_assignment PIN_M15 -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_H2 -to EPCS_DATA0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0 +set_location_assignment PIN_H1 -to EPCS_DCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK +set_location_assignment PIN_D2 -to EPCS_NCSO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO +set_location_assignment PIN_C1 -to EPCS_ASDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO +set_location_assignment PIN_A8 -to U6A_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A_IN[0] +set_location_assignment PIN_D3 -to U6A[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[0] +set_location_assignment PIN_B8 -to U6A_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A_IN[1] +set_location_assignment PIN_C3 -to U6A[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[1] +set_location_assignment PIN_A2 -to U6A[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[2] +set_location_assignment PIN_A3 -to U6A[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[3] +set_location_assignment PIN_B3 -to U6A[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[4] +set_location_assignment PIN_B4 -to U6A[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[5] +set_location_assignment PIN_A4 -to U6A[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[6] +set_location_assignment PIN_B5 -to U6A[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[7] +set_location_assignment PIN_A5 -to U6A[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[8] +set_location_assignment PIN_D5 -to U6A[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[9] +set_location_assignment PIN_B6 -to U6A[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[10] +set_location_assignment PIN_B7 -to U6A[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[12] +set_location_assignment PIN_A7 -to U6A[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[14] +set_location_assignment PIN_C8 -to U6A[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[16] +set_location_assignment PIN_E7 -to U6A[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[18] +set_location_assignment PIN_C9 -to U6A[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to U6A[24] +set_location_assignment PIN_P11 -to TTY1_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TTY1_RXD +set_location_assignment PIN_C6 -to TTY2_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TTY2_TXD +set_location_assignment PIN_E6 -to TTY2_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TTY2_RXD +set_location_assignment PIN_D8 -to LPR_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LPR_TXD +set_location_assignment PIN_F8 -to LPR_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LPR_RXD +set_location_assignment PIN_E9 -to LPR_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LPR_CTS +set_location_assignment PIN_D9 -to LPR_RTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LPR_RTS +set_location_assignment PIN_E10 -to PTR_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PTR_TXD +set_location_assignment PIN_B11 -to PTR_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PTR_RXD +set_location_assignment PIN_D11 -to PTR_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PTR_CTS +set_location_assignment PIN_B12 -to PTR_RTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PTR_RTS +set_location_assignment PIN_E8 -to USB_CLK_12MHZ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_CLK_12MHZ +set_location_assignment PIN_J16 -to RESET +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET +set_location_assignment PIN_E11 -to fpMISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpMISO +set_location_assignment PIN_K15 -to fpMOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpMOSI +set_location_assignment PIN_J13 -to fpFS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpFS +set_location_assignment PIN_J14 -to fpSCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpSCLK +set_location_assignment PIN_T9 -to swLOCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swLOCK +set_location_assignment PIN_F13 -to swCONT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swCONT +set_location_assignment PIN_R9 -to swBOOT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swBOOT +set_location_assignment PIN_T15 -to swEXAM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swEXAM +set_location_assignment PIN_T14 -to swLDADDR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swLDADDR +set_location_assignment PIN_T13 -to swHALT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swHALT +set_location_assignment PIN_R13 -to swLDEXTD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swLDEXTD +set_location_assignment PIN_T12 -to swSTEP +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swSTEP +set_location_assignment PIN_T11 -to swDEP +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swDEP +set_location_assignment PIN_T10 -to swD1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD2 +set_location_assignment PIN_R10 -to swROT1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT1 +set_location_assignment PIN_P9 -to swROT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT2 +set_location_assignment PIN_N11 -to swROT3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT3 +set_location_assignment PIN_N9 -to swD4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD4 +set_location_assignment PIN_L16 -to swD5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD5 +set_location_assignment PIN_K16 -to swROT4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT4 +set_location_assignment PIN_R16 -to swD6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD6 +set_location_assignment PIN_L15 -to swROT5 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT5 +set_location_assignment PIN_P15 -to swD7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD7 +set_location_assignment PIN_P16 -to swROT6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT6 +set_location_assignment PIN_R14 -to swROT7 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swROT7 +set_location_assignment PIN_L14 -to sdCS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdCS +set_location_assignment PIN_N15 -to swD8 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD8 +set_location_assignment PIN_M10 -to sdCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD9 +set_location_assignment PIN_N14 -to sdDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD10 +set_location_assignment PIN_L13 -to sdDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD11 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdCD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdCLEAR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdWP +set_location_assignment PIN_R12 -to swD0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swD0 +set_location_assignment PIN_R11 -to TTY1_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TTY1_TXD +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: trunk/de0_nano/oct_7seg.vhd =================================================================== --- trunk/de0_nano/oct_7seg.vhd (nonexistent) +++ trunk/de0_nano/oct_7seg.vhd (revision 5) @@ -0,0 +1,33 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +entity oct_7seg is + port ( + CLOCK_50 : in std_logic; + oct_digit : in std_logic_vector(2 downto 0); + seg : buffer std_logic_vector(6 downto 0) + ); +end oct_7seg; + +architecture rtl of oct_7seg is +begin + process(CLOCK_50) + begin +-- seg = {g,f,e,d,c,b,a}; +-- 0 is on and 1 is off + + case oct_digit is + when "000" => seg <= B"1000000"; + when "001" => seg <= B"1111001"; + when "010" => seg <= B"0100100"; + when "011" => seg <= B"0110000"; + when "100" => seg <= B"0011001"; + when "101" => seg <= B"0010010"; + when "110" => seg <= B"0000010"; + when "111" => seg <= B"1111000"; + when others => seg <= B"0000000"; + end case; + end process; +end rtl; Index: trunk/de0_nano/pdp8_top.vhd =================================================================== --- trunk/de0_nano/pdp8_top.vhd (nonexistent) +++ trunk/de0_nano/pdp8_top.vhd (revision 5) @@ -0,0 +1,430 @@ +--! +--! DE0-Nano PDP-8 Processor +--! +--! \brief +--! PDP-8 implementation for the DE0-Nano board +--! +--! \details +--! +--! \file +--! pdp8_top.vhd +--! +--! \author +--! Joe Manojlovich - joe.manojlovich (at) gmail (dot) com +--! +-------------------------------------------------------------------- +-- +-- Copyright (C) 2012 Joe Manojlovich +-- +-- This source file may be used and distributed without +-- restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains +-- the original copyright notice and the associated disclaimer. +-- +-- This source file is free software; you can redistribute it +-- and/or modify it under the terms of the GNU Lesser General +-- Public License as published by the Free Software Foundation; +-- version 2.1 of the License. +-- +-- This source is distributed in the hope that it will be +-- useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +-- PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General +-- Public License along with this source; if not, download it +-- from http://www.gnu.org/licenses/lgpl.txt +-- +-------------------------------------------------------------------- +-- +-- Comments are formatted for doxygen +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +use ieee.numeric_std; +use work.uart_types.all; --! UART Types +use work.dk8e_types.all; --! DK8E Types +use work.kc8e_types.all; --! KC8E Types +use work.kl8e_types.all; --! KL8E Types +use work.rk8e_types.all; --! RK8E Types +use work.rk05_types.all; --! RK05 Types +use work.ls8e_types.all; --! LS8E Types +use work.pr8e_types.all; --! PR8E Types +use work.cpu_types.all; --! CPU Types +use work.sd_types.all; --! SD Types +use work.sdspi_types.all; --! SPI Types +use work.oct_7seg; + +ENTITY pdp8_top IS + generic( + invert_reset : std_logic := '0' -- 0 : not invert, 1 invert + ); + + PORT ( + SW : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => 'Z'); --! Toggle switches + KEY : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => 'Z'); --! Push buttons + CLOCK_50 : IN STD_LOGIC; --! Input clock + LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => 'Z'); --! Output green LEDs + + TTY1_TXD : OUT STD_LOGIC; --! UART send line + TTY1_RXD : IN STD_LOGIC; --! UART receive line + TTY2_TXD : OUT STD_LOGIC; --! UART send line + TTY2_RXD : IN STD_LOGIC; --! UART receive line + LPR_TXD : OUT STD_LOGIC; --! LPR send line + LPR_RXD : IN STD_LOGIC; --! LPR receive line + LPR_CTS : IN STD_LOGIC; + LPR_RTS : OUT STD_LOGIC; + PTR_TXD : OUT STD_LOGIC; + PTR_RXD : IN STD_LOGIC; + PTR_CTS : IN STD_LOGIC; + PTR_RTS : OUT STD_LOGIC; + USB_CLK_12MHZ : OUT STD_LOGIC; -- FIXME + RESET : OUT STD_LOGIC; + fpMISO : IN STD_LOGIC; + fpMOSI : OUT STD_LOGIC; + fpFS : OUT STD_LOGIC; + fpSCLK : OUT STD_LOGIC; + + swLOCK : IN STD_LOGIC; + swCONT : IN STD_LOGIC; + swBOOT : IN STD_LOGIC; + swEXAM : IN STD_LOGIC; + swLDADDR : IN STD_LOGIC; + swHALT : IN STD_LOGIC; + swLDEXTD : IN STD_LOGIC; + swSTEP : IN STD_LOGIC; + swD0 : IN STD_LOGIC; + swDEP : IN STD_LOGIC; + swD1 : IN STD_LOGIC; + swROT0 : IN STD_LOGIC; + swD2 : IN STD_LOGIC; + swROT1 : IN STD_LOGIC; + swD3 : IN STD_LOGIC; + swROT2 : IN STD_LOGIC; + swD4 : IN STD_LOGIC; + swROT3 : IN STD_LOGIC; + swD5 : IN STD_LOGIC; + swROT4 : IN STD_LOGIC; + swD6 : IN STD_LOGIC; + swROT5 : IN STD_LOGIC; + swD7 : IN STD_LOGIC; + swROT6 : IN STD_LOGIC; + swROT7 : IN STD_LOGIC; + sdCS : OUT STD_LOGIC; --! SD card chip select + swD8 : IN STD_LOGIC; + sdCLK : OUT STD_LOGIC; --! SD card clock + swD9 : IN STD_LOGIC; + sdDI : OUT STD_LOGIC; --! SD card master out slave in + swD10 : IN STD_LOGIC; + sdDO : IN STD_LOGIC; --! SD card master in slave out + swD11 : IN STD_LOGIC; + sdCD: IN STD_LOGIC; + swCLEAR : IN STD_LOGIC; + swWP : IN STD_LOGIC + + ); +END pdp8_top; + + architecture rtl of pdp8_top is + signal rk8eSTAT : rk8eSTAT_t; + signal swCNTL : swCNTL_t := (others => '0'); --! Front Panel Control Switches + signal swROT : swROT_t := dispIR; --! Front panel rotator switch + signal swOPT : swOPT_t; --! PDP-8 options\ + signal swDATA : swDATA_t; --! Front panel switches + signal ledDATA : data_t; + + signal dly: std_logic := '0'; --! Delay used for reset logic + signal rst: std_logic := '0'; --! Internal reset line + signal int_reset : std_logic; --! Initial reset line + signal rst_out : std_logic; --! Reset line output to PDP-8 + + constant max_count : natural := 24000; + signal op : std_logic; + + type display_type is (S0, S1, S2, S3, S4, S5); + signal state: display_type := S0; + signal i : integer range 0 to 32 := 0; + --signal i : std_logic_vector(7 downto 0) := (others => '0'); + signal data7 : std_logic_vector(31 downto 0); -- := X"fa00fa00"; -- (others => '0'); + + +begin + + swOPT.KE8 <= '1'; + swOPT.KM8E <= '1'; + swOPT.TSD <= '1'; + swOPT.STARTUP <= '1'; -- Setting the 'STARTUP' bit will cause the PDP8 to boot + -- to the address in the switch register + + int_reset <= '0'; + + ---------------------------------------------------------------------------- + -- RESET signal generator. + ---------------------------------------------------------------------------- + process(CLOCK_50) + begin + if(rising_edge(CLOCK_50)) then + dly <= ( not(int_reset) and dly and not(rst) ) + or ( not(int_reset) and not(dly) and rst ); + rst <= ( not(int_reset) and not(dly) and not(rst) ); + end if; + end process; + + rst_out <= rst xor invert_reset ; + + -- + -- Front Panel Data Switches + -- + + swDATA <= o"0023"; + --swDATA <= o"7400"; + + compteur : process(CLOCK_50, rst_out) + variable count : natural range 0 to max_count := 0; + begin + if rising_edge(CLOCK_50) then + if count < max_count/2 then + op <='1'; + count := count + 1; + elsif count < max_count then + op <='0'; + count := count + 1; + else + count := 0; + op <='1'; + end if; + end if; + end process compteur; + + -- LED(6) <= op; + + ---------------------------------------------------------------------------- + -- Display toggle switch (stand in for rotator switch) + --------------------------------------------------------------------------- + toggle_switch : process(CLOCK_50) + begin + if rising_edge(KEY(0)) then + swROT <= swROT + 1; + end if; + end process toggle_switch; + + + display : process(CLOCK_50) + begin + + if rising_edge(CLOCK_50) then + + if op = '1' + then + state <= S1; + i <= 0; + RESET <= '1'; + end if; + +-- if state = S0 +-- then +-- LED(1) <= '1'; +-- LED(2) <= '1'; +-- LED(3) <= '1'; +-- LED(4) <= '1'; +-- LED(5) <= '1'; +-- end if; + + if state = S1 + then + fpFS <= '0'; + state <= S2; + +-- LED(1) <= '1'; +-- LED(2) <= '0'; +-- LED(3) <= '0'; +-- LED(4) <= '0'; +-- LED(5) <= '0'; + end if; + + if state = S2 + then +-- LED(1) <= '0'; +-- LED(2) <= '1'; +-- LED(3) <= '0'; +-- LED(4) <= '0'; +-- LED(5) <= '0'; + + if i = 32 + then + state <= S5; + else + fpSCLK <= '0'; + state <= S3; + end if; + end if; + + if state = S3 + then + fpMOSI <= data7(31 - i); + i <= i + 1; + state <= S4; + +-- LED(1) <= '0'; +-- LED(2) <= '0'; +-- LED(3) <= '1'; +-- LED(4) <= '0'; +-- LED(5) <= '0'; + end if; + + if state = S4 + then + fpSCLK <= '1'; + state <= S2; + +-- LED(1) <= '0'; +-- LED(2) <= '0'; +-- LED(3) <= '0'; +-- LED(4) <= '1'; +-- LED(5) <= '0'; + end if; + + if state = S5 + then + fpFS <= '1'; + state <= S0; + +-- LED(1) <= '0'; +-- LED(2) <= '0'; +-- LED(3) <= '0'; +-- LED(4) <= '0'; +-- LED(5) <= '1'; + end if; + end if; + +end process display; + + ---------------------------------------------------------------------------- + -- PDP8 Processor + --------------------------------------------------------------------------- + iPDP8 : entity work.ePDP8 (rtl) port map ( + -- System + clk => CLOCK_50, --! 50 MHz Clock + rst => rst_out, --! Reset Button + -- CPU Configuration + swCPU => swPDP8A, --! CPU Configured to emulate PDP8A + swOPT => swOPT, --! Enable Options + -- Real Time Clock Configuration + swRTC => clkDK8EC2, --! RTC 50 Hz interrupt + -- TTY1 Interfaces + tty1BR => uartBR9600, --! TTY1 is 9600 Baud + tty1HS => uartHSnone, --! TTY1 has no flow control + tty1CTS => '1', --! TTY1 doesn't need CTS + tty1RTS => open, --! TTY1 doesn't need RTS + tty1RXD => TTY1_RXD, --! TTY1 RXD (to RS-232 interface) + tty1TXD => TTY1_TXD, --! TTY1 TXD (to RS-232 interface) + -- TTY2 Interfaces + tty2BR => uartBR9600, --! TTY2 is 9600 Baud + tty2HS => uartHSnone, --! TTY2 has no flow control + tty2CTS => '1', --! TTY2 doesn't need CTS + tty2RTS => open, --! TTY2 doesn't need RTS + tty2RXD => '1', --! TTY2 RXD (tied off) + tty2TXD => open, --! TTY2 TXD (tied off) + -- LPR Interface + lprBR => uartBR9600, --! LPR is 9600 Baud + lprHS => uartHSnone, --! LPR has no flow control + lprDTR => '1', --! LPR doesn't need DTR + lprDSR => open, --! LPR doesn't need DSR + lprRXD => '1', --! LPR RXD (tied off) + lprTXD => open, --! LPR TXD (tied off) + -- Paper Tape Reader Interface + ptrBR => uartBR9600, --! PTR is 9600 Baud + ptrHS => uartHSnone, --! PTR has no flow control + ptrCTS => '1', --! PTR doesn't need CTS + ptrRTS => open, --! PTR doesn't need RTS + ptrRXD => '1', --! PTR RXD (tied off) + ptrTXD => open, --! PTR TXD (tied off) + -- Secure Digital Disk Interface + sdCD => '0', --! SD Card Detect + sdWP => '0', --! SD Write Protect + sdMISO => sdDO, --! SD Data In + sdMOSI => sdDI, --! SD Data Out + sdSCLK => sdCLK, --! SD Clock + sdCS => sdCS, --! SD Chip Select + -- Status + rk8eSTAT => rk8eSTAT, --! Disk Status (Ignore) + -- Switches and LEDS + swROT => swROT, --! Data LEDS display PC + swDATA => swDATA, --! RK8E Boot Loader Address + swCNTL => swCNTL, --! Switches + ledRUN => LED(7), --! Run LED + ledDATA => ledDATA, --! Data output register + ledADDR => open --! Address output register + ); + + --data7(7 downto 0) <= rk8eSTAT.sdSTAT.state; + --data7(15 downto 8) <= rk8eSTAT.sdSTAT.err; + --data7(23 downto 16) <= rk8eSTAT.sdSTAT.val; + --data7(31 downto 24) <= rk8eSTAT.sdSTAT.debug; + +-- digit1 : entity hex_7seg port map ( +-- CLOCK_50 => CLOCK_50, +-- hex_digit => rk8eSTAT.sdSTAT.debug(4 to 7), +-- seg => data7(13 downto 7) +-- ); +-- +-- digit2 : entity hex_7seg port map ( +-- CLOCK_50 => CLOCK_50, +-- hex_digit => rk8eSTAT.sdSTAT.debug(0 to 3), +-- seg => data7(6 downto 0) +-- ); +-- +-- digit3 : entity hex_7seg port map ( +-- CLOCK_50 => CLOCK_50, +-- hex_digit => rk8eSTAT.sdSTAT.err(4 to 7), +-- seg => data7(20 downto 14) +-- ); +-- +-- digit4 : entity hex_7seg port map ( +-- CLOCK_50 => CLOCK_50, +-- hex_digit => rk8eSTAT.sdSTAT.err(0 to 3), +-- seg => data7(27 downto 21) +-- ); + + +-- digit3 : entity oct_7seg port map ( +-- CLOCK_50 => CLOCK_50, +-- oct_digit => ledDATA(3 to 5), +-- seg => data7(13 downto 7) +-- ); +-- +-- digit4 : entity oct_7seg port map ( +-- CLOCK_50 => CLOCK_50, +-- oct_digit => ledDATA(0 to 2), +-- seg => data7(6 downto 0) +-- ); + + digit1 : entity oct_7seg port map ( + CLOCK_50 => CLOCK_50, + oct_digit => ledDATA(9 to 11), + seg => data7(27 downto 21) + ); + + digit2 : entity oct_7seg port map ( + CLOCK_50 => CLOCK_50, + oct_digit => ledDATA(6 to 8), + seg => data7(20 downto 14) + ); + + digit3 : entity oct_7seg port map ( + CLOCK_50 => CLOCK_50, + oct_digit => ledDATA(3 to 5), + seg => data7(13 downto 7) + ); + + digit4 : entity oct_7seg port map ( + CLOCK_50 => CLOCK_50, + oct_digit => ledDATA(0 to 2), + seg => data7(6 downto 0) + ); + +end rtl;