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trunk/DOC/fft128_um.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/TB/FFT128_TB.v =================================================================== --- trunk/TB/FFT128_TB.v (nonexistent) +++ trunk/TB/FFT128_TB.v (revision 2) @@ -0,0 +1,169 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Testbench for the FFT128_core - FFT 128 processor +// FUNCTION: a set of 4 sine waves is inputted to the FFT processor, +// the results are compared with the expected waves, +// the square root mean error is calculated (without a root) +// FILES: FFT128_TB.v - this file, contains +// FFT128.v - unit under test +// Wave_ROM128.v - rom with the test waveform, generating by +// sinerom128_gen.pl script +// PROPERTIES: 1) the calculated error after ca. 6us modeling +// is outputted to the console as the note: +// rms error is 1 lsb +// 2)if the error is 0,1,2 then the test is OK +// 3) the customer can exchange the test selecting the +// different frequencies and generating the wave ROM by +// the script sinerom128_gen.pl +// 4) the proper operation can be checked by investigation +// of the core output waveforms +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`include "FFT128_CONFIG.inc" + +`timescale 1ns / 1 ps +module FFT128_tb; + //Parameters declaration: + `FFT128paramnb + + //Internal signals declarations: + reg CLK; + reg RST; + reg ED; + reg START; + reg [3:0]SHIFT; + wire [nb-1:0]DR; + wire [nb-1:0]DI; + wire RDY; + wire OVF1; + wire OVF2; + wire [6:0]ADDR; + wire signed [nb+3:0]DOR; + wire signed [nb+3:0]DOI; + + initial + begin + CLK = 1'b0; + forever #5 CLK = ~CLK; + end + + initial + begin + SHIFT = 4'b0000; + ED = 1'b1; + RST = 1'b0; + START = 1'b0; + #13 RST =1'b1; + #43 RST =1'b0; + #53 START =1'b1; + #12 START =1'b0; + end + + //initial //ED testing +// begin +// #1 ED = 1'b0; +// forever #10 ED = ~ED; +// end + + reg [6:0] ct128; + always @(posedge CLK or posedge START) + if (ED) begin + if (START) ct128 = 7'b000_0000; + else ct128 = ct128+ 'd1; + end + + wire [15:0] D_R,D_I,DATA_0; + Wave_ROM128 UG( .ADDR(ct128) , + .DATA_RE(D_R), .DATA_IM(D_I), .DATA_REF(DATA_0) );// + + assign DR=(D_R[15]&&(nb!=16))? (D_R[15:15-nb+1]+1) : D_R[15:15-nb+1]; + assign DI=(D_I[15]&&(nb!=16))? (D_I[15:15-nb+1]+1) : D_I[15:15-nb+1]; + + // Unit Under Test + FFT128 UUT ( + .CLK(CLK), + .RST(RST), + .ED(ED), + .START(START), + .SHIFT(SHIFT), + .DR(DR), + .DI(DI), + .RDY(RDY), + .OVF1(OVF1), + .OVF2(OVF2), + .ADDR(ADDR), + .DOR(DOR), + .DOI(DOI)); + + wire [7:0] addrr; + `ifdef FFT128paramifft + assign addrr= (128-ADDR); //the result order if IFFT + `else + assign addrr= ADDR; + `endif + + + wire signed [15:0] DATA_R0,DATA_I0,DATA_REF; + Wave_ROM128 UR( .ADDR(addrr) , + .DATA_RE(DATA_R0), .DATA_IM(DATA_I0), .DATA_REF(DATA_REF) );// + + wire signed [18:15-nb+1] DREF=2*DATA_REF[15:15-nb+1]; + + integer sqra; + integer ctres; + reg f; + initial f=0; + always@(posedge CLK) begin //SQR calculator + if(ED) begin + if (f) + ctres=ctres+1; + if (RST || RDY) begin + if (RDY) f=1; + sqra=0; + ctres=0; end + else if (ctres<128) begin + //considered that input phase is 45 deg. ie. DOI=DOR + #2 sqra = sqra +(DREF-DOR)*(DREF-DOR); + #2 sqra = sqra +(DREF-DOI)*(DREF-DOI); end + else if (ctres==128) + $display("rms error is ", (sqra/256), " lsb"); + end end + + +endmodule Index: trunk/TB/sinerom128_gen.pl =================================================================== --- trunk/TB/sinerom128_gen.pl (nonexistent) +++ trunk/TB/sinerom128_gen.pl (revision 2) @@ -0,0 +1,145 @@ + +#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +# +# Copyright(c) 2009 by Unicore Systems. All rights reserved +# +# DESIGN : FFT128_core +# FILENAME : sinerom64_gen.pl +# CREATED : 10.1:2008 +# MODIFIED : +# VERSION : 1.0 +# +# AUTHORS: Anatolij Sergiyenko. +# HISTORY : +#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +# DESCRIPTION : Test generating PERL file1 +# FUNCTION: Generating sine wave ROM +# with $n samples which consists of 4 sine wave sum +#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +$aw=7; ## - address bit width +$n = 128; ### - period length +$n0 = 0; ### - init address +$f1 = 1; ## - first frequency +$f2 = 3; ## -second frequency +$f3 = 5; ## - 3-d frequency +$f4 = 7; ## -4-th frequency +$Pi = 3.14159265358 ; +$ph =$Pi/4; ## initial phase => 45 degree + open OutFile, ">Wave_ROM128.v" || die "Cannot open file .V"; # file is open to write + + + print OutFile "//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n"; + print OutFile "// ROM with ".$n." samples of the sine waves at the frequencies = ".$f1.", ". $f2.",". $f3." and ".$f4 ."\n"; + print OutFile "//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n"; + print OutFile " `timescale 1 ns / 1 ps \n"; + print OutFile "module Wave_ROM128 ( ADDR ,DATA_RE,DATA_IM,DATA_REF ); \n"; + print OutFile " output [15:0] DATA_RE,DATA_IM,DATA_REF ; \n"; + print OutFile " input [".($aw-1).":0] ADDR ; \n"; + + +# # Cosine table generation + print OutFile " reg [15:0] cosi[0:".($n-1)."]; \n"; + print OutFile " initial begin \n"; + for $j(0..$n/16-1){ + $cos_row=0; + for $i(0..15){ +$CosArr=(32767*cos(2*$Pi*$f1*(($n0+$i+16*$j)/$n))); #23170 +# $CosArr=(16384*cos(2*$Pi*$f1*(($n0+$i+$j*16)/$n))); +# +16383*cos(2*$Pi*$f2*(($n0+$i+$j*16)/$n))); +# $CosArr=(8191*cos($ph+2*$Pi*$f1*(($n0+$i+$j*16)/$n)) + # +8191*cos($ph+2*$Pi*$f2*(($n0+$i+$j*16)/$n)) + # +8191*cos($ph+2*$Pi*$f3*(($n0+$i+$j*16)/$n)) + # +8191*cos($ph+2*$Pi*$f4*(($n0+$i+$j*16)/$n))); + $sinv= To_Hex4(int ($CosArr)); + + print OutFile " cosi[".($n0+$i+$j*16)."]=16'h".$sinv.";"; +} +print OutFile "\n"; +} +print OutFile " end \n\n"; + print "\n"; +# # Sine table generation + print OutFile " reg [15:0] sine[0:".($n-1)."]; \n"; + print OutFile " initial begin \n"; + for $j(0..$n/16-1){ + $sin_row=0; + for $i(0..15){ + $SinArr=(32767*sin(2*$Pi*$f1*(($n0+$i+16*$j)/$n))); #16384 23170 +# $SinArr=(16384*sin(2*$Pi*$f1*(($n0+$i+$j*16)/$n))); # +# +16383*sin(2*$Pi*$f2*(($n0+$i+$j*16)/$n))); +# $SinArr=(8191*sin($ph+2*$Pi*$f1*(($n0+$i+$j*16)/$n)) + # +8191*sin($ph+2*$Pi*$f2*(($n0+$i+$j*16)/$n)) + # +8191*sin($ph+2*$Pi*$f3*(($n0+$i+$j*16)/$n)) + # +8191*sin($ph+2*$Pi*$f4*(($n0+$i+$j*16)/$n))); + + + $sinv= To_Hex4(int ($SinArr)); + + print OutFile " sine[".($n0+$i+$j*16)."]=16'h".$sinv.";"; +} +print OutFile "\n"; +} + print "\n"; +print OutFile " end \n\n"; + +##Reference table generation + print OutFile " reg [15:0] deltas[0:".($n-1)."]; \n"; + print OutFile " initial begin \n"; + for $j(0..$n/4-1){ + for $i(0..3){ + print OutFile " deltas[".($n0+$i+$j*4)."]=16'h0000;"; +} +print OutFile "\n"; +} +##print OutFile " deltas[".$f1."]=16'h3fff; deltas[".$f2."]=16'h3fff;\n"; +$SinMag=To_Hex4(int (8191*4*sin($ph))); + +print OutFile " deltas[".$f1."]=16'h".$SinMag."; deltas[".$f2."]=16'h".$SinMag."; deltas[".$f3."]=16'h".$SinMag."; deltas[".$f4."]=16'h".$SinMag.";\n"; +print OutFile " end \n\n"; + +print OutFile " assign DATA_RE=cosi[ADDR]; \n"; +print OutFile " assign DATA_IM=sine[ADDR]; \n"; +print OutFile " assign DATA_REF=deltas[ADDR]; \n"; +print OutFile "endmodule \n"; + + close(OutFile); + + + sub To_Hex2{ + my(%Hexnumbers)= (0,0,1,1,2,2,3,3, + 4,4,5,5,6,6,7,7, + 8,8,9,9,10,'A',11,'B', + 12,'C',13,'D',14,'E',15,'F'); + + $_[0]=($_[0]>=0) ? $_[0] : 256+$_[0]; + my($h21)=$_[0] % 16; + my($h22)=int($_[0] / 16); + return $Hexnumbers{$h22}.$Hexnumbers{$h21}; + }; + + sub To_Hex4{ + my(%Hexnumbers)= (0,0,1,1,2,2,3,3, + 4,4,5,5,6,6,7,7, + 8,8,9,9,10,'A',11,'B', + 12,'C',13,'D',14,'E',15,'F'); + + $_[0]=($_[0]>=0) ? $_[0] : 65536+$_[0]; + my($h21)=$_[0] % 16; + my($r21)=int($_[0] / 16); + my($h22)=$r21 % 16; + my($r22)=int($r21 / 16); + my($h23)=$r22 % 16; + my($h24)=int($r22 / 16); + return $Hexnumbers{$h24}.$Hexnumbers{$h23}.$Hexnumbers{$h22}.$Hexnumbers{$h21}; + ##return $_[0]; + }; + + open (File, "Wave_ROM128.v") || die "Cannot open r"; + while ($line = ) + { + print $line; # Ready file output to the screen + } + + + close(File); Index: trunk/TB/Wave_ROM128.v =================================================================== --- trunk/TB/Wave_ROM128.v (nonexistent) +++ trunk/TB/Wave_ROM128.v (revision 2) @@ -0,0 +1,110 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// ROM with 128 samples of the sine waves at the frequencies = 1, 3,5 and 7 +//^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + `timescale 1 ns / 1 ps +module Wave_ROM128 ( ADDR ,DATA_RE,DATA_IM,DATA_REF ); + output [15:0] DATA_RE,DATA_IM,DATA_REF ; + input [6:0] ADDR ; + reg [15:0] cosi[0:127]; + initial begin + cosi[0]=16'h7FFF; cosi[1]=16'h7FD7; cosi[2]=16'h7F61; cosi[3]=16'h7E9C; cosi[4]=16'h7D89; cosi[5]=16'h7C29; cosi[6]=16'h7A7C; cosi[7]=16'h7883; cosi[8]=16'h7640; cosi[9]=16'h73B5; cosi[10]=16'h70E1; cosi[11]=16'h6DC9; cosi[12]=16'h6A6C; cosi[13]=16'h66CE; cosi[14]=16'h62F1; cosi[15]=16'h5ED6; + cosi[16]=16'h5A81; cosi[17]=16'h55F4; cosi[18]=16'h5133; cosi[19]=16'h4C3F; cosi[20]=16'h471C; cosi[21]=16'h41CD; cosi[22]=16'h3C56; cosi[23]=16'h36B9; cosi[24]=16'h30FB; cosi[25]=16'h2B1E; cosi[26]=16'h2527; cosi[27]=16'h1F19; cosi[28]=16'h18F8; cosi[29]=16'h12C7; cosi[30]=16'h0C8B; cosi[31]=16'h0647; + cosi[32]=16'h0000; cosi[33]=16'hF9B9; cosi[34]=16'hF375; cosi[35]=16'hED39; cosi[36]=16'hE708; cosi[37]=16'hE0E7; cosi[38]=16'hDAD9; cosi[39]=16'hD4E2; cosi[40]=16'hCF05; cosi[41]=16'hC947; cosi[42]=16'hC3AA; cosi[43]=16'hBE33; cosi[44]=16'hB8E4; cosi[45]=16'hB3C1; cosi[46]=16'hAECD; cosi[47]=16'hAA0C; + cosi[48]=16'hA57F; cosi[49]=16'hA12A; cosi[50]=16'h9D0F; cosi[51]=16'h9932; cosi[52]=16'h9594; cosi[53]=16'h9237; cosi[54]=16'h8F1F; cosi[55]=16'h8C4B; cosi[56]=16'h89C0; cosi[57]=16'h877D; cosi[58]=16'h8584; cosi[59]=16'h83D7; cosi[60]=16'h8277; cosi[61]=16'h8164; cosi[62]=16'h809F; cosi[63]=16'h8029; + cosi[64]=16'h8001; cosi[65]=16'h8029; cosi[66]=16'h809F; cosi[67]=16'h8164; cosi[68]=16'h8277; cosi[69]=16'h83D7; cosi[70]=16'h8584; cosi[71]=16'h877D; cosi[72]=16'h89C0; cosi[73]=16'h8C4B; cosi[74]=16'h8F1F; cosi[75]=16'h9237; cosi[76]=16'h9594; cosi[77]=16'h9932; cosi[78]=16'h9D0F; cosi[79]=16'hA12A; + cosi[80]=16'hA57F; cosi[81]=16'hAA0C; cosi[82]=16'hAECD; cosi[83]=16'hB3C1; cosi[84]=16'hB8E4; cosi[85]=16'hBE33; cosi[86]=16'hC3AA; cosi[87]=16'hC947; cosi[88]=16'hCF05; cosi[89]=16'hD4E2; cosi[90]=16'hDAD9; cosi[91]=16'hE0E7; cosi[92]=16'hE708; cosi[93]=16'hED39; cosi[94]=16'hF375; cosi[95]=16'hF9B9; + cosi[96]=16'h0000; cosi[97]=16'h0647; cosi[98]=16'h0C8B; cosi[99]=16'h12C7; cosi[100]=16'h18F8; cosi[101]=16'h1F19; cosi[102]=16'h2527; cosi[103]=16'h2B1E; cosi[104]=16'h30FB; cosi[105]=16'h36B9; cosi[106]=16'h3C56; cosi[107]=16'h41CD; cosi[108]=16'h471C; cosi[109]=16'h4C3F; cosi[110]=16'h5133; cosi[111]=16'h55F4; + cosi[112]=16'h5A81; cosi[113]=16'h5ED6; cosi[114]=16'h62F1; cosi[115]=16'h66CE; cosi[116]=16'h6A6C; cosi[117]=16'h6DC9; cosi[118]=16'h70E1; cosi[119]=16'h73B5; cosi[120]=16'h7640; cosi[121]=16'h7883; cosi[122]=16'h7A7C; cosi[123]=16'h7C29; cosi[124]=16'h7D89; cosi[125]=16'h7E9C; cosi[126]=16'h7F61; cosi[127]=16'h7FD7; + end + + reg [15:0] sine[0:127]; + initial begin + sine[0]=16'h0000; sine[1]=16'h0647; sine[2]=16'h0C8B; sine[3]=16'h12C7; sine[4]=16'h18F8; sine[5]=16'h1F19; sine[6]=16'h2527; sine[7]=16'h2B1E; sine[8]=16'h30FB; sine[9]=16'h36B9; sine[10]=16'h3C56; sine[11]=16'h41CD; sine[12]=16'h471C; sine[13]=16'h4C3F; sine[14]=16'h5133; sine[15]=16'h55F4; + sine[16]=16'h5A81; sine[17]=16'h5ED6; sine[18]=16'h62F1; sine[19]=16'h66CE; sine[20]=16'h6A6C; sine[21]=16'h6DC9; sine[22]=16'h70E1; sine[23]=16'h73B5; sine[24]=16'h7640; sine[25]=16'h7883; sine[26]=16'h7A7C; sine[27]=16'h7C29; sine[28]=16'h7D89; sine[29]=16'h7E9C; sine[30]=16'h7F61; sine[31]=16'h7FD7; + sine[32]=16'h7FFF; sine[33]=16'h7FD7; sine[34]=16'h7F61; sine[35]=16'h7E9C; sine[36]=16'h7D89; sine[37]=16'h7C29; sine[38]=16'h7A7C; sine[39]=16'h7883; sine[40]=16'h7640; sine[41]=16'h73B5; sine[42]=16'h70E1; sine[43]=16'h6DC9; sine[44]=16'h6A6C; sine[45]=16'h66CE; sine[46]=16'h62F1; sine[47]=16'h5ED6; + sine[48]=16'h5A81; sine[49]=16'h55F4; sine[50]=16'h5133; sine[51]=16'h4C3F; sine[52]=16'h471C; sine[53]=16'h41CD; sine[54]=16'h3C56; sine[55]=16'h36B9; sine[56]=16'h30FB; sine[57]=16'h2B1E; sine[58]=16'h2527; sine[59]=16'h1F19; sine[60]=16'h18F8; sine[61]=16'h12C7; sine[62]=16'h0C8B; sine[63]=16'h0647; + sine[64]=16'h0000; sine[65]=16'hF9B9; sine[66]=16'hF375; sine[67]=16'hED39; sine[68]=16'hE708; sine[69]=16'hE0E7; sine[70]=16'hDAD9; sine[71]=16'hD4E2; sine[72]=16'hCF05; sine[73]=16'hC947; sine[74]=16'hC3AA; sine[75]=16'hBE33; sine[76]=16'hB8E4; sine[77]=16'hB3C1; sine[78]=16'hAECD; sine[79]=16'hAA0C; + sine[80]=16'hA57F; sine[81]=16'hA12A; sine[82]=16'h9D0F; sine[83]=16'h9932; sine[84]=16'h9594; sine[85]=16'h9237; sine[86]=16'h8F1F; sine[87]=16'h8C4B; sine[88]=16'h89C0; sine[89]=16'h877D; sine[90]=16'h8584; sine[91]=16'h83D7; sine[92]=16'h8277; sine[93]=16'h8164; sine[94]=16'h809F; sine[95]=16'h8029; + sine[96]=16'h8001; sine[97]=16'h8029; sine[98]=16'h809F; sine[99]=16'h8164; sine[100]=16'h8277; sine[101]=16'h83D7; sine[102]=16'h8584; sine[103]=16'h877D; sine[104]=16'h89C0; sine[105]=16'h8C4B; sine[106]=16'h8F1F; sine[107]=16'h9237; sine[108]=16'h9594; sine[109]=16'h9932; sine[110]=16'h9D0F; sine[111]=16'hA12A; + sine[112]=16'hA57F; sine[113]=16'hAA0C; sine[114]=16'hAECD; sine[115]=16'hB3C1; sine[116]=16'hB8E4; sine[117]=16'hBE33; sine[118]=16'hC3AA; sine[119]=16'hC947; sine[120]=16'hCF05; sine[121]=16'hD4E2; sine[122]=16'hDAD9; sine[123]=16'hE0E7; sine[124]=16'hE708; sine[125]=16'hED39; sine[126]=16'hF375; sine[127]=16'hF9B9; + end + + reg [15:0] deltas[0:127]; + initial begin + deltas[0]=16'h0000; deltas[1]=16'h0000; deltas[2]=16'h0000; deltas[3]=16'h0000; + deltas[4]=16'h0000; deltas[5]=16'h0000; deltas[6]=16'h0000; deltas[7]=16'h0000; + deltas[8]=16'h0000; deltas[9]=16'h0000; deltas[10]=16'h0000; deltas[11]=16'h0000; + deltas[12]=16'h0000; deltas[13]=16'h0000; deltas[14]=16'h0000; deltas[15]=16'h0000; + deltas[16]=16'h0000; deltas[17]=16'h0000; deltas[18]=16'h0000; deltas[19]=16'h0000; + deltas[20]=16'h0000; deltas[21]=16'h0000; deltas[22]=16'h0000; deltas[23]=16'h0000; + deltas[24]=16'h0000; deltas[25]=16'h0000; deltas[26]=16'h0000; deltas[27]=16'h0000; + deltas[28]=16'h0000; deltas[29]=16'h0000; deltas[30]=16'h0000; deltas[31]=16'h0000; + deltas[32]=16'h0000; deltas[33]=16'h0000; deltas[34]=16'h0000; deltas[35]=16'h0000; + deltas[36]=16'h0000; deltas[37]=16'h0000; deltas[38]=16'h0000; deltas[39]=16'h0000; + deltas[40]=16'h0000; deltas[41]=16'h0000; deltas[42]=16'h0000; deltas[43]=16'h0000; + deltas[44]=16'h0000; deltas[45]=16'h0000; deltas[46]=16'h0000; deltas[47]=16'h0000; + deltas[48]=16'h0000; deltas[49]=16'h0000; deltas[50]=16'h0000; deltas[51]=16'h0000; + deltas[52]=16'h0000; deltas[53]=16'h0000; deltas[54]=16'h0000; deltas[55]=16'h0000; + deltas[56]=16'h0000; deltas[57]=16'h0000; deltas[58]=16'h0000; deltas[59]=16'h0000; + deltas[60]=16'h0000; deltas[61]=16'h0000; deltas[62]=16'h0000; deltas[63]=16'h0000; + deltas[64]=16'h0000; deltas[65]=16'h0000; deltas[66]=16'h0000; deltas[67]=16'h0000; + deltas[68]=16'h0000; deltas[69]=16'h0000; deltas[70]=16'h0000; deltas[71]=16'h0000; + deltas[72]=16'h0000; deltas[73]=16'h0000; deltas[74]=16'h0000; deltas[75]=16'h0000; + deltas[76]=16'h0000; deltas[77]=16'h0000; deltas[78]=16'h0000; deltas[79]=16'h0000; + deltas[80]=16'h0000; deltas[81]=16'h0000; deltas[82]=16'h0000; deltas[83]=16'h0000; + deltas[84]=16'h0000; deltas[85]=16'h0000; deltas[86]=16'h0000; deltas[87]=16'h0000; + deltas[88]=16'h0000; deltas[89]=16'h0000; deltas[90]=16'h0000; deltas[91]=16'h0000; + deltas[92]=16'h0000; deltas[93]=16'h0000; deltas[94]=16'h0000; deltas[95]=16'h0000; + deltas[96]=16'h0000; deltas[97]=16'h0000; deltas[98]=16'h0000; deltas[99]=16'h0000; + deltas[100]=16'h0000; deltas[101]=16'h0000; deltas[102]=16'h0000; deltas[103]=16'h0000; + deltas[104]=16'h0000; deltas[105]=16'h0000; deltas[106]=16'h0000; deltas[107]=16'h0000; + deltas[108]=16'h0000; deltas[109]=16'h0000; deltas[110]=16'h0000; deltas[111]=16'h0000; + deltas[112]=16'h0000; deltas[113]=16'h0000; deltas[114]=16'h0000; deltas[115]=16'h0000; + deltas[116]=16'h0000; deltas[117]=16'h0000; deltas[118]=16'h0000; deltas[119]=16'h0000; + deltas[120]=16'h0000; deltas[121]=16'h0000; deltas[122]=16'h0000; deltas[123]=16'h0000; + deltas[124]=16'h0000; deltas[125]=16'h0000; deltas[126]=16'h0000; deltas[127]=16'h0000; + deltas[1]=16'h5A7F; deltas[3]=16'h5A7F; deltas[5]=16'h5A7F; deltas[7]=16'h5A7F; + end + + assign DATA_RE=cosi[ADDR]; + assign DATA_IM=sine[ADDR]; + assign DATA_REF=deltas[ADDR]; +endmodule Index: trunk/SRC/cnorm.v =================================================================== --- trunk/SRC/cnorm.v (nonexistent) +++ trunk/SRC/cnorm.v (revision 2) @@ -0,0 +1,132 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Normalization unit +// FUNCTION: shifting left up to 3 bits +// FILES: CNORM.v +// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT +// 2) Is registered +// 3) Overflow detector detects the overflow event +// by the given shift condition. The detector is zeroed by the START signal +// 4) RDY is the START signal delayed to a single clock cycle +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// File : +// Generated : +// +// Description : +// +//----------------------------------------------------------------------------- +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module CNORM ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI ); + `FFT128paramnb + + output OVF ; + reg OVF ; + output RDY ; + reg RDY ; + output [nb+1:0] DOR ; + wire [nb+1:0] DOR ; + output [nb+1:0] DOI ; + wire [nb+1:0] DOI ; + + input CLK ; + wire CLK ; + input ED ; + wire ED ; + input START ; + wire START ; + input [nb+2:0] DR ; + wire [nb+2:0] DR ; + input [nb+2:0] DI ; + wire [nb+2:0] DI ; + input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits + wire [1:0] SHIFT ; + + wire signed [nb+3:0] diri,diii; + assign diri = DR << SHIFT; + assign diii = DI << SHIFT; + + reg [nb+2:0] dir,dii; + + `ifdef FFT128round //rounding + always @( posedge CLK ) begin + if (ED) begin + if (diri[nb+2] && ~diri[0]) // <0 with LSB=00 + dir<=diri; + else dir<=diri+2; + if (diii[nb+2] && ~diii[0]) + dii<=diii; + else dii<=diii+2; + end + end + + `else //truncation + always @( posedge CLK ) begin + if (ED) begin + dir<=diri; + dii<=diii; + end + end + + + `endif + + always @( posedge CLK ) begin + if (ED) begin + RDY<=START; + if (START) + OVF<=0; + else + case (SHIFT) + 2'b01 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]); + 2'b10 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]) || + (DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]); + 2'b11 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2])|| + (DR[nb+3] != DR[nb]) || (DI[nb+3] != DI[nb]) || + (DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]); + endcase + end + end + + assign DOR= dir[nb+3:2]; + assign DOI= dii[nb+3:2]; + +endmodule Index: trunk/SRC/mpuc1307.v =================================================================== --- trunk/SRC/mpuc1307.v (nonexistent) +++ trunk/SRC/mpuc1307.v (revision 2) @@ -0,0 +1,126 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Complex Multiplier by 0.7071 +// FUNCTION: Constant multiplier to cos(PI/8)+cos(3*PI/8) =1.307 +// FILES: MPU�1307.v +// PROPERTIES: 1) Is based on shifts right and add +// 2) for short input bit width 1.307 is approximated as 1_0100_111 = 1_0101_00T +// 3) for medium bit width 1.3066 is approximated as 1_0100_1110_0111_11= 1_0101_00T0_1000_0T +// 4) for long bit width 1.30656 is approximated as 1_0100_1110_0111_1011=1_0101_00T0_1000_0T0T +// 5) hardware is 3 or 5, or 6 adders +1 +// 6) MPYJ switches multiply by j +// 6) A complex data is multiplied for 2 cycles, latent delay=4 +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`include "FFT128_CONFIG.inc" + +module MPUC1307 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI, ); + `FFT128paramnb + + input CLK ; + wire CLK ; + input DS ; + wire DS ; + input ED; //data strobe + input MPYJ ; //the result is multiplied by -j + wire MPYJ ; + input [nb-1:0] DR ; + wire signed [nb-1:0] DR ; + input [nb-1:0] DI ; + wire signed [nb-1:0] DI ; + + output [nb:0] DOR ; + reg [nb:0] DOR ; + output [nb:0] DOI ; + reg [nb:0] DOI ; + + reg signed [nb+2 :0] dx5; + reg signed [nb-1 :0] dx7; + reg signed [nb-1 :0] dii; + reg signed [nb : 0] dt; + wire signed [nb+3 : 0] dx5p; + wire signed [nb+3 : 0] dot; + reg edd,edd2, edd3; //delayed data enable impulse + reg mpyjd,mpyjd2,mpyjd3; + reg [nb:0] doo ; + reg [nb:0] droo ; + + always @(posedge CLK) + begin + if (ED) begin + edd<=DS; + edd2<=edd; + edd3<=edd2; + mpyjd<=MPYJ; + mpyjd2<=mpyjd; + mpyjd3<=mpyjd2; //1_0100_1110_0111_1011 + if (DS) begin // 1_0101_00T0_1000_0T0T + dx5<=DR+(DR <<2); //multiply by 5 + dx7<=DR-(DR>>>3); //multiply by 7, shifted right to 2 + dt<=DR; + dii<=DI; + end + else begin + dx5<=dii+(dii <<2); //multiply by 5 + dx7<=dii-(dii>>>3); //multiply by 7, shifted right to 3 + dt<=dii; + end + doo<=dot >>>3; + droo<=doo; + if (edd3) + if (mpyjd3) begin + DOR<=doo; + DOI<= - droo; end + else begin + DOR<=droo; + DOI<= doo; end + end + end + + assign dx5p=(dx5<<1)+(dx7>>>1); // multiply by 1_0101_00T + + `ifdef FFT128bitwidth_coef_high + assign dot= (dx5p+(dt>>>6) -(dx5>>>13));// multiply by 1_0101_00T0_1000_0T0T + `else + assign dot= dx5p+(dt>>>6); + `endif + + + +endmodule Index: trunk/SRC/WROM128.v =================================================================== --- trunk/SRC/WROM128.v (nonexistent) +++ trunk/SRC/WROM128.v (revision 2) @@ -0,0 +1,111 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Twiddle factor ROM for 128-point FFT +// FUNCTION: +// FILES: WROM128.v - ROM of twiddle factors. +// PROPERTIES: 1) Has 128 complex coefficients which form a table 8x16, +// and stay in the needed order, as they are addressed +// by the simple counter +// 2) 16-bit values are stored. When shorter bit width is set +// then rounding is not used +// 3) for FFT and IFFT depending on paramifft +// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`include "FFT128_CONFIG.inc" +`timescale 1 ns / 1 ps +module WROM128 ( WI ,WR ,ADDR ); + `FFT128paramnw + + input [6:0] ADDR ; + wire [6:0] ADDR ; + + output [nw-1:0] WI ; + wire [nw-1:0] WI ; + output [nw-1:0] WR ; + wire [nw-1:0] WR ; + + wire [15:0] cosw[0:127]; +assign cosw[0]=16'h7FFF;assign cosw[1]=16'h7FFF;assign cosw[2]=16'h7FFF;assign cosw[3]=16'h7FFF;assign cosw[4]=16'h7FFF;assign cosw[5]=16'h7FFF;assign cosw[6]=16'h7FFF;assign cosw[7]=16'h7FFF;assign cosw[8]=16'h7FFF;assign cosw[9]=16'h7FFF;assign cosw[10]=16'h7FFF;assign cosw[11]=16'h7FFF;assign cosw[12]=16'h7FFF;assign cosw[13]=16'h7FFF;assign cosw[14]=16'h7FFF;assign cosw[15]=16'h7FFF; +assign cosw[16]=16'h7FFF;assign cosw[17]=16'h7FD7;assign cosw[18]=16'h7F61;assign cosw[19]=16'h7E9C;assign cosw[20]=16'h7D89;assign cosw[21]=16'h7C29;assign cosw[22]=16'h7A7C;assign cosw[23]=16'h7883;assign cosw[24]=16'h7640;assign cosw[25]=16'h73B5;assign cosw[26]=16'h70E1;assign cosw[27]=16'h6DC9;assign cosw[28]=16'h6A6C;assign cosw[29]=16'h66CE;assign cosw[30]=16'h62F1;assign cosw[31]=16'h5ED6; +assign cosw[32]=16'h7FFF;assign cosw[33]=16'h7F61;assign cosw[34]=16'h7D89;assign cosw[35]=16'h7A7C;assign cosw[36]=16'h7640;assign cosw[37]=16'h70E1;assign cosw[38]=16'h6A6C;assign cosw[39]=16'h62F1;assign cosw[40]=16'h5A81;assign cosw[41]=16'h5133;assign cosw[42]=16'h471C;assign cosw[43]=16'h3C56;assign cosw[44]=16'h30FB;assign cosw[45]=16'h2527;assign cosw[46]=16'h18F8;assign cosw[47]=16'h0C8B; +assign cosw[48]=16'h7FFF;assign cosw[49]=16'h7E9C;assign cosw[50]=16'h7A7C;assign cosw[51]=16'h73B5;assign cosw[52]=16'h6A6C;assign cosw[53]=16'h5ED6;assign cosw[54]=16'h5133;assign cosw[55]=16'h41CD;assign cosw[56]=16'h30FB;assign cosw[57]=16'h1F19;assign cosw[58]=16'h0C8B;assign cosw[59]=16'hF9B9;assign cosw[60]=16'hE708;assign cosw[61]=16'hD4E2;assign cosw[62]=16'hC3AA;assign cosw[63]=16'hB3C1; +assign cosw[64]=16'h7FFF;assign cosw[65]=16'h7D89;assign cosw[66]=16'h7640;assign cosw[67]=16'h6A6C;assign cosw[68]=16'h5A81;assign cosw[69]=16'h471C;assign cosw[70]=16'h30FB;assign cosw[71]=16'h18F8;assign cosw[72]=16'h0000;assign cosw[73]=16'hE708;assign cosw[74]=16'hCF05;assign cosw[75]=16'hB8E4;assign cosw[76]=16'hA57F;assign cosw[77]=16'h9594;assign cosw[78]=16'h89C0;assign cosw[79]=16'h8277; +assign cosw[80]=16'h7FFF;assign cosw[81]=16'h7C29;assign cosw[82]=16'h70E1;assign cosw[83]=16'h5ED6;assign cosw[84]=16'h471C;assign cosw[85]=16'h2B1E;assign cosw[86]=16'h0C8B;assign cosw[87]=16'hED39;assign cosw[88]=16'hCF05;assign cosw[89]=16'hB3C1;assign cosw[90]=16'h9D0F;assign cosw[91]=16'h8C4B;assign cosw[92]=16'h8277;assign cosw[93]=16'h8029;assign cosw[94]=16'h8584;assign cosw[95]=16'h9237; +assign cosw[96]=16'h7FFF;assign cosw[97]=16'h7A7C;assign cosw[98]=16'h6A6C;assign cosw[99]=16'h5133;assign cosw[100]=16'h30FB;assign cosw[101]=16'h0C8B;assign cosw[102]=16'hE708;assign cosw[103]=16'hC3AA;assign cosw[104]=16'hA57F;assign cosw[105]=16'h8F1F;assign cosw[106]=16'h8277;assign cosw[107]=16'h809F;assign cosw[108]=16'h89C0;assign cosw[109]=16'h9D0F;assign cosw[110]=16'hB8E4;assign cosw[111]=16'hDAD9; +assign cosw[112]=16'h7FFF;assign cosw[113]=16'h7883;assign cosw[114]=16'h62F1;assign cosw[115]=16'h41CD;assign cosw[116]=16'h18F8;assign cosw[117]=16'hED39;assign cosw[118]=16'hC3AA;assign cosw[119]=16'hA12A;assign cosw[120]=16'h89C0;assign cosw[121]=16'h8029;assign cosw[122]=16'h8584;assign cosw[123]=16'h9932;assign cosw[124]=16'hB8E4;assign cosw[125]=16'hE0E7;assign cosw[126]=16'h0C8B;assign cosw[127]=16'h36B9; + + wire [15:0] sinw[0:127]; + + `ifdef FFT256paramifft //Inverse FFT +assign sinw[0]=16'h0000;assign sinw[1]=16'h0000;assign sinw[2]=16'h0000;assign sinw[3]=16'h0000;assign sinw[4]=16'h0000;assign sinw[5]=16'h0000;assign sinw[6]=16'h0000;assign sinw[7]=16'h0000;assign sinw[8]=16'h0000;assign sinw[9]=16'h0000;assign sinw[10]=16'h0000;assign sinw[11]=16'h0000;assign sinw[12]=16'h0000;assign sinw[13]=16'h0000;assign sinw[14]=16'h0000;assign sinw[15]=16'h0000; +assign sinw[16]=16'h0000;assign sinw[17]=16'h0647;assign sinw[18]=16'h0C8B;assign sinw[19]=16'h12C7;assign sinw[20]=16'h18F8;assign sinw[21]=16'h1F19;assign sinw[22]=16'h2527;assign sinw[23]=16'h2B1E;assign sinw[24]=16'h30FB;assign sinw[25]=16'h36B9;assign sinw[26]=16'h3C56;assign sinw[27]=16'h41CD;assign sinw[28]=16'h471C;assign sinw[29]=16'h4C3F;assign sinw[30]=16'h5133;assign sinw[31]=16'h55F4; +assign sinw[32]=16'h0000;assign sinw[33]=16'h0C8B;assign sinw[34]=16'h18F8;assign sinw[35]=16'h2527;assign sinw[36]=16'h30FB;assign sinw[37]=16'h3C56;assign sinw[38]=16'h471C;assign sinw[39]=16'h5133;assign sinw[40]=16'h5A81;assign sinw[41]=16'h62F1;assign sinw[42]=16'h6A6C;assign sinw[43]=16'h70E1;assign sinw[44]=16'h7640;assign sinw[45]=16'h7A7C;assign sinw[46]=16'h7D89;assign sinw[47]=16'h7F61; +assign sinw[48]=16'h0000;assign sinw[49]=16'h12C7;assign sinw[50]=16'h2527;assign sinw[51]=16'h36B9;assign sinw[52]=16'h471C;assign sinw[53]=16'h55F4;assign sinw[54]=16'h62F1;assign sinw[55]=16'h6DC9;assign sinw[56]=16'h7640;assign sinw[57]=16'h7C29;assign sinw[58]=16'h7F61;assign sinw[59]=16'h7FD7;assign sinw[60]=16'h7D89;assign sinw[61]=16'h7883;assign sinw[62]=16'h70E1;assign sinw[63]=16'h66CE; +assign sinw[64]=16'h0000;assign sinw[65]=16'h18F8;assign sinw[66]=16'h30FB;assign sinw[67]=16'h471C;assign sinw[68]=16'h5A81;assign sinw[69]=16'h6A6C;assign sinw[70]=16'h7640;assign sinw[71]=16'h7D89;assign sinw[72]=16'h7FFF;assign sinw[73]=16'h7D89;assign sinw[74]=16'h7640;assign sinw[75]=16'h6A6C;assign sinw[76]=16'h5A81;assign sinw[77]=16'h471C;assign sinw[78]=16'h30FB;assign sinw[79]=16'h18F8; +assign sinw[80]=16'h0000;assign sinw[81]=16'h1F19;assign sinw[82]=16'h3C56;assign sinw[83]=16'h55F4;assign sinw[84]=16'h6A6C;assign sinw[85]=16'h7883;assign sinw[86]=16'h7F61;assign sinw[87]=16'h7E9C;assign sinw[88]=16'h7640;assign sinw[89]=16'h66CE;assign sinw[90]=16'h5133;assign sinw[91]=16'h36B9;assign sinw[92]=16'h18F8;assign sinw[93]=16'hF9B9;assign sinw[94]=16'hDAD9;assign sinw[95]=16'hBE33; +assign sinw[96]=16'h0000;assign sinw[97]=16'h2527;assign sinw[98]=16'h471C;assign sinw[99]=16'h62F1;assign sinw[100]=16'h7640;assign sinw[101]=16'h7F61;assign sinw[102]=16'h7D89;assign sinw[103]=16'h70E1;assign sinw[104]=16'h5A81;assign sinw[105]=16'h3C56;assign sinw[106]=16'h18F8;assign sinw[107]=16'hF375;assign sinw[108]=16'hCF05;assign sinw[109]=16'hAECD;assign sinw[110]=16'h9594;assign sinw[111]=16'h8584; +assign sinw[112]=16'h0000;assign sinw[113]=16'h2B1E;assign sinw[114]=16'h5133;assign sinw[115]=16'h6DC9;assign sinw[116]=16'h7D89;assign sinw[117]=16'h7E9C;assign sinw[118]=16'h70E1;assign sinw[119]=16'h55F4;assign sinw[120]=16'h30FB;assign sinw[121]=16'h0647;assign sinw[122]=16'hDAD9;assign sinw[123]=16'hB3C1;assign sinw[124]=16'h9594;assign sinw[125]=16'h83D7;assign sinw[126]=16'h809F;assign sinw[127]=16'h8C4B; + + `else //Forward FFT + +assign sinw[0]=16'h0000;assign sinw[1]=16'h0000;assign sinw[2]=16'h0000;assign sinw[3]=16'h0000;assign sinw[4]=16'h0000;assign sinw[5]=16'h0000;assign sinw[6]=16'h0000;assign sinw[7]=16'h0000;assign sinw[8]=16'h0000;assign sinw[9]=16'h0000;assign sinw[10]=16'h0000;assign sinw[11]=16'h0000;assign sinw[12]=16'h0000;assign sinw[13]=16'h0000;assign sinw[14]=16'h0000;assign sinw[15]=16'h0000; +assign sinw[16]=16'h0000;assign sinw[17]=16'hF9B9;assign sinw[18]=16'hF375;assign sinw[19]=16'hED39;assign sinw[20]=16'hE708;assign sinw[21]=16'hE0E7;assign sinw[22]=16'hDAD9;assign sinw[23]=16'hD4E2;assign sinw[24]=16'hCF05;assign sinw[25]=16'hC947;assign sinw[26]=16'hC3AA;assign sinw[27]=16'hBE33;assign sinw[28]=16'hB8E4;assign sinw[29]=16'hB3C1;assign sinw[30]=16'hAECD;assign sinw[31]=16'hAA0C; +assign sinw[32]=16'h0000;assign sinw[33]=16'hF375;assign sinw[34]=16'hE708;assign sinw[35]=16'hDAD9;assign sinw[36]=16'hCF05;assign sinw[37]=16'hC3AA;assign sinw[38]=16'hB8E4;assign sinw[39]=16'hAECD;assign sinw[40]=16'hA57F;assign sinw[41]=16'h9D0F;assign sinw[42]=16'h9594;assign sinw[43]=16'h8F1F;assign sinw[44]=16'h89C0;assign sinw[45]=16'h8584;assign sinw[46]=16'h8277;assign sinw[47]=16'h809F; +assign sinw[48]=16'h0000;assign sinw[49]=16'hED39;assign sinw[50]=16'hDAD9;assign sinw[51]=16'hC947;assign sinw[52]=16'hB8E4;assign sinw[53]=16'hAA0C;assign sinw[54]=16'h9D0F;assign sinw[55]=16'h9237;assign sinw[56]=16'h89C0;assign sinw[57]=16'h83D7;assign sinw[58]=16'h809F;assign sinw[59]=16'h8029;assign sinw[60]=16'h8277;assign sinw[61]=16'h877D;assign sinw[62]=16'h8F1F;assign sinw[63]=16'h9932; +assign sinw[64]=16'h0000;assign sinw[65]=16'hE708;assign sinw[66]=16'hCF05;assign sinw[67]=16'hB8E4;assign sinw[68]=16'hA57F;assign sinw[69]=16'h9594;assign sinw[70]=16'h89C0;assign sinw[71]=16'h8277;assign sinw[72]=16'h8001;assign sinw[73]=16'h8277;assign sinw[74]=16'h89C0;assign sinw[75]=16'h9594;assign sinw[76]=16'hA57F;assign sinw[77]=16'hB8E4;assign sinw[78]=16'hCF05;assign sinw[79]=16'hE708; +assign sinw[80]=16'h0000;assign sinw[81]=16'hE0E7;assign sinw[82]=16'hC3AA;assign sinw[83]=16'hAA0C;assign sinw[84]=16'h9594;assign sinw[85]=16'h877D;assign sinw[86]=16'h809F;assign sinw[87]=16'h8164;assign sinw[88]=16'h89C0;assign sinw[89]=16'h9932;assign sinw[90]=16'hAECD;assign sinw[91]=16'hC947;assign sinw[92]=16'hE708;assign sinw[93]=16'h0647;assign sinw[94]=16'h2527;assign sinw[95]=16'h41CD; +assign sinw[96]=16'h0000;assign sinw[97]=16'hDAD9;assign sinw[98]=16'hB8E4;assign sinw[99]=16'h9D0F;assign sinw[100]=16'h89C0;assign sinw[101]=16'h809F;assign sinw[102]=16'h8277;assign sinw[103]=16'h8F1F;assign sinw[104]=16'hA57F;assign sinw[105]=16'hC3AA;assign sinw[106]=16'hE708;assign sinw[107]=16'h0C8B;assign sinw[108]=16'h30FB;assign sinw[109]=16'h5133;assign sinw[110]=16'h6A6C;assign sinw[111]=16'h7A7C; +assign sinw[112]=16'h0000;assign sinw[113]=16'hD4E2;assign sinw[114]=16'hAECD;assign sinw[115]=16'h9237;assign sinw[116]=16'h8277;assign sinw[117]=16'h8164;assign sinw[118]=16'h8F1F;assign sinw[119]=16'hAA0C;assign sinw[120]=16'hCF05;assign sinw[121]=16'hF9B9;assign sinw[122]=16'h2527;assign sinw[123]=16'h4C3F;assign sinw[124]=16'h6A6C;assign sinw[125]=16'h7C29;assign sinw[126]=16'h7F61;assign sinw[127]=16'h73B5; + `endif + + + wire [15:0] wri,wii ; + assign wri=cosw[ADDR]; + assign wii=sinw[ADDR]; + + wire [nw:0] wrt,wit; + + + assign wrt = wri[15:16-nw]; + assign wit = wii[15:16-nw]; + assign WR= wrt[nw-1:0]; + assign WI= wit[nw-1:0]; + +endmodule Index: trunk/SRC/ram2x128.v =================================================================== --- trunk/SRC/ram2x128.v (nonexistent) +++ trunk/SRC/ram2x128.v (revision 2) @@ -0,0 +1,139 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : 2-port RAM +// FUNCTION: 2-port RAM with 1 port to write and 1 port to read +// FILES: RAM2x256C.v - dual ported synchronous RAM, contains: +// RAM256.v -single ported synchronous RAM +// PROPERTIES: 1) Has the volume of 2x256 complex data +// 2) Contains 4 single port RAMs for real and imaginary parts of data in the 2-fold volume +// Two halves of RAM are switched on and off in the write mode by the signal ODD +// 3) RAM is synchronous one, the read datum is outputted in 2 cycles after the address setting +// 4) Can be substituted to any 2-port synchronous RAM for example, +// to one RAMB16_S36_S36 in Xilinx FPGAs +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + + + +module RAM2x128C ( CLK ,ED ,WE ,ODD ,ADDRW ,ADDRR ,DR ,DI ,DOR ,DOI ); + `FFT128paramnb + + + output [nb-1:0] DOR ; + wire [nb-1:0] DOR ; + output [nb-1:0] DOI ; + wire [nb-1:0] DOI ; + input CLK ; + wire CLK ; + input ED ; + wire ED ; + input WE ; //write enable + wire WE ; + input ODD ; // RAM part switshing + wire ODD ; + input [6:0] ADDRW ; + wire [6:0] ADDRW ; + input [6:0] ADDRR ; + wire [6:0] ADDRR ; + input [nb-1:0] DR ; + wire [nb-1:0] DR ; + input [nb-1:0] DI ; + wire [nb-1:0] DI ; + + reg oddd,odd2; + always @( posedge CLK) begin //switch which reswiches the RAM parts + if (ED) begin + oddd<=ODD; + odd2<=oddd; + end + end + `ifdef FFT128bufferports1 + //One-port RAMs are used + wire we0,we1; + wire [nb-1:0] dor0,dor1,doi0,doi1; + wire [6:0] addr0,addr1; + + + + assign addr0 =ODD? ADDRW: ADDRR; //MUXA0 + assign addr1 = ~ODD? ADDRW:ADDRR; // MUXA1 + assign we0 =ODD? WE: 0; // MUXW0: + assign we1 =~ODD? WE: 0; // MUXW1: + + //1-st half - write when odd=1 read when odd=0 + RAM128 #(nb) URAM0(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DR),.DO(dor0)); // + RAM128 #(nb) URAM1(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DI),.DO(doi0)); + + //2-d half + RAM128 #(nb) URAM2(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DR),.DO(dor1));// + RAM128 #(nb) URAM3(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DI),.DO(doi1)); + + assign DOR=~odd2? dor0 : dor1; // MUXDR: + assign DOI=~odd2? doi0 : doi1; // MUXDI: + + `else + //Two-port RAM is used + wire [7:0] addrr2 = {ODD,ADDRR}; + wire [7:0] addrw2 = {~ODD,ADDRW}; + wire [2*nb-1:0] di= {DR,DI} ; + + //wire [2*nb-1:0] doi; + reg [2*nb-1:0] doi; + + reg [2*nb-1:0] ram [255:0]; + reg [7:0] read_addra; + always @(posedge CLK) begin + if (ED) + begin + if (WE) + ram[addrw2] <= di; + read_addra <= addrr2; + doi = ram[read_addra]; + end + end + //assign + + assign DOR=doi[2*nb-1:nb]; // Real read data + assign DOI=doi[nb-1:0]; // Imaginary read data + + + `endif +endmodule Index: trunk/SRC/fft16.v =================================================================== --- trunk/SRC/fft16.v (nonexistent) +++ trunk/SRC/fft16.v (revision 2) @@ -0,0 +1,608 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Stage of FFT 128 processor +// FUNCTION: 16-point FFT +// FILES: FFT16.v - stage, contains +// MPUC707.v - multiplier to the factor 0.707. +// MPUC541.v - multiplier to the factor 0.541. +// MPUC1307.v - multiplier to the factor 1.307. +// MPUC924_383.v - multiplier to the factors 0.924 and 0.383. +// PROPERTIES: 1) Fully pipelined +// 2) Each clock cycle complex datum is entered +// and complex result is outputted +// 3) Has 16-clock cycle period starting with the START impulse +// and continuing forever +// 4) rounding is not used +// 5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms". +// 6)IFFT is performed by substituting the output result order to the reversed one +// (by exchanging - to + and + to -) +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +//Algorithm: +///procedure FFT16( +// X: in MEMOC; -- �� +// y:out MEMOC) -- �� +// is +// variable t1,t2,t3,t4,t5,t6,t7,t8,t9,t10: complex; +// variable t11,t12,t13,t14,t15,t16,t17,t18,t19,t20: complex; +// variable t21,t22,t23,t24,t25,t26: complex; +// variable m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10: complex; +// variable m11,m12,m13,m14,m15,m16,m17: complex; +// variable s1,s2,s3,s4,s5,s6,s7,s8,s9,s10: complex; +// variable s11,s12,s13,s14,s15,s16,s17,s18,s19,s20: complex; +// begin +// t1:=x(0) + x(8); m4:=x(0) - x(8); +// t2:=x(4) + x(12); m12:=-CBASE_j*(x(4)-x(12)); +// t3:=x(2) + x(10); t4:=x(2) - x(10); +// t5:=x(6) + x(14); t6:=x(6) - x(14); +// t7:=x(1) + x(9); t8:=x(1) - x(9); +// t9:=x(3) + x(11); t10:=x(3) - x(11); +// t11:=x(5) + x(13); t12:=x(5) - x(13); +// t13:=x(7) + x(15); t14:=x(7) - x(15); +// t15:=t1 + t2; m3:= t1 - t2; +// t16:=t3 + t5; m11:= -CBASE_j*(t3 - t5); +// t17:=t15 + t16; m2:= t15 - t16; +// t18:=t7 + t11; t19:= t7 - t11; +// t20:=t9 + t13; t21:= t9 - t13; +// t22:=t18 + t20; m10:= -CBASE_j*(t18 - t20); +// t23:=t8 + t14; t24:= t8 - t14; +// t25:=t12 + t10; t26:= t12 - t10; +// +// m0:=t17 + t22; m1:=t17 - t22; +// m13:=-CBASE_j*c707*(t19 + t21); m5:=c707*(t19 - t21); +// m6:=c707*(t4 - t6); m14:=-CBASE_j*c707*(t4 + t6); +// +// m7:=c3*(t24+t26); +// m8:=c13*(t24); +// m9:=-s1_3*(t26); +// s7:= m8 - m7; +// s8:= m9 - m7; +// +// m15:=-CBASE_j*c1*(t23 + t25); +// m16:= -CBASE_j*s1_3*(t23); +// m17:=-CBASE_j*c13*(t25); +// s15:= m15 - m16; +// s16:= m15 - m17; +// +// s1:=m3 + m5; s2:=m3 - m5; +// s3:=m13 + m11; s4:=m13 - m11; +// s5:=m4 + m6; s6:=m4 - m6; +// s9:=s5 + s7; s10:=s5 - s7; +// s11:=s6 + s8; s12:=s6 - s8; +// s13:=m12 + m14; s14:=m12 - m14; +// s17:=s13 + s15; s18:=s13 - s15; +// s19:=s14 + s16; s20:=s14 - s16; +// +// y(0):=m0; y(8):=m1; +// y(1):=s9 + s17; y(15):=s9 - s17; +// y(2):=s1 + s3; y(14):=s1 - s3; +// y(3):=s12 - s20; y(13):=s12 + s20; +// y(4):=m2 + m10; y(12):=m2 - m10; +// y(5):=s11 + s19; y(11):=s11 - s19; +// y(6):=s2 + s4; y(10):=s2 - s4; +// y(7):=s10 - s18; y(9):=s10 + s18; +// end procedure; +// + +`timescale 1ns / 1ps +`include "FFT128_CONFIG.inc" + +module FFT16 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY ); + `FFT128paramnb + + input ED ; //slowdown impulse + wire ED ; + input RST ; + wire RST ; + input CLK ; + wire CLK ; + input [nb-1:0] DII ; + wire [nb-1:0] DII ; + input START ; + wire START ; + input [nb-1:0] DIR ; + wire [nb-1:0] DIR ; + + output [nb+3:0] DOI ; + wire [nb+3:0] DOI ; + output [nb+3:0] DOR ; + wire [nb+3:0] DOR ; + output RDY ; + reg RDY ; + + reg [3:0] ct; //main phase counter + reg [5:0] ctd; //delay counter + + always @( posedge CLK) begin //Control counter + // + if (RST) begin + ct<=0; + ctd<=63; + RDY<=0; end + else if (START) begin + ct<=0; + ctd<=0; + RDY<=0; end + else if (ED) begin + RDY<=0; + ct<=ct+1; + if (ctd !=6'b111111) + ctd<=ctd+1; + if (ctd==44-16 ) + RDY<=1; + end + + end + + reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,d5r,d6r,d7r,d8r,di,d1i,d2i,d3i,d4i,d5i,d6i,d7i,d8i; + always @(posedge CLK) // input register file + begin + if (ED) begin + dr<=DIR; + d1r<=dr; d2r<=d1r; d3r<=d2r;d4r<=d3r; + d5r<=d4r;d6r<=d5r; d7r<=d6r; d8r<=d7r; + di<=DII; + d1i<=di; d2i<=d1i; d3i<=d2i; d4i<=d3i; + d5i<=d4i; d6i<=d5i;d7i<=d6i; d8i<=d7i; + end + end + + reg signed [nb:0] s1r,s1d1r,s1d2r,s1d3r,s1d4r,s1d5r,s1d6r,s1d7r,s1d8r; //even result sums + reg signed [nb:0] s1i,s1d1i,s1d2i,s1d3i,s1d4i,s1d5i,s1d6i,s1d7i,s1d8i; //even result sums + reg signed [nb:0] s2r,s2d1r,s2d2r,s2d3r,s2d4r,s2d5r,s2d6r,s2d7r,s2d8r,m4_12r; //odd result sums + reg signed [nb:0] s2i,s2d1i,s2d2i,s2d3i,s2d4i,s2d5i,s2d6i,s2d7i,s2d8i,m4_12i; //odd result sums + always @(posedge CLK) begin // S1,S2 =t1-t14,m4,m12' and delayed + if (ED && ((ct==9) || (ct==10) || (ct==11) ||(ct==12) || + (ct==13) || (ct==14) ||(ct==15) || (ct==0))) begin + s1r<=d8r + dr ; + s1i<=d8i + di ; + s2r<=d8r - dr ; + s2i<= d8i - di; + end + if (ED) begin //delayed results + s1d1r<=s1r; s1d2r<=s1d1r; s1d1i<=s1i; s1d2i<=s1d1i; + s1d3r<=s1d2r; s1d3i<=s1d2i; s1d4r<=s1d3r; s1d4i<=s1d3i; + s1d5r<=s1d4r; s1d5i<=s1d4i; s1d6r<=s1d5r; s1d6i<=s1d5i; + s1d7r<=s1d6r; s1d7i<=s1d6i; s1d8r<=s1d7r; s1d8i<=s1d7i; + + s2d1r<=s2r; s2d2r<=s2d1r; s2d1i<=s2i; s2d2i<=s2d1i; + s2d3r<=s2d2r; s2d3i<=s2d2i; s2d4r<=s2d3r; s2d4i<=s2d3i; + s2d5r<=s2d4r; s2d5i<=s2d4i; s2d6r<=s2d5r; s2d6i<=s2d5i; + s2d7r<=s2d6r; s2d7i<=s2d6i; s2d8r<=s2d7r; s2d8i<=s2d7i; + if (ct==2) begin + m4_12r<=s2d8r; m4_12i<=s2d8i; end + else if (ct==6) begin + m4_12r<=s2d8i; m4_12i<= 0 - s2d8r; + end + end + end + /////////////////////////////////////////// + //arm of even result calculations + //////////////////////////////////////////// + reg signed [nb+1:0] s3r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r; + reg signed [nb+1:0] s3i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i; + always @(posedge CLK) begin //ALU S3: + if (ED) begin + case (ct) + 14 ,15 : begin s3r<= s1d4r+s1r; //t15 //t18 + s3i<= s1d4i+ s1i ;end + 0 ,1 : begin s3r<= s1d6r - s1d2r; //m3, t19 + s3i<= s1d6i - s1d2i ;end + 2 ,3 : begin s3r<= s1d6r +s1d2r; //t16 ,t20 + s3i<= s1d6i+ s1d2i ; end + 4 ,5 : begin s3r<= s1d8r - s1d4r; // m11',t21 + s3i<= s1d8i - s1d4i ; end + endcase + s3d1r<=s3r; s3d1i<=s3i; s3d2r<=s3d1r; s3d2i<=s3d1i; + s3d3r<=s3d2r; s3d3i<=s3d2i; s3d4r<=s3d3r; s3d4i<=s3d3i; + s3d5r<=s3d4r; s3d5i<=s3d4i; s3d6r<=s3d5r; s3d6i<=s3d5i; + end + end + + reg signed [nb+2:0] s4r,s4d1r,s4d2r,s4d3r,s4d4r,s4d5r,s4d6r,s4d7r,m3r; + reg signed [nb+2:0] s4i,s4d1i,s4d2i,s4d3i,s4d4i,s4d5i,s4d6i,s4d7i,m3i; + + always @ (posedge CLK) begin // S4 + if (ED) begin + if ((ct==3) | (ct==4)) begin + s4r<= s3d4r + s3r; //t17 ,t22 + s4i<= s3d4i + s3i; end + else if ((ct==5) | (ct==6) | (ct==8) ) begin + s4r<=s3d6r - s3d2r; //m2,m10', m5' + s4i<= s3d6i - s3d2i; end + else if (ct==7) begin + s4r<=s3d1r + s3d5r; //m13 + s4i<= s3d1i + s3d5i; + end + s4d1r<=s4r; s4d1i<=s4i; s4d2r<=s4d1r; s4d2i<=s4d1i; + s4d3r<=s4d2r; s4d3i<=s4d2i; s4d4r<=s4d3r; s4d4i<=s4d3i; + s4d5r<=s4d4r; s4d5i<=s4d4i; s4d6r<=s4d5r; s4d6i<=s4d5i; + s4d7r<=s4d6r; s4d7i<=s4d6i; + if (ct==7) begin + m3r<=s3d6r; //m3 + m3i<=s3d6i; end + end + end + + wire em707,mpyj7; + assign em707 = ((ct==8) || (ct==10 )||(ct==1) || (ct==5)); //control signals for the multiplier + assign mpyj7 = ((ct==8) || (ct==5)); + + reg signed [nb+2:0] s7r,s7d1r; + reg signed [nb+2:0] s7i,s7d1i; + wire signed [nb+2:0] m707r,m707i,m70r,m70i; + assign m70r = ((ct==1) || (ct==5))? s7r :s4r; //multiplexor at the multiplier input + assign m70i = ((ct==1) || (ct==5))? s7i :s4i; + + MPUC707 #(nb+3) UM707( .CLK(CLK),.ED(ED),.DS(em707), .MPYJ(mpyj7), //multiplier by 0.707 + .DR(m70r),.DI(m70i) ,.DOR(m707r) ,.DOI(m707i)); + + + reg signed [nb+2:0] s3jr,s3ji, m10r,m10i; + always @ (posedge CLK) begin //multiply by J + if (ED) begin + case (ct) + 11: begin s3jr<= s3d6i; //m11 + s3ji<=0 - s3d6r; end + 14: begin s3jr<= s4d7i; //m10 + s3ji<=0 - s4d7r; end + endcase + if (ct==1) begin + m10r<=s3jr; //m10 + m10i<=s3ji; + end + end + end + + reg signed [nb+3:0] s5r,s5d1r,s5d2r,s5d3r,s5d4r,s5d5r,s5d6r,s5d7r,s5d8r,s5d9r, s5d10r,m2r,m2dr; + reg signed [nb+3:0] s5i,s5d1i,s5d2i,s5d3i,s5d4i,s5d5i,s5d6i,s5d7i,s5d8i,s5d9i,s5d10i,m2i,m2di; + always @ (posedge CLK) // S5: + if (ED) begin + case (ct) + 10: begin s5r<=s4d5r + s4d6r; //m0 + s5i<=s4d5i + s4d6i; end + 11: begin s5r<=s4d7r - s4d6r; //m1 + s5i<=s4d7i - s4d6i; end + 12: begin s5r<=m707r + s3jr; //S3 + s5i<= m707i+s3ji;end + 13: begin s5r<=m707r - s3jr; //S4 + s5i<= m707i - s3ji;end + 14: begin s5r<= m3r+m707r; //S1 + s5i<= m3i+m707i ;end + 15: begin s5r<=m3r-m707r ; //S2 + s5i<= m3i -m707i ;end + 6: begin //S2 + s5d10r<=s5d9r ; //S2 + s5d10i<=s5d9i ;end + + endcase + if ((ct==4)||(ct==5)||(ct==6)||(ct==7)) begin + s5d9r<=s5d8r ; s5d9i<=s5d8i ; end + + s5d1r<=s5r; s5d1i<=s5i; s5d2r<=s5d1r; s5d2i<=s5d1i; + s5d3r<=s5d2r; s5d3i<=s5d2i; s5d4r<=s5d3r; s5d4i<=s5d3i; + s5d5r<=s5d4r; s5d5i<=s5d4i; s5d6r<=s5d5r; s5d6i<=s5d5i; + s5d7r<=s5d6r; s5d7i<=s5d6i; s5d8r<=s5d7r; s5d8i<=s5d7i; + + if (ct==13) begin + m2r<=s4d7r; m2i<=s4d7i; end + if (ct==1) begin + m2dr<=m2r; m2di<=m2i; end + + end + + + + reg signed [nb+3:0] s6r,s6i ; + + `ifdef FFT128paramifft // For IFFT + always @ (posedge CLK) begin // S6-- result adder + if (ED) + case (ct) + 13: begin s6r<=s5d2r; // -- Y0 + s6i<=(s5d2i);end //-- Y0 + 15: begin + s6r<=s5d2r - s5r ; //Y2 + s6i<=s5d2i - s5i ; end + 1: begin + s6r<=m2r - s3jr ; //Y4 + s6i<=m2i - s3ji ; end + 3: begin + s6r<=s5d3r - s5d5r ; //Y6 + s6i<= s5d3i -s5d5i ; end + 5:begin s6r<=(s5d9r) ; //-- Y8 + s6i<=(s5d9i) ; end + 7: begin + s6r<= s5d7r + s5d9r ; // Y10 + s6i<= s5d7i + s5d9i ; end + 9: begin // Y12 + s6r<=m2dr +m10r ; + s6i<=m2di + m10i ; + end + 11: begin // Y14 + s6r<= s5d9r + s5d10r ; + s6i<= s5d9i + s5d10i ; + end + endcase + end + + `else + always @ (posedge CLK) begin // S6-- result adder + if (ED) + case (ct) + 13: begin s6r<=s5d2r; // -- Y0 + s6i<=s5d2i;end //-- Y0 + 15: begin + s6r<=s5d2r + s5r ; //Y2 + s6i<=s5d2i + s5i ; end + 1: begin + s6r<=m2r + s3jr ; //Y4 + s6i<=m2i + s3ji ; end + 3: begin + s6r<=s5d3r + s5d5r ; //Y6 + s6i<= s5d3i +s5d5i ; end + 5:begin s6r<=s5d9r; //-- Y8 + s6i<=s5d9i; end + 7: begin + s6r<= s5d7r - s5d9r ; // Y10 + s6i<= s5d7i - s5d9i ; end + 9: begin // Y12 + s6r<=m2dr -m10r ; + s6i<=m2di - m10i ; + end + 11: begin // Y14 + s6r<= s5d9r - s5d10r ; + s6i<= s5d9i - s5d10i ; + end + endcase + end + `endif + + /////////////////////////////////////////////////////////// + //arm of odd result calculations + ////////////////////////////////////////////////////////// + + always @(posedge CLK) begin //ALU S7: + if (ED) + case (ct) + 15:begin s7r<= s2d2r-s2r; //t26 + s7i<= s2d2i- s2i ;end + 0: begin s7r<= s2d4r-s2r; //m6' + s7i<= s2d4i- s2i ; + s7d1r<=s7r; + s7d1i<=s7i;end + 1: begin s7r<= s2d6r - s2r; //t24 + s7i<= s2d6i - s2i; end + 2: begin s7r<= s7r -s7d1r; //m7' + s7i<= s7i- s7d1i ; end + 3: begin s7r<= s2d8r + s2d2r; // t23 + s7i<= s2d8i + s2d2i ; end + 4: begin s7r<= s2d8r + s2d4r; // m14' + s7i<= s2d8i + s2d4i ; + s7d1r<=s7r; + s7d1i<=s7i;end + 5: begin s7r<= s2d8r + s2d6r; // t25 + s7i<= s2d8i + s2d6i ; end + 6: begin s7r<= s7r + s7d1r; //m15' + s7i<= s7i + s7d1i ; end + endcase + end + + wire em541,mpyj541; + wire signed [nb+2:0] m541r,m541i; + assign em541 = ((ct==0) || (ct==4)); //control signals for the multiplier + assign mpyj541 = ((ct==4)); + MPUC541 #(nb+3) UM541( .CLK(CLK),.ED(ED),.DS(em541), .MPYJ(mpyj541), //multiplier by 0.383 + .DR(s7r),.DI(s7i) ,.DOR(m541r) ,.DOI(m541i)); + + + wire em1307,mpyj1307; + wire signed [nb+2:0] m1307r,m1307i; + assign em1307 = ((ct==2) || (ct==6)); //control signals for the multiplier + assign mpyj1307 = ((ct==6)); + MPUC1307 #(nb+3) UM1307( .CLK(CLK),.ED(ED),.DS(em1307), .MPYJ(mpyj1307), //multiplier by 1.306 + .DR(s7r),.DI(s7i) ,.DOR(m1307r) ,.DOI(m1307i)); + + wire em383,mpyj383,c383; + wire signed [nb+2:0] m383r,m383i; + assign em383 = ((ct==3) || (ct==7)); //control signals for the multiplier + assign mpyj383 = ((ct==7)); + assign c383 = (ct==3); + MPUC924_383 #(nb+3) UM383(.CLK(CLK),.ED(ED),.DS(em383),.MPYJ(mpyj383),.C383(c383), //multiplier by 0.383 + .DR(s7r),.DI(s7i) ,.DOR(m383r) ,.DOI(m383i)); + + reg signed [nb+2:0] m8_17r,m8_17i,m9_16r,m9_16i; + always @(posedge CLK) begin //Reg-s + if (ED) begin + if (ct==4 || ct==8) begin + m9_16r<=m541r; //M9_ M16 + m9_16i<=m541i; + end + if ( ct==6 || ct==10) begin + m8_17r<=m1307r; //M8_ M17 + m8_17i<=m1307i; + end + end + end + + + + + reg signed [nb+2:0] s8r,s8i,s8d1r,s8d2r,s8d3r,s8d4r,s8d1i,s8d2i,s8d3i,s8d4i ; + always @ (posedge CLK) begin // S8-- adder + if (ED) + case (ct) + 5,9: begin s8r<=m4_12r +m707r ; // -- S5 S13 + s8i<=m4_12i +m707i ;end //-- + 6,10: begin + s8r<=m4_12r - m707r ; // -- S6 , S14 + s8i<=m4_12i - m707i ; end + 7: begin + s8r<=m8_17r - m383r ; // -- S7 ,S15 + s8i<=m8_17i -m383i ; end + 8: begin + s8r<=m9_16r - m383r ; // -- S8 , S16 + s8i<=m9_16i -m383i ; end + 11: begin + s8r<=m383r - m9_16r ; // -- S7 ,S15 + s8i<=m383i - m9_16i; end + 12: begin + s8r<=m383r - m8_17r; // -- S8 , S16 + s8i<=m383i - m8_17i; end + endcase + s8d1r<=s8r; s8d1i<=s8i; s8d2r<=s8d1r; s8d2i<=s8d1i; + s8d3r<=s8d2r; s8d3i<=s8d2i; s8d4r<=s8d3r; s8d4i<=s8d3i; + end + + reg signed [nb+3:0] s9r,s9d1r,s9d2r,s9d3r,s9d4r,s9d5r,s9d6r,s9d7r,s9d8r,s9d9r, s9d10r,s9d11r,s9d12r,s9d13r; + reg signed [nb+3:0] s9i,s9d1i,s9d2i,s9d3i,s9d4i,s9d5i,s9d6i,s9d7i,s9d8i,s9d9i,s9d10i,s9d11i,s9d12i,s9d13i; + always @ (posedge CLK) // ALU s9: + if (ED) begin + case (ct) + 8,9,12: begin s9r<= s8r + s8d2r; // S9,S11 , S17 + s9i<=s8i + s8d2i ; end + 13: begin s9r<= s8d2r - s8r; // S20 + s9i<=s8d2i - s8i ; end + 10,11,14: begin s9r<=s8d4r - s8d2r; //S10, S12,S18 + s9i<=s8d4i - s8d2i; end + 15: begin s9r<=s8d4r + s8d2r; //S19 + s9i<=s8d4i + s8d2i; end + endcase + + s9d1r<=s9r; s9d1i<=s9i; s9d2r<=s9d1r; s9d2i<=s9d1i; + s9d3r<=s9d2r; s9d3i<=s9d2i; s9d4r<=s9d3r; s9d4i<=s9d3i; + s9d5r<=s9d4r; s9d5i<=s9d4i; s9d6r<=s9d5r; s9d6i<=s9d5i; + s9d7r<=s9d6r; s9d7i<=s9d6i; s9d8r<=s9d7r; s9d8i<=s9d7i; + + s9d9r<=s9d8r ; s9d9i<=s9d8i ; + if ((ct!=8)) begin + s9d10r<=s9d9r ; s9d10i<=s9d9i ; + s9d11r<=s9d10r ; s9d11i<=s9d10i ; end + if ((ct==4) ||(ct==5) ||(ct==7) ||(ct==9) ) begin + s9d12r<=s9d11r ; s9d12i<=s9d11i ; end + if ((ct==5))begin + s9d13r<=s9d12r ; s9d13i<=s9d12i ; end + + end + + + reg signed [nb+3:0] s10r,s10i; + reg signed [nb+3:0] s10dr,s10di; + + `ifdef FFT256paramifft //For IFFT + always @ (posedge CLK) begin // S10-- result adder + if (ED) + case (ct) + 13: begin s10r<=s9d4r -s9r ; // -- Y1 + s10i<=s9d4i -s9i ;end // + 15: begin + s10r<=s9d3r + s9d1r ; //-- Y3 + s10i<=s9d3i + s9d1i ; end + 1: begin + s10r<=s9d7r - s9d1r ; //-- Y5 + s10i<=s9d7i - s9d1i ; end + 3: begin + s10r<=s9d8r + s9d4r ; // -- Y7 + s10i<= s9d8i + s9d4i ;end + + 5:begin s10r<=s9d10r - s9d6r ; //-- Y9 + s10i<=s9d10i - s9d6i ; end + 7: begin + s10r<=s9d12r + s9d7r ; //-- Y11 + s10i<=s9d12i + s9d7i ; end + + 9: begin + s10r<= s9d12r - s9d10r ; // Y13 + s10i<=s9d12i - s9d10i ; end + + 11: begin + s10r<= s9d13r + s9d12r ; // Y15 + s10i<= s9d13i + s9d12i ; end + + endcase + s10dr<=s10r; s10di<=s10i; + end + `else + +// reg signed [nb+3:0] s10r,s10i,s10dr,s10di; + always @ (posedge CLK) begin // S10-- result adder + if (ED) + case (ct) + 13: begin s10r<=s9d4r +s9r ; // -- Y0 + s10i<=s9d4i +s9i ;end // + 15: begin + s10r<=s9d3r - s9d1r ; //-- Y3 + s10i<=s9d3i - s9d1i ; end + 1: begin + s10r<=s9d7r +s9d1r ; //-- Y5 + s10i<=s9d7i +s9d1i ; end + 3: begin + s10r<=s9d8r - s9d4r ; // -- Y7 + s10i<= s9d8i - s9d4i ;end + + 5:begin s10r<=s9d10r + s9d6r ; //-- Y9 + s10i<=s9d10i + s9d6i ; end + 7: begin + s10r<=s9d12r - s9d7r ; //-- Y11 + s10i<=s9d12i - s9d7i ; end + + 9: begin + s10r<= s9d12r + s9d10r ; // Y13 + s10i<=s9d12i + s9d10i ; end + + 11: begin + s10r<= s9d13r - s9d12r ; // Y15 + s10i<= s9d13i - s9d12i ; end + + endcase + s10dr<=s10r; s10di<=s10i; + end + `endif + +//wire signed [nb+3:0] s6sr,s6si; //saturation of results +// assign s6sr = (~s6r[nb+4]&&s6r[nb+3])? ((1'b1 <<(nb+3))-1) : s6r[nb+3:0]; +// assign s6si = (~s6i[nb+4]&&s6i[nb+3])? ((1'b1<<(nb+3))-1) : s6i[nb+3:0]; +// + + wire selo; + assign selo = ct-(ct/2)*2; + assign #1 DOR=selo? s10dr:s6r; + assign #1 DOI= selo? s10di:s6i; + +endmodule Index: trunk/SRC/fft8_3.v =================================================================== --- trunk/SRC/fft8_3.v (nonexistent) +++ trunk/SRC/fft8_3.v (revision 2) @@ -0,0 +1,361 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : First stage of FFT 128 processor +// FUNCTION: 8-point FFT +// FILES: FFT8_3.v - 1-st stage, contains +// MPUC707.v - multiplier to the factor 0.707. +// PROPERTIES: 1) Fully pipelined +// 2) Each clock cycle complex datum is entered +// and complex result is outputted +// 3) Has 8-clock cycle period starting with the START impulse +// and continuing forever +// 4) rounding is not used +// 5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms". +// 6)IFFT is performed by substituting the output result order to the reversed one +// (by exchanging - to + and + to -) +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +//Algorithm: +// procedure FFT8( +// D: in MEMOC8; -- input array +// DO:out MEMOC8) -- output ARRAY +// is +// variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex; +// variable s1,s2,s3,s4: complex; +// begin +// t1:=D(0) + D(4); +// m3:=D(0) - D(4); +// t2:=D(6) + D(2); +// m6:=CBASE_j*(D(6)-D(2)); +// t3:=D(1) + D(5); +// t4:=D(1) - D(5); +// t5:=D(3) + D(7); +// t6:=D(3) - D(7); +// t8:=t5 + t3; +// m5:=CBASE_j*(t5-t3); +// t7:=t1 + t2; +// m2:=t1 - t2; +// m0:=t7 + t8; +// m1:=t7 - t8; +// m4:=SQRT(0.5)*(t4 - t6); +// m7:=-CBASE_j*SQRT(0.5)*(t4 + t6); +// s1:=m3 + m4; +// s2:=m3 - m4; +// s3:=m6 + m7; +// s4:=m6 - m7; +// DO(0):=m0; +// DO(4):=m1; +// DO(1):=s1 + s3; +// DO(7):=s1 - s3; +// DO(2):=m2 + m5; +// DO(6):=m2 - m5; +// DO(5):=s2 + s4; +// DO(3):=s2 - s4; +// end procedure; +// +// Note that MPUC707 is multiplied a complex data for 2 clk cycles +//_____________________________________________________________ + +`timescale 1ps / 1ps +`include "FFT128_CONFIG.inc" + +module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY ); + `FFT128paramnb + + input ED ; + wire ED ; + input RST ; + wire RST ; + input CLK ; + wire CLK ; + input [nb-1:0] DII ; + wire [nb-1:0] DII ; + input START ; + wire START ; + input [nb-1:0] DIR ; + wire [nb-1:0] DIR ; + + output [nb+2:0] DOI ; + wire [nb+2:0] DOI ; + output [nb+2:0] DOR ; + wire [nb+2:0] DOR ; + output RDY ; + reg RDY ; + + reg [2:0] ct; //main phase counter + reg [4:0] ctd; //delay counter + + always @( posedge CLK) begin //Control counter + // + if (RST) begin + ct<=0; + ctd<=16; + RDY<=0; end + else if (START) begin + ct<=0; + ctd<=0; + RDY<=0; end + else if (ED) begin + RDY<=0; + ct<=ct+1; + if (ctd !=5'b10000) + ctd<=ctd+1; + if (ctd==15 ) + RDY<=1; + end + + end + + reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i; + always @(posedge CLK) // input register file + begin + if (ED) begin + dr<=DIR; + d1r<=dr; + d2r<=d1r; + d3r<=d2r; + d4r<=d3r; + di<=DII; + d1i<=di; + d2i<=d1i; + d3i<=d2i; + d4i<=d3i; + end + end + + reg signed [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r,m3r; + reg signed [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i,m3i; + always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed + if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin + s1r<=d4r + dr ; + s1i<=d4i + di ; + s2r<=d4r - dr ; + s2i<= d4i - di; + end + if (ED) begin + s1d1r<=s1r; + s1d2r<=s1d1r; + s1d1i<=s1i; + s1d2i<=s1d1i; + if (ct==0 || ct==1) begin //## note for vhdl + s1d3r<=s1d2r; + s1d3i<=s1d2i; + end + if (ct==6 || ct==7 || ct==0) begin + s2d1r<=s2r; + s2d2r<=s2d1r; + s2d1i<=s2i; + s2d2i<=s2d1i; + end + if (ct==0) begin + s2d3r<=s2d2r; + s2d3i<=s2d2i; + end + if (ct==7) begin + m3r<=s2d3r; + m3i<=s2d3i; + end + end + end + + + reg signed [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r,s3d7r; + reg signed [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i,s3d7i; + always @(posedge CLK) begin //ALU S3: + if (ED) + case (ct) + 0: begin s3r<= s1d2r+s1r; //t7 + s3i<= s1d2i+ s1i ;end + 1: begin s3r<= s1d3r - s1d1r; //m2 + s3i<= s1d3i - s1d1i; end + 2: begin s3r<= s1d3r +s1r; //t8 + s3i<= s1d3i+ s1i ; end + 3: begin s3r<= s1d3r - s1r; // + s3i<= s1d3i - s1i ; end + endcase + + s3d1r<=s3r; s3d1i<=s3i; + s3d2r<=s3d1r; s3d2i<=s3d1i; + s3d3r<=s3d2r; s3d3i<=s3d2i; + if (ct==4 || ct==5 || ct==6|| ct==7) begin + s3d4r<=s3d3r; s3d4i<=s3d3i; + s3d5r<=s3d4r; s3d5i<=s3d4i; //t8 + end + if ( ct==6|| ct==7) begin + s3d6r<=s3d5r; s3d6i<=s3d5i; //m2 + s3d7r<=s3d6r; s3d7i<=s3d6i; //t7 + end + end + + + always @ (posedge CLK) begin // S4 + if (ED) begin + if (ct==1) begin + s4r<= s2d2r + s2r; + s4i<= s2d2i + s2i; end + else if (ct==2) begin + s4r<=s2d2r - s2r; + s4i<= s2d2i - s2i; + end + end + end + + wire ds,mpyj; + assign ds = (ct==2 || ct==4 ); + assign mpyj = (ct==2); // the multiplication by 0707 is followed by *J + wire signed [nb+1:0] m4m7r,m4m7i; + + MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(ds), .MPYJ(mpyj) , + .DR(s4r),.DI(s4i), + .DOR(m4m7r) ,.DOI(m4m7i) ); + + reg signed [nb+1:0] sjr,sji, m7r,m7i; + always @ (posedge CLK) begin //multiply by J + if (ED) begin + if (ct==6) begin + m7r<=m4m7r; //m7 + m7i<=m4m7i; + end + case (ct) + 6: begin sjr<= s2d1i; //m6 + sji<=0 - s2d1r; end + 1: begin sjr<= s3d4i; //m5 + sji<=0 - s3d4r; end + endcase + + end + end + + reg signed [nb+2:0] s7r,s7i,rs3r,rs3i; + always @ (posedge CLK) // S7: + if (ED) + case (ct) + 0:begin s7r<= sjr + m7r; + s7i<= sji + m7i; end + 1:begin s7r<= sjr - m7r; + s7i<= sji - m7i; + rs3r<=s7r; + rs3i<=s7i; end + endcase + + reg signed [nb+2:0] s5r,rs1r; + reg signed [nb+2:0] s5i,rs1i; + always @ (posedge CLK) // S5: + if (ED) + case (ct) + 0:begin s5r<= m3r + m4m7r; + s5i<= m3i + m4m7i; end + 1:begin s5r<= m3r - m4m7r; + s5i<= m3i - m4m7i; + rs1r<=s5r; + rs1i<=s5i; end + endcase + + reg signed [nb+3:0] s6r,s6i ; + `ifdef FFT128paramifft + always @ (posedge CLK) begin // S6-- result adder + if (ED) + case (ct) + 0: begin s6r<=s3d7r +s3d5r ; // -- D0 + s6i<=s3d7i +s3d5i ;end //-- D0 + 1: begin + s6r<=s5r - s7r ; //-- D1 + s6i<=s5i - s7i ; end + 2: begin + s6r<=s3d6r -sjr ; //-- D2 + s6i<=s3d6i -sji ; end + 3: begin + s6r<=s5r + s7r ; // -- D3 + s6i<= s5i + s7i ;end + + 4:begin s6r<=s3d7r - s3d5r ; //-- D4 + s6i<=s3d7i - s3d5i ; end + 5: begin + s6r<=s5r - s7r ; //-- D5 + s6i<=s5i - s7i ; end + + 6: begin + s6r<= s3d6r + sjr ; // D6 + s6i<=s3d6i + sji ; end + + 7: begin + s6r<= rs1r + rs3r ; // D0 + s6i<= rs1i + rs3i ; end + + endcase + end + + `else + always @ (posedge CLK) begin // S6-- result adder + if (ED) + case (ct) + 0: begin s6r<=s3d7r +s3d5r ; // -- D0 + s6i<=s3d7i +s3d5i ;end //-- D0 + 1: begin + s6r<=s5r + s7r ; //-- D1 + s6i<=s5i + s7i ; end + 2: begin + s6r<=s3d6r +sjr ; //-- D2 + s6i<=s3d6i +sji ; end + 3: begin + s6r<=s5r - s7r ; // -- D3 + s6i<= s5i - s7i ;end + + 4:begin s6r<=s3d7r - s3d5r ; //-- D4 + s6i<=s3d7i - s3d5i ; end + 5: begin + s6r<=s5r + s7r ; //-- D5 + s6i<=s5i + s7i ; end + + 6: begin + s6r<= s3d6r - sjr ; // D6 + s6i<=s3d6i - sji ; end + + 7: begin + s6r<= rs1r - rs3r ; // D0 + s6i<= rs1i - rs3i ; end + + endcase + end + `endif + + assign #1 DOR=s6r[nb+2:0]; + assign #1 DOI= s6i[nb+2:0]; + +endmodule Index: trunk/SRC/bufram128c_1.v =================================================================== --- trunk/SRC/bufram128c_1.v (nonexistent) +++ trunk/SRC/bufram128c_1.v (revision 2) @@ -0,0 +1,112 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Store buffer +// FUNCTION: FIFO - buffer with direct input order and 8-th inverse output order +// FILES: BUFRAM128C_1.v - 1-st,2-nd,3-d data buffer, contains: +// RAM2x128C.v - dual ported synchronous RAM, contains: +// RAM128.v -single ported synchronous RAM +// PROPERTIES: 1) Has the volume of 2x128 complex data +// 2) Contains 2- port RAM and address counter +// 3)Has 128-clock cycle period starting with the START impulse +// and continuing forever +// 4) Signal RDY precedes the 1-st correct datum outputted from the buffer +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module BUFRAM128C_1 ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI ); + `FFT128paramnb + output RDY ; + reg RDY ; + output [nb-1:0] DOR ; + wire [nb-1:0] DOR ; + output [nb-1:0] DOI ; + wire [nb-1:0] DOI ; + + input CLK ; + wire CLK ; + input RST ; + wire RST ; + input ED ; + wire ED ; + input START ; + wire START ; + input [nb-1:0] DR ; + wire [nb-1:0] DR ; + input [nb-1:0] DI ; + wire [nb-1:0] DI ; + + wire odd, we; + wire [6:0] addrw,addrr; + reg [7:0] addr; + reg [8:0] ct2; //counter for the RDY signal + + always @(posedge CLK) // CTADDR + begin + if (RST) begin + addr<=7'b000_0000; + ct2<= 8'b1000_0001; + RDY<=1'b0; end + else if (START) begin + addr<=7'b000_0000; + ct2<= 8'b0000_0000; + RDY<=1'b0;end + else if (ED) begin + RDY<=1'b0; + addr<=addr+1; + if (ct2!=129) + ct2<=ct2+1; + if (ct2==128) + RDY<=1'b1; + end + end + + +assign addrw= addr[6:0]; +assign odd=addr[7]; // signal which switches the 2 parts of the buffer +assign addrr={addr[2 : 0], addr[6 : 3]}; // 16-th inverse output address +assign we = ED; + + RAM2x128C #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd), + .ADDRW(addrw), .ADDRR(addrr), + .DR(DR),.DI(DI), + .DOR(DOR), .DOI(DOI)); + +endmodule Index: trunk/SRC/bufram128c_2.v =================================================================== --- trunk/SRC/bufram128c_2.v (nonexistent) +++ trunk/SRC/bufram128c_2.v (revision 2) @@ -0,0 +1,112 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Store buffer +// FUNCTION: FIFO - buffer with direct input order and 8-th inverse output order +// FILES: BUFRAM128C_2.v - 1-st,2-nd,3-d data buffer, contains: +// RAM2x128C.v - dual ported synchronous RAM, contains: +// RAM128.v -single ported synchronous RAM +// PROPERTIES: 1) Has the volume of 2x128 complex data +// 2) Contains 2- port RAM and address counter +// 3)Has 128-clock cycle period starting with the START impulse +// and continuing forever +// 4) Signal RDY precedes the 1-st correct datum outputted from the buffer +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module BUFRAM128C_2 ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI ); + `FFT128paramnb + output RDY ; + reg RDY ; + output [nb-1:0] DOR ; + wire [nb-1:0] DOR ; + output [nb-1:0] DOI ; + wire [nb-1:0] DOI ; + + input CLK ; + wire CLK ; + input RST ; + wire RST ; + input ED ; + wire ED ; + input START ; + wire START ; + input [nb-1:0] DR ; + wire [nb-1:0] DR ; + input [nb-1:0] DI ; + wire [nb-1:0] DI ; + + wire odd, we; + wire [6:0] addrw,addrr; + reg [7:0] addr; + reg [8:0] ct2; //counter for the RDY signal + + always @(posedge CLK) // CTADDR + begin + if (RST) begin + addr<=7'b000_0000; + ct2<= 8'b1000_0001; + RDY<=1'b0; end + else if (START) begin + addr<=7'b000_0000; + ct2<= 8'b0000_0000; + RDY<=1'b0;end + else if (ED) begin + RDY<=1'b0; + addr<=addr+1; + if (ct2!=129) + ct2<=ct2+1; + if (ct2==128) + RDY<=1'b1; + end + end + + +assign addrw= addr[6:0]; +assign odd=addr[7]; // signal which switches the 2 parts of the buffer +assign addrr={addr[3 : 0], addr[6 : 4]}; // 8-th inverse output address +assign we = ED; + + RAM2x128C #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd), + .ADDRW(addrw), .ADDRR(addrr), + .DR(DR),.DI(DI), + .DOR(DOR), .DOI(DOI)); + +endmodule Index: trunk/SRC/mpuc541.v =================================================================== --- trunk/SRC/mpuc541.v (nonexistent) +++ trunk/SRC/mpuc541.v (revision 2) @@ -0,0 +1,126 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Complex Multiplier by 0.5411 +// FUNCTION: Constant multiplier to cos(PI/8)-cos(3*PI/8) =0.5411 +// FILES: MPU�541.v +// PROPERTIES: 1) Is based on shifts right and add +// 2) for short input bit width 0.541 is approximated as 0_1000_1010_1 +// 3) for medium bit width 1.3066 is approximated as 0_1000_1010_1001 +// 4) for long bit width 1.30656 is approximated as 0_1000_1010_1000_11 +// 5) hardware is 3,or4, or 5 adders +1 +// 6) MPYJ switches multiply by j +// 6) A complex data is multiplied for 2 cycles, latent delay=4 +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`include "FFT128_CONFIG.inc" + +module MPUC541 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI, ); + `FFT128paramnb + + input CLK ; + wire CLK ; + input DS ; + wire DS ; + input ED; //data strobe + input MPYJ ; //the result is multiplied by -j + wire MPYJ ; + input [nb-1:0] DR ; + wire signed [nb-1:0] DR ; + input [nb-1:0] DI ; + wire signed [nb-1:0] DI ; + + output [nb-1:0] DOR ; + reg [nb-1:0] DOR ; + output [nb-1:0] DOI ; + reg [nb-1:0] DOI ; + + reg signed [nb :0] dx5; + reg signed [nb :0] dx3; + reg signed [nb-1 :0] dii; + reg signed [nb-1 : 0] dt; + wire signed [nb+1 : 0] dx5p; + wire signed [nb+1 : 0] dot; + reg edd,edd2, edd3; //delayed data enable impulse + reg mpyjd,mpyjd2,mpyjd3; + reg [nb-1:0] doo ; + reg [nb-1:0] droo ; + + always @(posedge CLK) + begin + if (ED) begin + edd<=DS; + edd2<=edd; + edd3<=edd2; + mpyjd<=MPYJ; + mpyjd2<=mpyjd; + mpyjd3<=mpyjd2; + if (DS) begin // 0_1000_1010_1000_11 + dx5<=DR+(DR >>>2); //multiply by 5 + dx3<=DR+(DR >>>1); //multiply by 3, + dt<=DR; + dii<=DI; + end + else begin + dx5<=dii+(dii >>>2); //multiply by 5 + dx3<=dii +(dii >>>1); //multiply by 3 + dt<=dii; + end + doo<=dot >>>2; + droo<=doo; + if (edd3) + if (mpyjd3) begin + DOR<=doo; + DOI<= - droo; end + else begin + DOR<=droo; + DOI<= doo; end + end + end + + assign dx5p=(dt<<1)+(dx5>>>3); // multiply by 0_1000_101 + + `ifdef FFT128bitwidth_coef_high + assign dot= (dx5p+(dt>>>7) +(dx3>>>11));// multiply by // 0_1000_1010_1000_11 + `else + assign dot= dx5p+(dt>>>7); + `endif + + + +endmodule Index: trunk/SRC/cnorm_1.v =================================================================== --- trunk/SRC/cnorm_1.v (nonexistent) +++ trunk/SRC/cnorm_1.v (revision 2) @@ -0,0 +1,132 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Normalization unit +// FUNCTION: shifting left up to 3 bits +// FILES: CNORM.v +// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT +// 2) Is registered +// 3) Overflow detector detects the overflow event +// by the given shift condition. The detector is zeroed by the START signal +// 4) RDY is the START signal delayed to a single clock cycle +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// File : +// Generated : +// +// Description : +// +//----------------------------------------------------------------------------- +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module CNORM_1 ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI ); + `FFT128paramnb + + output OVF ; + reg OVF ; + output RDY ; + reg RDY ; + output [nb+1:0] DOR ; + wire [nb+1:0] DOR ; + output [nb+1:0] DOI ; + wire [nb+1:0] DOI ; + + input CLK ; + wire CLK ; + input ED ; + wire ED ; + input START ; + wire START ; + input [nb+2:0] DR ; + wire [nb+2:0] DR ; + input [nb+2:0] DI ; + wire [nb+2:0] DI ; + input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits + wire [1:0] SHIFT ; + + wire signed [nb+2:0] diri,diii; + assign diri = DR << SHIFT; + assign diii = DI << SHIFT; + + reg [nb+2:0] dir,dii; + + `ifdef FFT128round //rounding + always @( posedge CLK ) begin + if (ED) begin + if (diri[nb+2] && ~diri[0]) // <0 with LSB=00 + dir<=diri; + else dir<=diri+2; + if (diii[nb+2] && ~diii[0]) + dii<=diii; + else dii<=diii+2; + end + end + + `else //truncation + always @( posedge CLK ) begin + if (ED) begin + dir<=diri; + dii<=diii; + end + end + + + `endif + + always @( posedge CLK ) begin + if (ED) begin + RDY<=START; + if (START) + OVF<=0; + else + case (SHIFT) + 2'b01 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]); + 2'b10 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]) || + (DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]); + 2'b11 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1])|| + (DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]) || + (DR[nb+2] != DR[nb-1]) || (DI[nb+2] != DI[nb-1]); + endcase + end + end + + assign DOR= dir[nb+2:1]; + assign DOI= dii[nb+2:1]; + +endmodule Index: trunk/SRC/cnorm_2.v =================================================================== --- trunk/SRC/cnorm_2.v (nonexistent) +++ trunk/SRC/cnorm_2.v (revision 2) @@ -0,0 +1,132 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Normalization unit +// FUNCTION: shifting left up to 3 bits +// FILES: CNORM.v +// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT +// 2) Is registered +// 3) Overflow detector detects the overflow event +// by the given shift condition. The detector is zeroed by the START signal +// 4) RDY is the START signal delayed to a single clock cycle +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// File : +// Generated : +// +// Description : +// +//----------------------------------------------------------------------------- +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module CNORM_2 ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI ); + `FFT128paramnb + + output OVF ; + reg OVF ; + output RDY ; + reg RDY ; + output [nb+1:0] DOR ; + wire [nb+1:0] DOR ; + output [nb+1:0] DOI ; + wire [nb+1:0] DOI ; + + input CLK ; + wire CLK ; + input ED ; + wire ED ; + input START ; + wire START ; + input [nb+3:0] DR ; + wire [nb+3:0] DR ; + input [nb+3:0] DI ; + wire [nb+3:0] DI ; + input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits + wire [1:0] SHIFT ; + + wire signed [nb+3:0] diri,diii; + assign diri = DR << SHIFT; + assign diii = DI << SHIFT; + + reg [nb+3:0] dir,dii; + + `ifdef FFT128round //rounding + always @( posedge CLK ) begin + if (ED) begin + if (diri[nb+3] && ~diri[0]) // <0 with LSB=00 + dir<=diri; + else dir<=diri+2; + if (diii[nb+3] && ~diii[0]) + dii<=diii; + else dii<=diii+2; + end + end + + `else //truncation + always @( posedge CLK ) begin + if (ED) begin + dir<=diri; + dii<=diii; + end + end + + + `endif + + always @( posedge CLK ) begin + if (ED) begin + RDY<=START; + if (START) + OVF<=0; + else + case (SHIFT) + 2'b01 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]); + 2'b10 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]) || + (DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]); + 2'b11 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2])|| + (DR[nb+3] != DR[nb]) || (DI[nb+3] != DI[nb]) || + (DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]); + endcase + end + end + + assign DOR= dir[nb+3:2]; + assign DOI= dii[nb+3:2]; + +endmodule Index: trunk/SRC/mpuc924_383.v =================================================================== --- trunk/SRC/mpuc924_383.v (nonexistent) +++ trunk/SRC/mpuc924_383.v (revision 2) @@ -0,0 +1,136 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Complex Multiplier by 0.924 +// FUNCTION: Constant multiplier to cos(PI/8)-cos(3*PI/8) =0.9239 +// FILES: MPU�924.v +// PROPERTIES: 1) Is based on shifts right and add +// 2) for short input bit width 0.924 is approximated as 0.1110_1100_1 =1_00T0_1100_1 +// 3) for long bit width 0.9239 is appr. as 0.1110_1100_1000_0011 =1_00T0_1100_1000_0011 +// 4) for short input bit width 0.383 is approximated as 0_0110_001 +// 5) for long bit width 0.3827 is approximated as 0_0110_0001_1111_1 = 0_0110_0010_0000_T// 4) hardware is 4, or 5 adders +1 +// 6) MPYJ switches multiply by j , C383=1 selects the coefficient 0.383 +// 7) A complex data is multiplied for 2 cycles, latent delay=4 +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`include "FFT128_CONFIG.inc" + +module MPUC924_383 ( CLK,DS ,ED, MPYJ,C383,DR,DI ,DOR ,DOI, ); + `FFT128paramnb + + input CLK ; + wire CLK ; + input DS ; + wire DS ; + input ED; //data strobe + input MPYJ ; //the result is multiplied by -j + wire MPYJ ; + input C383 ; //the coefficient is 0.383 + wire C383 ; + input [nb-1:0] DR ; + wire signed [nb-1:0] DR ; + input [nb-1:0] DI ; + wire signed [nb-1:0] DI ; + + output [nb-1:0] DOR ; + reg [nb-1:0] DOR ; + output [nb-1:0] DOI ; + reg [nb-1:0] DOI ; + + reg signed [nb+1 :0] dx7; + reg signed [nb :0] dx3; + reg signed [nb-1 :0] dii; + reg signed [nb-1 : 0] dt; + wire signed [nb+1 : 0] dx5p; + wire signed [nb+1 : 0] dot; + reg edd,edd2, edd3; //delayed data enable impulse + reg mpyjd,mpyjd2,mpyjd3,c3d,c3d2,c3d3; + reg [nb-1:0] doo ; + reg [nb-1:0] droo ; + + always @(posedge CLK) + begin + if (ED) begin + edd<=DS; + edd2<=edd; + edd3<=edd2; + mpyjd<=MPYJ; + mpyjd2<=mpyjd; + mpyjd3<=mpyjd2; + c3d<=C383; + c3d2<=c3d; + c3d3<=c3d2; + if (DS) begin // 1_00T0_1100_1000_0011 + dx7<=(DR<<2) - (DR >>>1); //multiply by 7 + dx3<=DR+(DR >>>1); //multiply by 3, + dt<=DR; + dii<=DI; + end + else begin + dx7<=(dii<<2) - (dii >>>1); //multiply by 7 + dx3<=dii +(dii >>>1); //multiply by 3 + dt<=dii; + end + if (c3d || c3d2) doo<=dot >>>2; + else doo<=dot >>>2; + + droo<=doo; + if (edd3) + if (mpyjd3) begin + DOR<=doo; + DOI<= - droo; end + else begin + DOR<=droo; + DOI<= doo; end + end + end + + assign dx5p= (c3d || c3d2)? ((dt>>>5)+dx3) : ( dx7+(dx3>>>3)); // multiply by 0_0110_001 + //or multiply by 1_00T0_11 + + `ifdef FFT128bitwidth_coef_high + assign dot= (c3d || c3d2)? dx5p-(dt>>>11) :(dx5p+((dt>>>7) +(dx3>>>13)));// by 0_0110_0010_0000_T + //or multiply by 1_00T0_1100_1000_0011 + `else + assign dot= (c3d || c3d2)? dx5p : (dx5p+(dt>>>7)); + //or multiply by 1_00T0_1100_1 + `endif + + + +endmodule Index: trunk/SRC/mpuc707.v =================================================================== --- trunk/SRC/mpuc707.v (nonexistent) +++ trunk/SRC/mpuc707.v (revision 2) @@ -0,0 +1,123 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Complex Multiplier by 0.7071 +// FUNCTION: Constant multiplier +// FILES: MPU707.v +// PROPERTIES: 1) Is based on shifts right and add +// 2) for short input bit width 0.7071 is approximated as 10110101 then rounding is not used +// 3) for long input bit width 0.7071 is approximated as 10110101000000101 +// 4) hardware is 4 or 5 adders +// 5) MPYJ switches multiply by j +// 6) A complex data is multiplied for 2 cycles +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`include "FFT128_CONFIG.inc" + +module MPUC707 ( CLK,ED, DS, MPYJ,DR,DI ,DOR ,DOI, ); + `FFT128paramnb +// MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(es), .MPYJ(mpyj) , + + input CLK ; + wire CLK ; + input DS ; //data strobe + wire DS ; + input ED; //slowdown + input MPYJ ; //the result is multiplied by -j + wire MPYJ ; + input [nb-1:0] DR ; + wire signed [nb-1:0] DR ; + input [nb-1:0] DI ; + wire signed [nb-1:0] DI ; + + output [nb-1:0] DOR ; + reg [nb-1:0] DOR ; + output [nb-1:0] DOI ; + reg [nb-1:0] DOI ; + + reg signed [nb+1 :0] dx5; + reg signed [nb : 0] dt; + reg signed [nb-1 : 0] dii; + wire signed [nb+2 : 0] dx5p; + wire signed [nb+3 : 0] dot; + reg edd,edd2, edd3; //delayed data enable impulse + reg mpyjd,mpyjd2,mpyjd3; + reg [nb-1:0] doo ; + reg [nb-1:0] droo ; + + always @(posedge CLK) + begin + if (ED) begin + edd<=DS; + edd2<=edd; + edd3<=edd2; + mpyjd<=MPYJ; + mpyjd2<=mpyjd; + mpyjd3<=mpyjd2; + if (DS) begin + dx5<=DR+(DR <<2); //multiply by 5 + dt<=DR; + dii<=DI; + end + else begin + dx5<=dii+(dii <<2); //multiply by 5 + dt<=dii; + end + doo<=(dot >>>4) ; + droo<=doo; + if (edd3) + if (mpyjd3) begin + DOR<=doo; + DOI<= - droo; end + else begin + DOR<=droo; + DOI<= doo; end + end + end + + assign dx5p=(dx5<<1)+(dx5>>>2); // multiply by 101101 + + `ifdef FFT128bitwidth_coef_high + assign dot= dx5p+(dt>>>4)+(dx5>>>12);// (dt>>>9); // multiply by 10110101000000101 + `else + assign dot= dx5p+(dt>>>4) ; // multiply by 10110101 + `endif + + + +endmodule Index: trunk/SRC/fft128_config.inc =================================================================== --- trunk/SRC/fft128_config.inc (nonexistent) +++ trunk/SRC/fft128_config.inc (revision 2) @@ -0,0 +1,65 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Parameter file +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +`timescale 10 ps / 1ps + +//input data bit width +`define FFT128paramnb parameter nb=16; + +//twiddle factor bit width +`define FFT128paramnw parameter nw=16; + +//when is absent then FFT, when is present then IFFT +//`define FFT128paramifft ; + +//buffer number 2 or 3 +`define FFT128parambuffers3 + +// buffer type: 1 ports in RAMS else -2 ports RAMS +//`define FFT128bufferports1 + +//Coeficient bit width is increased to high +`define FFT128bitwidth_coef_high + + +//Rounding butterfly results +//`define FFT128round \ No newline at end of file Index: trunk/SRC/ram128.v =================================================================== --- trunk/SRC/ram128.v (nonexistent) +++ trunk/SRC/ram128.v (revision 2) @@ -0,0 +1,76 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : 1-port synchronous RAM +// FUNCTION: 1-port synchronous RAM +// FILES: RAM256.v -single ported synchronous RAM +// PROPERTIES: 1) Has the volume of 256 data +// 2) RAM is synchronous one, the read datum is outputted in 2 cycles after the address setting +// 3) Can be substituted to any 2-port synchronous RAM +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module RAM128 ( CLK, ED,WE ,ADDR ,DI ,DO ); + `FFT128paramnb + + output [nb-1:0] DO ; + reg [nb-1:0] DO ; + input CLK ; + wire CLK ; + input ED; + input WE ; + wire WE ; + input [6:0] ADDR ; + wire [6:0] ADDR ; + input [nb-1:0] DI ; + wire [nb-1:0] DI ; + reg [nb-1:0] mem [127:0]; + reg [6:0] addrrd; + + always @(posedge CLK) begin + if (ED) begin + if (WE) mem[ADDR] <= DI; + addrrd <= ADDR; //storing the address + DO <= mem[addrrd]; // registering the read datum + end + end + + +endmodule Index: trunk/SRC/fft128.v =================================================================== --- trunk/SRC/fft128.v (nonexistent) +++ trunk/SRC/fft128.v (revision 2) @@ -0,0 +1,187 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Top level of the high speed FFT core +// FUNCTION: Structural model of the high speed 128-complex point FFT +// core intended for synthesizing +// for any type FPGAs and ASIC. +// FILES: FFT128.v - root unit, this file, +// FFT128_CONFIG.inc - core configuration file +// BUFRAM128C.v - 1-st,2-nd,3-d data buffer, contains: +// RAM2x128C.v - dual ported synchronous RAM, contains: +// RAM128.v -single ported synchronous RAM +// FFT16.v- 1-st,2-nd stages implementing 16-point FFTs, contains +// MPU707.v, MPU707_2.v - multiplier to the factor 0.707. +// ROTATOR256.v - unit for rotating complex vectors, contains +// WROM256.v - ROM of twiddle factors. +// CNORM.v - normalization stages +// UNFFT256_TB.v - testbench file, includes: +// Wave_ROM256.v - ROM with input data and result reference data +// SineROM256_gen.pl - PERL script to generate the Wave_ROM256.v file +// +// PROPERTIES: 1. Fully pipelined, 1 complex data in, 1 complex result out each clock cycle +// 2. Input data, output data, coefficient widths are adjustable in range 8..16 +// 3. Normalization stages trigger the data overflow and shift data right +// to prevent the overflow +// 4. Core can contain 2 or 3 data buffers. In the configuration of 2 buffers +// the results are in the shuffled order but provided with the proper address. +// 5. The core operation can be slowed down by the control of the ED input +// 6. The reset RST is synchronous one +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module FFT128 ( CLK ,RST ,ED ,START ,SHIFT ,DR ,DI ,RDY ,OVF1 ,OVF2 ,ADDR ,DOR ,DOI ); + `FFT128paramnb //nb is the data bit width + + output RDY ; // in the next cycle after RDY=1 the 0-th result is present + wire RDY ; + output OVF1 ; // 1 signals that an overflow occured in the 1-st stage + wire OVF1 ; + output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage + wire OVF2 ; + output [6:0] ADDR ; //result data address/number + wire [6:0] ADDR ; + output [nb+3:0] DOR ;//Real part of the output data, + wire [nb+3:0] DOR ; // the bit width is nb+4, can be decreased when instantiating the core + output [nb+3:0] DOI ;//Imaginary part of the output data + wire [nb+3:0] DOI ; + + input CLK ; //Clock signal is less than 300 MHz for the Xilinx Virtex5 FPGA + wire CLK ; + input RST ; //Reset signal, is the synchronous one with respect to CLK + wire RST ; + input ED ; //=1 enables the operation (eneabling CLK) + wire ED ; + input START ; // its falling edge starts the transform or the serie of transforms + wire START ; // and resets the overflow detectors + input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage + wire [3:0] SHIFT ; // bits 3,2 -shift left code in the 2-nd stage + input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after + wire [nb-1:0] DR ; // the START signal or after 255-th data of the previous transform + input [nb-1:0] DI ; //Imaginary part of the input data + wire [nb-1:0] DI ; + + wire [nb-1:0] dr1,di1; + wire [nb+1:0] dr3,di3,dr4,di4, dr5,di5 ; + wire [nb+2:0] dr2,di2; + wire [nb+5:0] dr6,di6; + wire [nb+3:0] dr7,di7,dr8,di8; + wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8; + reg [7:0] addri ; + // input buffer =8-bit inversion ordering + BUFRAM128C_1 #(nb) U_BUF1(.CLK(CLK), .RST(RST), .ED(ED), .START(START), + .DR(DR), .DI(DI), .RDY(rdy1), .DOR(dr1), .DOI(di1)); + + //1-st stage of FFT + FFT8 #(nb) U_FFT1(.CLK(CLK), .RST(RST), .ED(ED), + .START(rdy1),.DIR(dr1),.DII(di1), + .RDY(rdy2), .DOR(dr2),. DOI(di2)); + + wire [1:0] shiftl= SHIFT[1:0]; + CNORM_1 #(nb) U_NORM1( .CLK(CLK), .ED(ED), //1-st normalization unit + .START(rdy2), // overflow detector reset + .DR(dr2), .DI(di2), + .SHIFT(shiftl), //shift left bit number + .OVF(OVF1), + .RDY(rdy3), + .DOR(dr3),.DOI(di3)); + + // rotator to the angles proportional to PI/64 + ROTATOR128 #(nb+2) U_MPU (.CLK(CLK),.RST(RST),.ED(ED), + .START(rdy3),. DR(dr3),.DI(di3), + .RDY(rdy4), .DOR(dr4), .DOI(di4)); + + BUFRAM128C_2 #(nb+2) U_BUF2(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering + .START(rdy4),. DR(dr4),.DI(di4), + .RDY(rdy5), .DOR(dr5), .DOI(di5)); + + //2-nd stage of FFT + FFT16 #(nb+2) U_FFT2(.CLK(CLK), .RST(RST), .ED(ED), + .START(rdy5),. DIR(dr5),.DII(di5), + .RDY(rdy6), .DOR(dr6), .DOI(di6)); + + wire [1:0] shifth= SHIFT[3:2]; + //2-nd normalization unit + CNORM_2 #(nb+2) U_NORM2 ( .CLK(CLK), .ED(ED), + .START(rdy6), // overflow detector reset + .DR(dr6), .DI(di6), + .SHIFT(shifth), //shift left bit number + .OVF(OVF2), + .RDY(rdy7), + .DOR(dr7), .DOI(di7)); + + + BUFRAM128C #(nb+4) Ubuf3(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering + .START(rdy7),. DR(dr7),.DI(di7), + .RDY(rdy8), .DOR(dr8), .DOI(di8)); + + + + + `ifdef FFT128parambuffers3 // 3-data buffer configuratiion + always @(posedge CLK) begin //POINTER to the result samples + if (RST) + addri<=7'b000_0000; + else if (rdy8==1 ) + addri<=7'b000_0000; + else if (ED) + addri<=addri+1; + end + + assign ADDR= addri ; + assign DOR=dr8; + assign DOI=di8; + assign RDY=rdy8; + + `else + always @(posedge CLK) begin //POINTER to the result samples + if (RST) + addri<=7'b000_0000; + else if (rdy7) + addri<=7'b000_0000; + else if (ED) + addri<=addri+1; + end + assign #1 ADDR= {addri[2:0] , addri[6:3]} ; + assign #2 DOR= dr7; + assign #2 DOI= di7; + assign RDY= rdy7; + `endif +endmodule Index: trunk/SRC/bufram128c.v =================================================================== --- trunk/SRC/bufram128c.v (nonexistent) +++ trunk/SRC/bufram128c.v (revision 2) @@ -0,0 +1,112 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : Store buffer +// FUNCTION: FIFO - buffer with direct input order and 8-th inverse output order +// FILES: BUFRAM128C_2.v - 1-st,2-nd,3-d data buffer, contains: +// RAM2x128C.v - dual ported synchronous RAM, contains: +// RAM128.v -single ported synchronous RAM +// PROPERTIES: 1) Has the volume of 2x128 complex data +// 2) Contains 2- port RAM and address counter +// 3)Has 128-clock cycle period starting with the START impulse +// and continuing forever +// 4) Signal RDY precedes the 1-st correct datum outputted from the buffer +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`timescale 1 ns / 1 ps +`include "FFT128_CONFIG.inc" + +module BUFRAM128C_2 ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI ); + `FFT128paramnb + output RDY ; + reg RDY ; + output [nb-1:0] DOR ; + wire [nb-1:0] DOR ; + output [nb-1:0] DOI ; + wire [nb-1:0] DOI ; + + input CLK ; + wire CLK ; + input RST ; + wire RST ; + input ED ; + wire ED ; + input START ; + wire START ; + input [nb-1:0] DR ; + wire [nb-1:0] DR ; + input [nb-1:0] DI ; + wire [nb-1:0] DI ; + + wire odd, we; + wire [6:0] addrw,addrr; + reg [7:0] addr; + reg [8:0] ct2; //counter for the RDY signal + + always @(posedge CLK) // CTADDR + begin + if (RST) begin + addr<=7'b000_0000; + ct2<= 8'b1000_0001; + RDY<=1'b0; end + else if (START) begin + addr<=7'b000_0000; + ct2<= 8'b0000_0000; + RDY<=1'b0;end + else if (ED) begin + RDY<=1'b0; + addr<=addr+1; + if (ct2!=129) + ct2<=ct2+1; + if (ct2==128) + RDY<=1'b1; + end + end + + +assign addrw= addr[6:0]; +assign odd=addr[7]; // signal which switches the 2 parts of the buffer +assign addrr={addr[3 : 0], addr[6 : 4]}; // 8-th inverse output address +assign we = ED; + + RAM2x128C #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd), + .ADDRW(addrw), .ADDRR(addrr), + .DR(DR),.DI(DI), + .DOR(DOR), .DOI(DOI)); + +endmodule Index: trunk/SRC/rotator128_v.v =================================================================== --- trunk/SRC/rotator128_v.v (nonexistent) +++ trunk/SRC/rotator128_v.v (revision 2) @@ -0,0 +1,134 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FFT/IFFT 128 points transform //// +//// //// +//// Authors: Anatoliy Sergienko, Volodya Lepeha //// +//// Company: Unicore Systems http://unicore.co.ua //// +//// //// +//// Downloaded from: http://www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2006-2010 Unicore Systems LTD //// +//// www.unicore.co.ua //// +//// o.uzenkov@unicore.co.ua //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED "AS IS" //// +//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// +//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// +//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// +//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// +//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// +//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// +//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// +//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// +//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// +//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// +//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// +//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// +//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DESCRIPTION : rotating unit, stays between 2 stages of FFT pipeline +// FUNCTION: complex multiplication to the twiddle factors proper to the 64 point FFT +// for any type FPGAs and ASIC. +// FILES: ROTATOR128_v.v - this file, +// WROM128.v - ROM of twiddle factors. +// PROPERTIES: 1) Has 128-clock cycle period starting with the START impulse +// and continuing forever +// 2) rounding is not used +// 3)intended for synthesizing +// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +`timescale 1ns / 1ps +`include "FFT128_CONFIG.inc" + +module ROTATOR128 (CLK ,RST,ED,START, DR,DI, DOR, DOI,RDY ); + `FFT128paramnb + `FFT128paramnw + + input RST ; + wire RST ; + input CLK ; + wire CLK ; + input ED ; //operation enable + input [nb-1:0] DI; //Imaginary part of data + wire [nb-1:0] DI ; + input [nb-1:0] DR ; //Real part of data + input START ; //1-st Data is entered after this impulse + wire START ; + + output [nb-1:0] DOI ; //Imaginary part of data + wire [nb-1:0] DOI ; + output [nb-1:0] DOR ; //Real part of data + wire [nb-1:0] DOR ; + output RDY ; //repeats START impulse following the output data + reg RDY ; + + + reg [6:0] addrw; + reg sd1,sd2; + always @( posedge CLK) //address counter for twiddle factors + begin + if (RST) begin + addrw<=0; + sd1<=0; + sd2<=0; + end + else if (START && ED) begin + addrw[6:0]<=0; + sd1<=START; + sd2<=0; + end + else if (ED) begin + addrw<=addrw+1; + sd1<=START; + sd2<=sd1; + RDY<=sd2; + end + end + + wire [6:0] addrwi; + assign addrwi={addrw[4 : 0], addrw[6 : 3] }; + wire signed [nw-1:0] wr,wi; //twiddle factor coefficients + //twiddle factor ROM + WROM128 UROM( .ADDR(addrwi), .WR(wr),.WI(wi) ); + + + reg signed [nb-1 : 0] drd,did; + reg signed [nw-1 : 0] wrd,wid; + wire signed [nw+nb-1 : 0] drri,drii,diri,diii; + reg signed [nb:0] drr,dri,dir,dii,dwr,dwi; + + assign drri=drd*wrd; + assign diri=did*wrd; + assign drii=drd*wid; + assign diii=did*wid; + + always @(posedge CLK) //complex multiplier + begin + if (ED) begin + drd<=DR; + did<=DI; + wrd<=wr; + wid<=wi; + drr<=drri[nw+nb-1 :nw-1]; //msbs of multiplications are stored + dri<=drii[nw+nb-1 : nw-1]; + dir<=diri[nw+nb-1 : nw-1]; + dii<=diii[nw+nb-1 : nw-1]; + dwr<=drr - dii; + dwi<=dri + dir; + end + end + assign DOR=dwr[nb:1]; + assign DOI=dwi[nb:1]; + +endmodule

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