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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac/branches/fp
    from Rev 135 to Rev 136
    ↔ Reverse comparison
  •

Rev 135 → Rev 136

/dpc.vhd
29,14 → 29,16
--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
);
port (
clk : in std_logic;
paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
fifo32x26_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
scalar : in std_logic;
sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
93,14 → 95,27
add32blki(i*width+width-1 downto i*width) <= ssumando(i);
resultoutput(i*width+width-1 downto i*width) <= sresult(i);
end generate stuff08;
stuff06:
for i in 05 downto 0 generate
sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
end generate stuff06;
process (clk)
begin
if clk'event and clk='1' then
for i 05 downto 0 loop
sprd32blk(p0) <= prd32blko(i*width+width-1 downto i*width);
end loop;
end if;
end process;
stuff04:
for i in 03 downto 0 generate
for i in 03 downto 1 generate
sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
end generate stuff04;
process (clk)
begin
if clk'event and clk='1' then
sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
sinv32blk <= inv32blko;
end if;
end process;
stuff03:
for i in 02 downto 0 generate
snormfifo_q(i) <= fifo32x26_q(i*width+width-1 downto i*width);
115,10 → 130,9
sinv32blk <= inv32blko;
ssqr32blk <= sqr32blko;
--! Salidas de los distintos resultados;
--! Colas de salida de los distintos resultados;
sresult(0) <= ssqr32blk;
sresult(1) <= sadd32blk(a0);
sresult(2) <= sadd32blk(a1);
133,11 → 147,20
snormfifo_d(qy) <= sparaminput(ay);
snormfifo_d(qz) <= sparaminput(az);
--! Signo de los 3 primeros sumadores
--! La entrada al inversor SIEMPRE viene con la salida de la raiz cuadrada
inv32blki <= sqr32blko;
 
sqr32blki <= sadd32blk(a1);
--! Conectar las entradas del sumador a, a la salida
ssumando(s6) <= sadd32blk(a2);
ssumando(s7) <= sdpfifo_q(dpfifocd);
mul:process(unary,addsub,crossprod,scalar,sparaminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,snormfifo_q)
begin
199,8 → 222,7
end if;
ssumando(s6) <= sadd32blk(a2);
ssumando(s7) <= sdpfifo_q(dpfifocd);
if addsub='1' then
ssumando(s0) <= sparaminput(ax);
ssumando(s1) <= sparaminput(bx);
/memblock.vhd
140,8 → 140,8
 
begin
 
dpfifo : scfifo
generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",9,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
dpfifo : scfifo --! Debe ir registrada la salida.
generic map ("ON","Cyclone III","RAM_BLOCK_TYPE=M9K",15,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
normfifo : scfifo
generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",96,5,"OFF","OFF","ON")

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