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  • This comparison shows the changes necessary to convert path 
    /raytrac/branches/fp
    from Rev 139 to Rev 140
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  •

Rev 139 → Rev 140

/dpc.vhd
29,7 → 29,7
--!external_readable_widthad : integer := integer(ceil(log(real(external_readable_blocks),2.0))))
);
port (
clk,ena : in std_logic;
clk,ena,rst : in std_logic;
paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
43,8 → 43,8
fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 6 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
res567w,res13w,res2w,res0w,res4w,fifo32x09_w,fifo32x23_w,fifo32x09_r,fifo32x23_r: out std_logic;
resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
);
end dpc;
 
80,41 → 80,67
signal sdpfifo_q : vectorblock02;
signal ssqr32blk,sinv32blk : std_logic_vector(width-1 downto 0);
signal sync_chain : std_logic_vector(27 downto 0);
signal sync_chain_d : std_logic;
constant rstMasterValue : std_logic := '0';
begin
--! Cadena de sincronización: 28 posiciones.
sync_chain_proc:
process(clk,rst)
begin
if rst=rstMasterValue then
sync_chain <= (others => '0');
elsif clk'event and clk='1' then
sync_chain(0) <= sync_chain_d;
for i in 27 downto 1 loop
sync_chain(i) <= sync_chain(i-1);
end loop;
end if;
end process sync_chain_proc;
--! Escritura en las colas de resultados y escritura/lectura en las colas intermedias mediante cadena de resultados.
fifo32x09_w <= sync_chain(4);
fifo32x23_w <= sync_chain(0);
fifo32x09_r <= sync_chain();
fifo32x23_r <= sync_chain();
res0w <= sync_chain(22);
res4w <= sync_chain(20);
sync_chain_comb:
process (sync_chain,addsub,crossprod)
begin
if unary='1' then
res567w <= sync_chain(27);
else
res567w <= sync_chain(3);
end if;
if addsub='1' then
res13w <= sync_chain(8);
res2w <= sync_chain(8);
else
res13w <= sync_chain(12);
if crossprod='1' then
res2w <= res13w;
else
res2w <= sync_chain(21);
end if;
end if;
end process sync_chain_comb;
--! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, simplemente son abstracciones a nivel de c&oacute;digo y no representar&aacute; cambios en la s&iacute;ntesis.
stuff12:
for i in 11 downto 0 generate
sparaminput(i) <= paraminput(i*width+width-1 downto i*width);
prd32blki(i*width+width-1 downto i*width) <= sfactor(i);
end generate stuff12;
stuff08:
for i in 07 downto 0 generate
add32blki(i*width+width-1 downto i*width) <= ssumando(i);
resultoutput(i*width+width-1 downto i*width) <= sresult(i);
end generate stuff08;
register_products_outputs:
process (clk,ena)
begin
if clk'event and clk='1' and ena='1' then
for i in 05 downto 0 loop
sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
end loop;
end if;
end process;
register_adder0_and_inversor_output:
process (clk,ena)
begin
if clk'event and clk='1' and ena='1' then
sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
sinv32blk <= inv32blko;
end if;
end process;
stuff04:
for i in 03 downto 1 generate
sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
131,10 → 157,32
for i in 01 downto 0 generate
sdpfifo_q(i) <= fifo32x09_q(i*width+width-1 downto i*width);
end generate stuff02;
--! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, son abstracciones de c&oacute;digo tambi&eacute;n, sin embargo se realizan a trav&eacute;s de registros.
register_products_outputs:
process (clk)
begin
if clk'event and clk='1' then
for i in 05 downto 0 loop
sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
end loop;
end if;
end process;
--! Los productos del multiplicador 2 y 3, ya registrados dentro de dpc van a la cola intermedia del producto punto (fifo32x09_d)
fifo32x09_d <= sprd32blk(p3)&sprd32blk(p2);
register_adder0_and_inversor_output:
process (clk)
begin
if clk'event and clk='1' then
sadd32blk(a0) <= add32blko(a0*width+width-1 downto a0*width);
sinv32blk <= inv32blko;
end if;
end process;
ssqr32blk <= sqr32blko;
--! Colas de salida de los distintos resultados;
/memblock.vhd
128,7 → 128,7
);
end component;
signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1 downto 0);
signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se &ntilde;al extra es para la escritura de la cola de instrucciones.
signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
141,20 → 141,26
 
begin
 
dpfifo : scfifo --! Debe ir registrada la salida.
generic map ("ON",9,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",16,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
--! Cola interna de producto punto, ubicada entre el pipe line aritm&eacute;co.
q0q1 : scfifo --! Debe ir registrada la salida.
generic map ("ON",8,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",16,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
normfifo : scfifo
--! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute
qxqyqz : scfifo
generic map ("ON",23,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",32,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
instrfifo : scfifo
--! Cola de instrucciones
qi : scfifo
generic map ("ON",31,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",32,"OFF","SCIFIFO",32,5,"ON","OFF","ON")
port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrfifo_full);
--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de c&oacute;digo, no influye en la sintesis del circuito.
sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
--! Instanciaci&oacute;n de la cola de resultados.
results_blocks:
for i in 7 downto 0 generate
sint_d(i) <= int_d((i+1)*width-1 downto i*width);
161,11 → 167,9
resultsfifo : scfifo
generic map ("ON",511,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",512,"OFF","SCIFIFO",32,9,"ON","OFF","ON")
port map (s0ext_rd_ack(i),resultfifo_flush,resultfifo_empty(i),clk,s0ext_q(i),resultfifo_wr,sint_d(i),open,resultfifo_full(i));
-- resultsblock : altsyncram
-- generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
-- port map (resultfifo_wr,clk,resultfifo_wr_add,ext_rd_add(widthadmemblock-1 downto 0),ext_rd,s1ext_q(i),sint_d(i));
end generate results_blocks;
--! Instanciaci&oacute;n de la cola de resultados de salida.
operands_blocks:
for i in 11 downto 0 generate
int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
174,7 → 178,7
port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
end generate operands_blocks;
--! Escritura en registros de operandos de entrada.
operands_block_proc: process (clk,ena)
begin
if clk'event and clk='1' and ena='1' then
184,26 → 188,31
s0ext_d <= ext_d;
end if;
end process;
--! Decodificaci&oacute;n de se&ntilde;al escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la direcci&oacute;n de entrada.
operands_block_comb: process (s0ext_wr_add,s0ext_wr)
begin
--! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.
--! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como est&aacute; el pool de direcciones por bloques de vectores.
case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
when x"0" => s0ext_wr_add_one_hot <= x"00"&"000"&s0ext_wr;
when x"1" => s0ext_wr_add_one_hot <= x"00"&"00"&s0ext_wr&'0';
when x"2" => s0ext_wr_add_one_hot <= x"00"&'0'&s0ext_wr&"00";
when x"3" => s0ext_wr_add_one_hot <= x"00"&s0ext_wr&"000";
when x"4" => s0ext_wr_add_one_hot <= x"0"&"000"&s0ext_wr&x"0";
when x"5" => s0ext_wr_add_one_hot <= x"0"&"00"&s0ext_wr&'0'&x"0";
when x"6" => s0ext_wr_add_one_hot <= x"0"&'0'&s0ext_wr&"00"&x"0";
when x"7" => s0ext_wr_add_one_hot <= x"0"&s0ext_wr&"000"&x"0";
when x"8" => s0ext_wr_add_one_hot <= "000"&s0ext_wr&x"00";
when x"9" => s0ext_wr_add_one_hot <= "00"&s0ext_wr&'0'&x"00";
when x"A" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"00"&x"00";
when others => s0ext_wr_add_one_hot <= s0ext_wr&"000"&x"00";
when x"0" => s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
when x"1" => s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
when x"2" => s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
when x"4" => s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
when x"5" => s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
when x"6" => s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
when x"8" => s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
when x"9" => s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
when x"A" => s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
when x"C" => s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
when x"D" => s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
when x"E" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
when others => s0ext_wr_add_one_hot <= '1'&x"000";
end case;
end process;
--! Decodificaci&oacute;n para seleccionar que cola de resultados se conectar&acute; a la salida del RayTrac.
results_block_proc: process(clk,ena)
begin
if clk'event and clk='1' and ena='1' then
223,6 → 232,8
end case;
end if;
end process;
--! rdack decoder para las colas de resultados de salida.
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
begin
case '0'&s0ext_rd_add is

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