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  • This comparison shows the changes necessary to convert path 
    /raytrac/branches/fp_sgdma
    from Rev 246 to Rev 248
    ↔ Reverse comparison
  •

Rev 246 → Rev 248

/ap_n_dpc.vhd
33,7 → 33,7
port (
p0,p1,p2 : out std_logic_vector(31 downto 0);
p0,p1,p2,p3,p4,p5,p6,p7,p8: out std_logic_vector(31 downto 0);
clk : in std_logic;
70,7 → 70,7
 
architecture ap_n_dpc_arch of ap_n_dpc is
--!Constantes de apoyo
constant ssync_chain_max : integer :=27;
constant ssync_chain_max : integer :=32;
constant ssync_chain_min : integer :=2;
--! Tunnning delay
289,12 → 289,19
ssync_chain(ssync_chain_min) <= sync_chain_1;
--! Salida de los multiplicadores p0 p1 p2
if ssync_chain(21)='1' then
p0 <= sa0; -- El resultado quedara consignado en VZ1=BASE+1
elsif ssync_chain(22)='1' then
p1 <= sa0; -- El resutlado quedara consignado en VY1=BASE+2
elsif ssync_chain(23)='1' then
p2 <= sa0; -- El resultado quedara consignado en VX1=BASE+3
if ssync_chain(23)='1' then
p0 <= ssq32; -- El resultado quedara consignado en VZ1=BASE+1
elsif ssync_chain(28)='1' then
p1 <= sq2_q; -- El resultado quedara consignado en VX1=BASE+3
elsif ssync_chain(24)='1' then
p2 <= sinv32; -- El resutlado quedara consignado en VY1=BASE+2
p3 <= sqx_q;
p4 <= sqy_q;
p5 <= sqz_q;
elsif ssync_chain(28)='1' then
p6 <= sp3o;
p7 <= sp4o;
p8 <= sp5o;
end if;
end if;
429,7 → 436,7
sqr_dy <= sp4;
sqr_dz <= sp5;
sqr_w <= ssync_chain(27);
sqr_w <= ssync_chain(27+adder1_delay);
when others =>
504,7 → 511,7
use_eab => "ON"
)
port map (
rdreq => ssync_chain(27),
rdreq => ssync_chain(28),
sclr => '0',
clock => clk,
empty => sq2_e,
529,7 → 536,7
aclr => '0',
clock => clk,
empty => sq1_e,
rdreq => ssync_chain(23),
rdreq => ssync_chain(23+adder1_delay),
wrreq => sync_chain_1,
data => ax,
q => sqx_q
548,7 → 555,7
port map (
aclr => '0',
clock => clk,
rdreq => ssync_chain(23),
rdreq => ssync_chain(23+adder1_delay),
wrreq => sync_chain_1,
data => ay,
q => sqy_q
567,7 → 574,7
port map (
aclr => '0',
clock => clk,
rdreq => ssync_chain(23),
rdreq => ssync_chain(23+adder1_delay),
wrreq => sync_chain_1,
data => az,
q => sqz_q
/raytrac.vhd
200,12 → 200,12
signal sflood_condition : std_logic;
signal sflood_burstcount : std_logic_vector(mb downto 0);
 
signal sp0,sp1,sp2 : std_logic_vector(31 downto 0);
signal sp0,sp1,sp2,sp3,sp4,sp5,sp6,sp7,sp8: std_logic_vector(31 downto 0);
--! Arithmetic Pipeline and Data Path Control
component ap_n_dpc
port (
p0,p1,p2 : out std_logic_vector(31 downto 0);
p0,p1,p2,p3,p4,p5,p6,p7,p8 : out std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
ax : in std_logic_vector(31 downto 0);
221,8 → 221,8
ack : in std_logic;
empty : out std_logic;
dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_1 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
pipeline_pending : out std_logic --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
sync_chain_1 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
pipeline_pending : out std_logic --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
);
end component;
245,6 → 245,13
p0 => sp0,
p1 => sp1,
p2 => sp2,
p3 => sp3,
p4 => sp4,
p5 => sp5,
p6 => sp6,
p7 => sp7,
p8 => sp8,
clk => clk,
rst => rst,
ax => sreg_block(reg_ax),
733,9 → 740,6
sslave_read <= slave_read;
sslave_writedata <= slave_writedata;
sreg_block(reg_vz) <= sp0;
sreg_block(reg_vy) <= sp1;
sreg_block(reg_vx) <= sp2;
for i in reg_scalar downto reg_scalar loop
if sslave_address=i then
if sslave_write='1' then
746,7 → 750,29
for i in 15 downto 0 loop
if sslave_address=i then
if sslave_read='1' then
slave_readdata <= sreg_block(i);
if (i<10 and i>3) or i=0 then
slave_readdata <= sreg_block(i);
elsif i=1 then
slave_readdata <= sp0;
elsif i=2 then
slave_readdata <= sp1;
elsif i=3 then
slave_readdata <= sp2;
elsif i=10 then
slave_readdata <= sp3;
elsif i=11 then
slave_readdata <= sp4;
elsif i=12 then
slave_readdata <= sp5;
elsif i=13 then
slave_readdata <= sp6;
elsif i=14 then
slave_readdata <= sp7;
elsif i=15 then
slave_readdata <= sp8;
end if;
end if;
end if;
end loop;

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