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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac/branches
    from Rev 218 to Rev 219
    ↔ Reverse comparison
  •

Rev 218 → Rev 219

/fp_sgdma/arithblock.vhd
39,8 → 39,8
add32blko : out vectorblock03;
prd32blko : out vectorblock06;
sq32o : xfloat32;
inv32o : xfloat32
sq32o : out xfloat32;
inv32o : out xfloat32
52,12 → 52,48
signal sadd32blko_01 : xfloat32;
signal ssq32o : xfloat32;
--! Componentes Aritméticos
component fadd32
port (
clk : in std_logic;
dpc : in std_logic;
a32 : in xfloat32;
b32 : in xfloat32;
c32 : out xfloat32
);
end component;
component fmul32
port (
clk : in std_logic;
a32 : in xfloat32;
b32 : in xfloat32;
p32 : out xfloat32
);
end component;
--! Bloque de Raiz Cuadrada
component sqrt32
port (
clk : in std_logic;
rd32: in xfloat32;
sq32: out xfloat32
);
end component;
--! Bloque de Inversores.
component invr32
port (
clk : in std_logic;
dvd32 : in xfloat32;
qout32 : out xfloat32
);
end component;
 
 
begin
 
sq32o <= ssq32o;
sadd32blko_01 <= add32blko(1);
add32blko(1) <= sadd32blko_01;
 
--!TBXINSTANCESTART
adder_i_0 : fadd32
75,7 → 111,7
dpc => sign,
a32 => add32blki(2),
b32 => add32blki(3),
c32 => add32blko(1)
c32 => sadd32blko_01
);
--!TBXINSTANCESTART
adder_i_2 : fadd32
/fp_sgdma/fadd32.vhd
78,6 → 78,23
signal s5result : std_logic_vector (25 downto 0);
--!TBXEND
--! LPM_MULTIPLIER
component lpm_mult
generic (
lpm_hint : string;
lpm_pipeline : natural;
lpm_representation : string;
lpm_type : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
result : out std_logic_vector( lpm_widthp-1 downto 0 )
);
end component;
146,7 → 163,7
end process;
--! Etapa 5: Codificar el corrimiento para la normalizacion de la mantissa resultante y entregar el resultado.
c32(31) <= s5result(25);
process (s5result(24 downto 0))
process (s5result(24 downto 0),s5exp)
begin
case s5result(24) is
when '1' =>
/fp_sgdma/raytrac.vhd
1,6 → 1,29
--! @file raytrac.vhd
--! @brief Sistema de Procesamiento Vectorial. La interface es compatible con el bus Avalon de Altera.
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- raytrac.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.arithpack.all;
 
library altera_mf;
use altera_mf.altera_mf_components.all;
12,11 → 35,8
entity raytrac is
generic (
wd : integer := 32;
sl : integer := 5; --! Arith Sync Chain Long 2**sl
ln : integer := 12; --! Max Transfer Length = 2**ln = n_outputbuffers * 256
fd : integer := 8; --! Result Fifo Depth = 2**fd =256
mb : integer := 4; --! Max Burst Length = 2**mb
nr : integer := 4 --! Number of Registers = 2**nr
mb : integer := 4 --! Max Burst Length = 2**mb
);
port (
clk: in std_logic;
59,13 → 79,11
attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
 
subtype xfloat32 is std_logic_vector(wd-1 downto 0);
type registerblock is array ((2**nr)-1 downto 0) of xfloat32;
type registerblock is array (15 downto 0) of xfloat32;
type transferState is (IDLE,SINK,SOURCE);
type upload_chain is (UPVX,UPVY,UPVZ,SC,DMA);
type download_chain is (DWAX,DWAY,DWAZ,DWBX,DWBY,DWBZ,DWAXBX,DWAYBY,DWAZBZ);
constant rstMasterValue : std_logic :='0';
constant reg_ctrl : integer:=00;
constant reg_vz : integer:=01;
constant reg_vy : integer:=02;
114,8 → 132,8
signal sreg_block : registerblock;
signal sslave_read : std_logic;
signal sslave_write : std_logic;
signal sslave_writedata : xfloat32;
signal sslave_address : std_logic_vector (nr-1 downto 0);
signal sslave_writedata : std_logic_vector (wd-1 downto 0);
signal sslave_address : std_logic_vector (3 downto 0);
signal sslave_waitrequest : std_logic;
--! Avalon MM Master
128,9 → 146,9
signal sres_ack : std_logic;
signal soutb_ack : std_logic;
signal sres_q : std_logic_vector(4*wd-1 downto 0);
signal sres_q : std_logic_vector (4*wd-1 downto 0);
signal sres_d : std_logic_vector(4*wd-1 downto 0);
signal sres_d : vectorblock04;
signal soutb_d : std_logic_vector(wd-1 downto 0);
156,7 → 174,6
--!Unload Control
type upload_chain is (VX,VY,VZ,SC,DMA);
signal supload_chain : upload_chain;
signal supload_start : upload_chain;
164,7 → 181,6
signal zero : std_logic_vector(31 downto 0);
--!High Register Bank Control Signals or AKA Load Sync Chain Control
type download_chain is (AX,AY,AZ,BX,BY,BZ,AXBX,AYBY,AZBZ);
signal sdownload_chain : download_chain;
signal sdownload_start : download_chain;
signal srestart_chain : std_logic;
177,32 → 193,66
signal sflood_condition : std_logic;
signal sflood_burstcount : std_logic_vector(mb downto 0);
 
--! Arithmetic Pipeline and Data Path Control
component ap_n_dpc
port (
clk : in std_logic;
rst : in std_logic;
paraminput : in vectorblock06; --! Vectores A,B
d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_1 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
sync_chain_pending : out std_logic;
qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
);
end component;
signal sparaminput : vectorblock06;
begin
 
--! Unos y ceros
--!Zero agreggate
zero <= (others => '0');
--! Salidas no asignadas
sparaminput(ax) <= sreg_block(reg_ax);
sparaminput(ay) <= sreg_block(reg_ay);
sparaminput(az) <= sreg_block(reg_az);
sparaminput(bx) <= sreg_block(reg_bx);
sparaminput(by) <= sreg_block(reg_by);
sparaminput(bz) <= sreg_block(reg_bz);
--! Mientras tanto
ssync_chain_pending <= ssync_chain_1;
sres_d ((wd*1)-1 downto wd*0)<= sreg_block(reg_bz) ;
sres_d ((wd*2)-1 downto wd*1)<= sreg_block(reg_by) ;
sres_d ((wd*3)-1 downto wd*2)<= sreg_block(reg_bx) ;
sres_d ((wd*4)-1 downto wd*3)<= sreg_block(reg_ax) ;
sres_w <= ssync_chain_1;
--! *************************************************************************************************************************************************************************************************************************************************************
--! ARITHMETIC PIPELINE AND DATA PATH INSTANTIATION => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
--! *************************************************************************************************************************************************************************************************************************************************************
--! Arithpipeline and Datapath Control Instance
arithmetic_pipeline_and_datapath_controller : ap_n_dpc
port map (
clk => clk,
rst => rst,
paraminput => sparaminput,
d => sreg_block(reg_ctrl)(reg_ctrl_d),
c => sreg_block(reg_ctrl)(reg_ctrl_c),
s => sreg_block(reg_ctrl)(reg_ctrl_s),
sync_chain_1 => ssync_chain_1,
sync_chain_pending => ssync_chain_pending,
qresult_w => sres_w,
qresult_d => sres_d
);
--! *************************************************************************************************************************************************************************************************************************************************************
--! AVALON MEMORY MAPPED MASTER INTERFACE BEGIN => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
--! *************************************************************************************************************************************************************************************************************************************************************
--! ******************************************************************************************************************************************************
--! TRANSFER CONTROL RTL CODE
--! ******************************************************************************************************************************************************
TRANSFER_CONTROL:
process(clk,rst,master_waitrequest,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,sres_e,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,sres_e,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
begin
--! Conexi&oacuteln a se&ntilde;ales externas.
242,7 → 292,7
end if;
--! ELEMENTO DE SINCRONIZACION CARGA DE OPERANDOS: Se est&aacute;n cargando los operandos que ser&aacute;n operados en el pipeline aritm&eacute;tico.
if sdownload_chain /= AX and sdownload_chain /= AXBX then
if sdownload_chain /= DWAX and sdownload_chain /= DWAXBX then
sparamload_pending <= '1';
else
sparamload_pending <= '0';
449,11 → 499,12
--! Ir al estado Source.
sm <= SOURCE;
sreg_block(reg_ctrl)(reg_ctrl_rom) <= '1';
 
else
sreg_block(reg_ctrl)(reg_ctrl_rom) <= '0';
end if;
end if;
when others =>
null;
end case;
end if;
end process;
464,7 → 515,7
--! ******************************************************************************************************************************************************
res:scfifo
generic map (lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 128, lpm_widthu => fd, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
port map (rdreq => sres_ack, aclr => '0', empty => sres_e, clock => clk, q => sres_q, wrreq => sres_w, data => sres_d);
port map (rdreq => sres_ack, aclr => '0', empty => sres_e, clock => clk, q => sres_q, wrreq => sres_w, data => sres_d(qsc)&sres_d(qx)&sres_d(qy)&sres_d(qz));
output_buffer:scfifo
generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
491,9 → 542,11
--! Control de lectura de la cola de resultados.
if sres_e='0' then
--!Hay datos en la cola de resultados.
if (supload_chain=VZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
if (supload_chain=UPVZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
sres_ack <= '1';
else
sres_ack <= '0';
end if;
else
sres_ack <= '0';
503,14 → 556,14
--! Decodificar que salida de la cola de resultados se conecta a la entrada del otput buffer
--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexi&oacute;n
case supload_chain is
when VX =>
soutb_d <= sres_q ((wd*1)-1 downto wd*0);
when VY =>
soutb_d <= sres_q ((wd*2)-1 downto wd*1);
when VZ =>
soutb_d <= sres_q ((wd*3)-1 downto wd*2);
when UPVX =>
soutb_d <= sres_q (32*qx+31 downto 32*qx);
when UPVY =>
soutb_d <= sres_q (32*qy+31 downto 32*qy);
when UPVZ =>
soutb_d <= sres_q (32*qz+31 downto 32*qz);
when SC =>
soutb_d <= sres_q ((wd*4)-1 downto wd*3);
soutb_d <= sres_q (32*qsc+31 downto 32*qsc);
when DMA =>
soutb_d <= master_readdata;
end case;
520,27 → 573,27
when "01" =>
supload_start <= SC;
when others =>
supload_start <= VX;
supload_start <= UPVX;
end case;
--! M&aacute;quina de estados para el width adaptation RES(128) -> OUTPUTBUFFER(32).
if rst=rstMasterValue then
supload_chain <= VX;
supload_chain <= UPVX;
elsif clk'event and clk='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
--! Modo de operaci&oacute;n normal.
case supload_chain is
when VX =>
when UPVX =>
if sres_e='1' then
supload_chain <= supload_start;
else
supload_chain <= VY;
supload_chain <= UPVY;
end if;
when VY =>
supload_chain <= VZ;
when VZ =>
when UPVY =>
supload_chain <= UPVZ;
when UPVZ =>
if sreg_block(reg_ctrl)(reg_ctrl_sc)='0' then
supload_chain <= VX;
supload_chain <= UPVX;
else
supload_chain <= SC;
end if;
563,14 → 616,14
process(clk,rst,master_readdatavalid,master_readdata,sreg_block(reg_ctrl)(reg_ctrl_dma downto reg_ctrl_s),sslave_write,sslave_address,supload_chain)
begin
--! Est&aacute; ocurriendo un evento de transici&oacute;n del estado TX al estado FETCH: Programar el enganche de par&aacute;metros que vienen de la interconexi&oacute;n.
--! Mirar como es la carga inicial. Si es Normalizacion o Magnitud (dcs=110) entonces cargar AXBX de lo contrario solo AX.
--! Mirar como es la carga inicial. Si es Normalizacion o Magnitud (dcs=110) entonces cargar DWAXBX de lo contrario solo DWAX.
case sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s) is
when "110" | "100" => sdownload_start <= AXBX;
when others => sdownload_start <= AX;
when "110" | "100" => sdownload_start <= DWAXBX;
when others => sdownload_start <= DWAX;
end case;
if rst=rstMasterValue then
ssync_chain_1 <= '0';
sdownload_chain <= AX;
sdownload_chain <= DWAX;
for i in reg_bz downto reg_ax loop
sreg_block(i) <= (others => '0');
end loop;
579,55 → 632,55
if master_readdatavalid='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
--! El dato en la interconexi&oacute;n es valido, se debe enganchar.
case sdownload_chain is
when AX | AXBX =>
when DWAX | DWAXBX =>
--! Cargar el operando correspondiente al componente "X" del vector "A"
ssync_chain_1 <= '0';
sreg_block(reg_ax) <= master_readdata;
if sdownload_start = AXBX then
if sdownload_start = DWAXBX then
--! Operaci&oacute;n Unaria por ejemplo magnitud de un vector
--! Escribir en el registro bx adicionalmente.
sreg_block(reg_bx) <= master_readdata;
--! El siguiente estado es cargar el componente "Y" de del operando a ejecutar.
sdownload_chain <= AYBY;
sdownload_chain <= DWAYBY;
else
--! Operaci&oacute;n de dos operandos. Por ejemplo Producto Cruz.
--! El siguiente estado es cargar el vector "Y" del operando "A".
sdownload_chain <= AY;
sdownload_chain <= DWAY;
end if;
when AY | AYBY =>
when DWAY | DWAYBY =>
sreg_block(reg_ay) <= master_readdata;
ssync_chain_1 <= '0';
if sdownload_chain = AYBY then
if sdownload_chain = DWAYBY then
sreg_block(reg_by) <= master_readdata;
sdownload_chain <= AZBZ;
sdownload_chain <= DWAZBZ;
else
sdownload_chain <= AZ;
sdownload_chain <= DWAZ;
end if;
when AZ | AZBZ =>
when DWAZ | DWAZBZ =>
sreg_block(reg_az) <= master_readdata;
if sdownload_chain=AZBZ then
if sdownload_chain=DWAZBZ then
ssync_chain_1 <= '1';
sreg_block(reg_bz) <= master_readdata;
sdownload_chain <= AXBX;
sdownload_chain <= DWAXBX;
else
ssync_chain_1 <= '0';
sdownload_chain <= BX;
sdownload_chain <= DWBX;
end if;
when BX =>
when DWBX =>
ssync_chain_1 <= '0';
sreg_block(reg_bx) <= master_readdata;
sdownload_chain <= BY;
when BY =>
sdownload_chain <= DWBY;
when DWBY =>
ssync_chain_1 <= '0';
sreg_block(reg_by) <= master_readdata;
sdownload_chain <= BZ;
when BZ =>
sdownload_chain <= DWBZ;
when DWBZ =>
sreg_block(reg_bz) <= master_readdata;
ssync_chain_1 <= '1';
if sreg_block(reg_ctrl)(reg_ctrl_cmb)='1' then
sdownload_chain <= BX;
sdownload_chain <= DWBX;
else
sdownload_chain <= AX;
sdownload_chain <= DWAX;
end if;
when others =>
null;
800,7 → 853,7
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
--! Data Write Start Address (reg_sinkstart) BASE_ADDRESS + 0x24 |
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
--! Parameter Ax component (reg_ax) BASE_ADDRESS + 0x28 |
--! Parameter AX component (reg_ax) BASE_ADDRESS + 0x28 |
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
--! Parameter Ay component (reg_ay) BASE_ADDRESS + 0x2C |
--!---------|-----------|-------------------------------------------------------------------------------------------------------------------|
/fp_sgdma/arithpack.vhd
19,7 → 19,7
package arithpack is
--!Constantes usadas por los RTLs
constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant sc : integer := 03;
constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;constant qsc: integer := 03;
constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
27,19 → 27,7
constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
constant index_control_register : integer := 00;
constant index_start_address_r : integer := 01;
constant index_end_address_r : integer := 02;
constant index_start_address_w : integer := 03;
constant index_end_address_w : integer := 04;
constant index_scratch_register : integer := 05;
--! M&aacute;quina de estados.
--! Control de tama&ntilde;os de memoria.
constant widthadmemblock : integer := 9;
subtype xfloat32 is std_logic_vector(31 downto 0);
type v3f is array(02 downto 0) of xfloat32;
60,273 → 48,8
constant tclk_4 : time := tclk/4;
component raytrac
port (
clk : in std_logic;
rst : in std_logic;
--! Interface Avalon Master
address_master : out std_logic_vector(31 downto 0);
begintransfer : out std_logic;
read_master : out std_logic;
readdata_master : in std_logic_vector (31 downto 0);
write_master : out std_logic;
writedata_master: out std_logic_vector (31 downto 0);
waitrequest : in std_logic_vector;
readdatavalid_m : in std_logic_vector;
--! Interface Avalon Slave
address_slave : in std_logic_vector(3 downto 0);
read_slave : in std_logic;
readdata_slave : in std_logic_vector(31 downto 0);
write_slave : in std_logic;
writedata_slave : in std_logic_vector(31 downto 0);
readdatavalid_s : out std_logic;
--! Interface Interrupt Sender
irq : out std_logic
);
end component;
component raytrac_control
port (
--! Se&ntilde;ales normales de secuencia.
clk: in std_logic;
rst: in std_logic;
--! Interface Avalon Master
begintransfer : out std_logic;
address_master : out std_logic_vector(31 downto 0);
read_master : out std_logic;
write_master : out std_logic;
waitrequest : in std_logic;
readdatavalid_m : in std_logic;
--! Interface Avalon Slave
address_slave : in std_logic_vector(3 downto 0);
read_slave : in std_logic;
readdata_slave : out std_logic_vector(31 downto 0);
write_slave : in std_logic;
writedata_slave : in std_logic_vector(31 downto 0);
readdatavalid_s : out std_logic;
 
--! Interface Interrupt Sender
irq : out std_logic;
--! Se&ntilde;ales de Control (Memblock)
go : out std_logic;
comb : out std_logic;
load : out std_logic;
load_chain : out std_logic_vector(1 downto 0);
qparams_e : in std_logic;
qresult_e : in std_logic_vector(3 downto 0);
--! Se&ntilde;les de Control de Datapath (DPC)
qparams_q : in xfloat32;
d : out std_logic;
c : out std_logic;
s : out std_logic;
qresult_sel : out std_logic_vector(1 downto 0)
);
end component;
--! Bloque de memorias
component memblock
port (
--!Entradas de Control
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
comb : in std_logic;
load : in std_logic;
load_chain : in std_logic_vector(1 downto 0);
--! Cola de par&aacute;metros
readdatavalid : in std_logic;
readdata_master : in xfloat32;
qparams_r : in std_logic;
qparams_e : out std_logic;
--! Cola de resultados
qresult_d : in vectorblock04;
qresult_q : out vectorblock04;
--! Registro de par&aacute;metros
paraminput : out vectorblock06;
--! Cadena de sincronización
sync_chain_0 : out std_logic;
--! se&ntilde;ales de colas vacias
qresult_e : out std_logic_vector(3 downto 0);
--! Colas de resultados
qresult_w : in std_logic_vector(3 downto 0);
qresult_rdec : in std_logic_vector(3 downto 0)
);
end component;
--! Bloque decodificacion DataPath Control.
component dpc
port (
clk : in std_logic;
rst : in std_logic;
paraminput : in vectorblock06; --! Vectores A,B
prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.
add32blko : in vectorblock03; --! Salidas de los 3 sumadores.
inv32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
sqr32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_0 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
qresult_q : in vectorblock04; --! Salida de las colas de resultados
qresult_sel : in std_logic_vector (1 downto 0); --! Direccion con el resultado de la
qresult_rdec : out std_logic_vector (3 downto 0); --!Se&ntilde;ales de escritura decodificadas
qresult_w : out std_logic_vector (3 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
qresult_d : out vectorblock04; --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
dataread : in std_logic;
 
prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicaci&oacute;n respectivamente.
add32blki : out vectorblock06; --! Entrada de los 6 sumandos del bloque de 3 sumadores.
dataout : out xfloat32
);
end component;
--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
component arithblock
port (
clk : in std_logic;
rst : in std_logic;
sign : in std_logic;
prd32blki : in vectorblock12;
add32blki : in vectorblock06;
add32blko : out vectorblock03;
prd32blko : out vectorblock06;
sq32o : out xfloat32;
inv32o : out xfloat32
);
end component;
--! Componentes Aritm&eacute;ticos
component fadd32
port (
clk : in std_logic;
dpc : in std_logic;
a32 : in xfloat32;
b32 : in xfloat32;
c32 : out xfloat32
);
end component;
component fmul32
port (
clk : in std_logic;
a32 : in xfloat32;
b32 : in xfloat32;
p32 : out xfloat32
);
end component;
--! Bloque de Raiz Cuadrada
component sqrt32
port (
clk : in std_logic;
rd32: in xfloat32;
sq32: out xfloat32
);
end component;
--! Bloque de Inversores.
component invr32
port (
clk : in std_logic;
dvd32 : in xfloat32;
qout32 : out xfloat32
);
end component;
--! Contadores para la m&aacute;quina de estados.
component customCounter
port (
clk : in std_logic;
rst : in std_logic;
stateTrans : in std_logic;
waitrequest_n : in std_logic;
endaddress : in std_logic_vector (31 downto 2); --! Los 5 bits de arriba.
startaddress : in std_logic_vector(31 downto 0);
endaddressfetch : out std_logic;
address_master : out std_logic_vector (31 downto 0)
);
end component;
--! LPM_MULTIPLIER
component lpm_mult
generic (
lpm_hint : string;
lpm_pipeline : natural;
lpm_representation : string;
lpm_type : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
result : out std_logic_vector( lpm_widthp-1 downto 0 )
);
end component;
--! LPM Memory Compiler.
-- component scfifo
-- generic (
-- add_ram_output_register :string;
-- allow_rwcycle_when_full :string;
-- intended_device_family :string;
-- lpm_hint :string;
-- lpm_numwords :natural;
-- lpm_showahead :string;
-- lpm_type :string;
-- lpm_width :natural;
-- overflow_checking :string;
-- underflow_checking :string;
-- use_eab :string
-- );
-- port(
-- rdreq : in std_logic;
-- aclr : in std_logic;
-- empty : out std_logic;
-- clock : in std_logic;
-- q : out std_logic_vector(lpm_width-1 downto 0);
-- wrreq : in std_logic;
-- data : in std_logic_vector(lpm_width-1 downto 0);
-- almost_full : out std_logic;
-- full : out std_logic
-- );
-- end component;
type apCamera is record
resx,resy : integer;
width,height : real;
/fp_sgdma/dpc.vhd
1,10 → 1,10
--! @file dpc.vhd
--! @file ap_n_dpc.vhd
--! @brief Decodificador de operaci&eacute;n. Sistema de decodificación de los \kdatapaths, cuyo objetivo es a partir del par&acute;ametro de entrada DCS.\nSon 4 las posibles configuraciones de \kdatapaths que existen. Los valores de los bits DC son los que determinan y decodifican la interconexi&oacute;n entre los componentes aritm&eacute;ticos. El componente S determina el signo de la operaci&oacute;n cuando es una suma la que operaci&oacute;n se es&eacutea; ejecutando en el momento.
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- dpc.vhd
-- ap_n_dpc.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
29,7 → 29,7
use altera_mf.altera_mf_components.all;
 
 
entity dpc is
entity ap_n_dpc is
port (
clk : in std_logic;
37,28 → 37,20
paraminput : in vectorblock06; --! Vectores A,B
prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.
add32blko : in vectorblock03; --! Salidas de los 3 sumadores.
inv32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
sqr32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.
d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
sync_chain_1 : in std_logic; --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
sync_chain_pendant : out std_logic; --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
sync_chain_pending : out std_logic; --! Se&ntilde;al para indicar si hay datos en el pipeline aritm&eacute;tico.
qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
qresult_d : out vectorblock04; --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
 
prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicaci&oacute;n respectivamente.
add32blki : out vectorblock06 --! Entrada de los 6 sumandos del bloque de 3 sumadores.
 
 
);
end entity;
 
architecture dpc_arch of dpc is
architecture ap_n_dpc_arch of ap_n_dpc is
--!TBXSTART:FACTORS_N_ADDENDS
signal sfactor : vectorblock12;
88,13 → 80,57
signal sq1_q : std_logic_vector(31 downto 0);
signal sq1_w : std_logic;
signal sq1_e : std_logic;
 
 
signal sadd32blko : vectorblock03; --! Salidas de los 3 sumadores.
signal sprd32blko : vectorblock06; --! Salidas de los 6 multiplicadores.
 
signal sinv32blko : xfloat32; --! Salidas de la raiz cuadradas y el inversor.
signal ssqr32blko : xfloat32; --! Salidas de la raiz cuadradas y el inversor.
--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
component arithblock
port (
clk : in std_logic;
rst : in std_logic;
sign : in std_logic;
prd32blki : in vectorblock12;
add32blki : in vectorblock06;
add32blko : out vectorblock03;
prd32blko : out vectorblock06;
sq32o : out xfloat32;
inv32o : out xfloat32
);
end component;
begin
 
--! Bloque Aritm&eacute;tico
ap : arithblock
port map (
clk => clk,
rst => rst,
sign => s,
prd32blki => sfactor,
add32blki => ssumando,
add32blko => sadd32blko,
prd32blko => sprd32blko,
sq32o => ssqr32blko,
inv32o => sinv32blko
);
--! Cadena de sincronizaci&oacute;n: 29 posiciones.
sync_chain_pendant <= sync_chain_1 or sq1_e or sqxyz_e;
sync_chain_pending <= sync_chain_1 or not(sq1_e) or not(sqxyz_e);
sync_chain_proc:
process(clk,rst,sync_chain_1)
begin
118,8 → 154,6
--! El siguiente c&oacute;digo sirve para conectar arreglos a se&ntilde;ales std_logic_1164, simplemente son abstracciones a nivel de c&oacute;digo y no representar&aacute; cambios en la s&iacute;ntesis.
prd32blki <= sfactor;
add32blki <= ssumando;
qresult_d <= sresult;
130,11 → 164,11
process (clk)
begin
if clk'event and clk='1' then
sprd32blk <= prd32blko;
sadd32blk <= add32blko;
sinv32blk <= inv32blko;
sprd32blk <= sprd32blko;
sadd32blk <= sadd32blko;
sinv32blk <= sinv32blko;
--! Raiz Cuadrada.
ssqr32blk <= sqr32blko;
ssqr32blk <= ssqr32blko;
end if;
end process;
221,12 → 255,12
end if;
--res3
sresult(sc) <= sq1_q;
if c='1' then
sresult(qsc) <= sq1_q;
if c='1' then
sq1_d <= ssqr32blk;
sq1_w <= ssync_chain(20);
sq1_w <= ssync_chain(20) and d;
else
sq1_w <= ssync_chain(19);
sq1_w <= ssync_chain(19) and d;
sq1_d <= sadd32blk(a1);
end if;
262,7 → 296,6
port map (
sclr => '0',
clock => clk,
empty => sq1_e,
rdreq => ssync_chain(12),
wrreq => ssync_chain(5),
data => sprd32blk(p2),
285,6 → 318,7
rdreq => ssync_chain(25),
sclr => '0',
clock => clk,
empty => sq1_e,
q => sq1_q,
wrreq => sq1_w,
data => sq1_d
/fp_sgdma/fmul32.vhd
57,6 → 57,26
signal s1ac,s1umu:std_logic_vector(35 downto 0);
signal s2umu:std_logic_vector(24 downto 0);
signal sxprop : std_logic_vector(2 downto 0);
--! LPM_MULTIPLIER
component lpm_mult
generic (
lpm_hint : string;
lpm_pipeline : natural;
lpm_representation : string;
lpm_type : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
result : out std_logic_vector( lpm_widthp-1 downto 0 )
);
end component;
begin

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