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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk
    from Rev 49 to Rev 50
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  •

Rev 49 → Rev 50

/tb.vhd
54,7 → 54,7
 
--! Device Under Test
dude: raytrac
generic map ("YES") -- Entrada registrada, pues la ROM no tiene salida registrada.
generic map ("YES","YES") -- Test bench y Entrada registrada, pues la ROM no tiene salida registrada.
port map(qa,qb,qc,qd,opcode,addcode,clock,rst,ena,cpx,cpy,cpz,dp0,dp1);
--! Procedimiento para escribir los resultados del testbench
74,8 → 74,34
write (buff,now,unit =>ns);
write (buff,string'(" "));
hexwrite_0 (buff,address(7 downto 0));
write (buff,string'(" {"));
hexwrite_0 (buff,qa(17 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,qa(17 downto 0));
hexwrite_0 (buff,qa(35 downto 18));
write (buff,string'(" "));
hexwrite_0 (buff,qa(53 downto 36));
write (buff,string'("} "));
write (buff,string'(" {"));
hexwrite_0 (buff,qb(17 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,qb(35 downto 18));
write (buff,string'(" "));
hexwrite_0 (buff,qb(53 downto 36));
write (buff,string'("} "));
write (buff,string'(" {"));
hexwrite_0 (buff,qc(17 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,qc(35 downto 18));
write (buff,string'(" "));
hexwrite_0 (buff,qc(53 downto 36));
write (buff,string'("} "));
write (buff,string'(" {"));
hexwrite_0 (buff,qd(17 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,qd(35 downto 18));
write (buff,string'(" "));
hexwrite_0 (buff,qd(53 downto 36));
write (buff,string'("} "));
writeline(rombuff,buff);
wait for tclk;
end loop displayRom;
83,6 → 109,7
end process sampleproc;
--! Descripcion del test: 512 x (2/clock) productos punto y 1024 x (1/clock) productos cruz.
thetest:
process (clock,rst)
162,7 → 189,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
187,7 → 214,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
212,7 → 239,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
237,7 → 264,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
262,7 → 289,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
312,7 → 339,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
337,7 → 364,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
362,7 → 389,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
387,7 → 414,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
412,7 → 439,7
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "M9K",
widthad_a => 9,
width_a => 18,
/raytrac.vhd
85,7 → 85,7
 
entity raytrac is
generic (
testbench_generation : string := "NO";
registered : string := "NO" --! Este parametro, por defecto "YES", indica si se registran o cargan en registros los vectores A,B,C,D y los codigos de operacion opcode y addcode en vez de ser conectados directamente al circuito combinatorio. \n This parameter, by default "YES", indicates if vectors A,B,C,D and operation code inputs opcode are to be loaded into a register at the beginning of the pipe rather than just connecting them to the operations decoder (opcoder).
);
port (
166,6 → 166,7
--! Instantiate Opcoder
opcdr : opcoder
port map (
SA(17 downto 0),SB(17 downto 0),SC(17 downto 0),SD(17 downto 0),SA(35 downto 18),SB(35 downto 18),SC(35 downto 18),SD(35 downto 18),SA(53 downto 36),SB(53 downto 36),SC(53 downto 36),SD(53 downto 36),
smf00,smf01,smf10,smf11,smf20,smf21,smf30,smf31,smf40,smf41,smf50,smf51,
173,7 → 174,7
);
--! Instantiate uf, cross product and dot product functional unit.
uf0 : uf
generic map ("YES","RCA")
generic map ("YES",testbench_generation,"RCA")
port map (
sopcode,
smf00,smf01,smf10,smf11,smf20,smf21,smf30,smf31,smf40,smf41,smf50,smf51,
/arithpack.vhd
68,7 → 68,7
--! Ray Trac: Implementacion del Rt Engine
component raytrac
generic (
testbench_generation : string := "NO";
registered : string := "NO" --! Este parametro, por defecto "YES", indica si se registran o cargan en registros los vectores A,B,C,D y los codigos de operacion opcode y addcode en vez de ser conectados directamente al circuito combinatorio. \n This parameter, by default "YES", indicates if vectors A,B,C,D and operation code inputs opcode are to be loaded into a register at the beginning of the pipe rather than just connecting them to the operations decoder (opcoder).
);
port (
110,6 → 110,7
component uf
generic (
use_std_logic_signed : string := "NO";
testbench_generation : string := "NO";
carry_logic : string := "CLA"
);
port (
144,24 → 145,31
c: out std_logic_vector(width-1 downto 0)
);
end component;
 
component r_a18_b18_smul_c32_r
component lpm_mult
generic (
lpm_hint : string := "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
lpm_pipeline : natural:= 2;
lpm_representation : string:="SIGNED";
lpm_type : string:="LPM_MULT";
lpm_widtha : natural:=18;
lpm_widthb : natural:=18;
lpm_widthp : natural:=32
lpm_hint : string;
lpm_pipeline : natural;
lpm_representation : string;
lpm_type : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
aclr,clock:in std_logic;
dataa,datab:in std_logic_vector (17 downto 0);
result: out std_logic_vector(31 downto 0)
aclr : in std_logic ;
clock : in std_logic ;
datab : in std_logic_vector (17 downto 0);
dataa : in std_logic_vector (17 downto 0);
result : out std_logic_vector (31 downto 0)
);
end component;
 
 
component cla_logic_block
generic ( width: integer:=4);
207,16 → 215,18
constant hexchars : string (1 to 16) := "0123456789ABCDEF";
procedure hexwrite_0(l:inout line;h:in std_logic_vector) is
variable index_high,index_low,acc : integer;
variable index_high,index_low,highone : integer;
begin
for i in (h'high)/4 downto 0 loop
highone := h'high-h'low;
for i in (highone)/4 downto 0 loop
index_low:=i*4;
if (index_low+3)>h'high then
index_high := h'high;
if (index_low+3)>highone then
index_high := highone;
else
index_high := i*4+3;
end if;
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high downto index_low))));
write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high+h'low downto index_low+h'low))));
end loop;
end procedure;
end package body arithpack;
/uf.vhd
27,6 → 27,9
 
use ieee.std_logic_signed.all;
 
--! Paquete estandar de texto
use std.textio.all;
 
--! Se usaran en esta descripcion los componentes del package arithpack.vhd.\n It will be used in this description the components on the arithpack.vhd package.
use work.arithpack.all;
 
42,6 → 45,7
entity uf is
generic (
use_std_logic_signed : string := "NO";
testbench_generation : string := "NO";
carry_logic : string := "CLA"
);
port (
79,7 → 83,16
 
-- Multiplicator Instantiation (StAgE 0)
--! Multiplicador 0
m0 : r_a18_b18_smul_c32_r
m0 : lpm_mult
generic map (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_pipeline => 2,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 32
)
port map (
aclr => rst,
clock => clk,
89,7 → 102,16
);
--! Multiplicador 1
m1 : r_a18_b18_smul_c32_r
m1 : lpm_mult
generic map (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_pipeline => 2,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 32
)
port map (
aclr => rst,
clock => clk,
99,7 → 121,16
);
--! Multiplicador 2
m2 : r_a18_b18_smul_c32_r
m2 : lpm_mult
generic map (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_pipeline => 2,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 32
)
port map (
aclr => rst,
clock => clk,
109,7 → 140,16
);
--! Multiplicador 3
m3 : r_a18_b18_smul_c32_r
m3 : lpm_mult
generic map (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_pipeline => 2,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 32
)
port map (
aclr => rst,
clock => clk,
119,7 → 159,16
);
--! Multiplicador 4
m4 : r_a18_b18_smul_c32_r
m4 : lpm_mult
generic map (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_pipeline => 2,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 32
)
port map (
aclr => rst,
clock => clk,
129,7 → 178,16
);
--! Multiplicador 5
m5 : r_a18_b18_smul_c32_r
m5 : lpm_mult
generic map (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
lpm_pipeline => 2,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 32
)
port map (
aclr => rst,
clock => clk,
277,6 → 335,112
end if;
end process uf_seq;
--! Codigo generado para realizar test bench
tbgen:
if testbench_generation="YES" generate
tbproc0:
process
variable buff : line;
file mbuff : text open write_mode is "TRACE_multiplier_content";
begin
write(buff,string'("UF multipliers test benching"));
writeline(mbuff, buff);
wait for 5 ns;
wait until rst=not(rstMasterValue);
wait until clk='1';
wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
displayRom:
loop
write (buff,now,unit =>ns);
write (buff,string'(" "));
hexwrite_0 (buff,stage1p0(31 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,stage1p1(31 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,stage1p2(31 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,stage1p1(31 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,stage1p4(31 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,stage1p5(31 downto 0));
writeline(mbuff,buff);
wait for tclk;
end loop displayRom;
end process tbproc0;
tbproc1:
process
variable buff : line;
file fbuff : text open write_mode is "TRACE_decoded_factors_content";
begin
write(buff,string'("UF factors decoded test benching"));
writeline(fbuff, buff);
wait for 5 ns;
wait until rst=not(rstMasterValue);
wait until clk='1';
wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
displayRom:
loop
write (buff,now,unit =>ns);
write (buff,string'(" {"));
hexwrite_0 (buff,m0f0(17 downto 0));
hexwrite_0 (buff,m0f1(17 downto 0));
write (buff,string'("} {"));
hexwrite_0 (buff,m1f0(17 downto 0));
hexwrite_0 (buff,m1f1(17 downto 0));
write (buff,string'("} {"));
hexwrite_0 (buff,m2f0(17 downto 0));
hexwrite_0 (buff,m2f1(17 downto 0));
write (buff,string'("} {"));
hexwrite_0 (buff,m3f0(17 downto 0));
hexwrite_0 (buff,m3f1(17 downto 0));
write (buff,string'("} {"));
hexwrite_0 (buff,m4f0(17 downto 0));
hexwrite_0 (buff,m4f1(17 downto 0));
write (buff,string'("} {"));
hexwrite_0 (buff,m5f0(17 downto 0));
hexwrite_0 (buff,m5f1(17 downto 0));
write (buff,string'("}"));
writeline(fbuff,buff);
wait for tclk;
end loop displayRom;
end process tbproc1;
tbproc2:
process
variable buff : line;
file rbuff : text open write_mode is "TRACE_results_content";
begin
write(buff,string'("UF results test benching"));
writeline(rbuff, buff);
wait for 5 ns;
wait until rst=not(rstMasterValue);
wait until clk='1';
wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
displayRom:
loop
write (buff,now,unit =>ns);
write (buff,string'(" {"));
hexwrite_0 (buff,stage1a0(31 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,stage1a1(31 downto 0));
write (buff,string'(" "));
hexwrite_0 (buff,stage1a2(31 downto 0));
write (buff,string'("} {dp0: "));
hexwrite_0 (buff,stage2a3(31 downto 0));
write (buff,string'(",dp1: "));
hexwrite_0 (buff,stage2a4(31 downto 0));
write (buff,string'("}"));
writeline(rbuff,buff);
wait for tclk;
end loop displayRom;
end process tbproc2;
 
end generate tbgen;
end uf_arch;

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