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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac/trunk
    from Rev 58 to Rev 59
    ↔ Reverse comparison
  •

Rev 58 → Rev 59

/arithpack.vhd
164,11 → 164,11
lpm_widthp : natural
);
port (
aclr : in std_logic ;
clock : in std_logic ;
datab : in std_logic_vector (17 downto 0);
dataa : in std_logic_vector (17 downto 0);
result : out std_logic_vector (31 downto 0)
aclr : in std_logic ;
clock : in std_logic ;
datab : in std_logic_vector (17 downto 0);
dataa : in std_logic_vector (17 downto 0);
result : out std_logic_vector (31 downto 0)
);
end component;
 
210,9 → 210,37
);
end component;
--! Entidad raiz cuadrada para enteros de 32 bits. no worries 'jhonny g' aint no thy recepie!.
--! No es una entidad de aproximaci´on, posee: etapa de decodificaci&acute e imparidad;on de direcciones,
--! etapa de calculo de la raiz cuadrada mediante memoria, etapa:
component sqrt
port (
clk,rst : in std_logic; -- señales de control.
r : in std_logic_vector (31 downto 0); --radicando
s : out std_logic_vector (15 downto 0)
);
end component;
--! Procedimiento para escribir std_logic_vectors en formato hexadecimal.
procedure hexwrite_0(l:inout line; h: in std_logic_vector);
component shifter is
generic (
address_width : integer := 9;
width : integer := 12
);
port (
data : in std_logic_vector(width - 1 downto 0);
address : out std_logic_vector (address_width-1 downto 0);
zero : out std_logic;
maxoneispair : out std_logic
);
end component;
 
end package;
 
--! Funciones utilitarias, relacionadas sobre todo con el testbench
/shift.vhd
0,0 → 1,85
------------------------------------------------
--! @file shift.vhd
--! @brief RayTrac TestBench
--! @author Julián Andrés Guarín Reyes
--------------------------------------------------
 
 
-- RAYTRAC
-- Author Julian Andres Guarin
-- shift.vhd
-- This file is part of raytrac.
--
-- raytrac is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- raytrac is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
 
 
entity shifter is
generic (
address_width : integer := 9;
width : integer := 32
);
port (
data : in std_logic_vector(width - 1 downto 0);
address : out std_logic_vector (address_width-1 downto 0);
zero : out std_logic;
maxoneispair : out std_logic
);
end shifter;
 
architecture shifter_arch of shifter is
signal datamask : std_logic_vector(width+address_width-1 downto 0);
begin
datamask (width+address_width-1 downto address_width) <= data(width-1 downto 0);
datamask (address_width-1 downto 0) <= (others=>'0');
sanityLost:
process (datamask)
variable index: integer range 0 to width+address_width-1:=width+address_width-1;
begin
address<=(others=>'0');
maxoneispair<='0';
sanityWon:
for index in width+address_width-1 downto address_width loop
if datamask(index)='1' then
if (index-address_width) rem 2 = 0 then
maxoneispair<='1';
end if;
address(address_width-1 downto 0) <= datamask(index-1 downto index-address_width);
exit;
end if;
end loop sanityWon;
end process sanityLost;
process (data)
begin
if data=0 then
zero<='1';
else
zero<='0';
end if;
end process;
end shifter_arch;
 
 
 
 
 
/opcoder.vhd
35,7 → 35,7
entity opcoder is
generic (
width : integer := 18;
structuralDescription : string:= "YES"
structuralDescription : string:= "NO"
);
port (
Ax,Bx,Cx,Dx,Ay,By,Cy,Dy,Az,Bz,Cz,Dz : in std_logic_vector (width-1 downto 0);

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