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Rev 83 → Rev 84

/fpbranch/ema2.vhd
0,0 → 1,82
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
 
entity ema2 is
port (
clk : in std_logic;
a32,b32 : in std_logic_vector (31 downto 0);
exp : out std_logic_vector (7 downto 0);
sma,smb : out std_logic_vector (24 downto 0)
);
end ema2;
 
architecture ema2_arch of ema2 is
signal sa,sb,ssa,ssb,sssa,sssb,s4a : std_logic_vector(31 downto 0);
signal s4umb : std_logic_vector(23 downto 0);
signal s4sma,s4smb : std_logic_vector(24 downto 0);
signal s4sgb : std_logic;
begin
 
process (clk)
begin
if clk'event and clk='1' then
--!Registro de entrada
sa <= a32;
sb <= b32;
 
--!Primera etapa a vs. b
if sa(30 downto 23) >= sb (30 downto 23) then
--!signo,exponente,mantissa
ssb(31) <= sb(31);
ssb(30 downto 23) <= sa(30 downto 23)-sb(30 downto 23);
ssb(22 downto 0) <= sb(22 downto 0);
--!clasifica a
ssa <= sa;
else
--!signo,exponente,mantissa
ssb(31) <= sa(31);
ssb(30 downto 23) <= sb(30 downto 23)-sa(30 downto 23);
ssb(22 downto 0) <= sa(22 downto 0);
--!clasifica b
ssa <= sb;
end if;
--! Tercera etapa corrimiento y normalizaci&oacute;n de mantissas
s4a <= ssa;
s4sgb <= ssb(31);
s4umb <= shr('1'&ssb(22 downto 0),ssb(30 downto 23));
--! Cuarta etapa signar la mantissa y entregar el exponente.
sma <= s4sma + s4a(31);
smb <= s4smb + s4sgb;
exp <= s4a(30 downto 23);
end if;
end process;
--! Combinatorial Gremlin
--!Signar b y c
signbc:
for i in 23 downto 0 generate
s4smb(i) <= s4sgb xor s4umb(i);
end generate;
s4smb(24) <= s4sgb;
--!Signar a
signa:
for i in 22 downto 0 generate
s4sma(i) <= s4a(31) xor s4a(i);
end generate;
s4sma(23) <= not(s4a(31));
s4sma(24) <= s4a(31);
end ema2_arch;
 
/fpbranch/ema3.vhd
0,0 → 1,110
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
 
entity ema3 is
port (
clk : in std_logic;
a32,b32,c32 : in std_logic_vector (31 downto 0);
exp : out std_logic_vector (7 downto 0);
sma,smb,smc : out std_logic_vector (24 downto 0)
);
end ema3;
 
architecture ema3_arch of ema3 is
signal sa,sb,sc,ssa,ssb,ssc,sssa,sssb,sssc,s4a : std_logic_vector(31 downto 0);
signal s4umb,s4umc : std_logic_vector(23 downto 0);
signal s4sma,s4smb,s4smc : std_logic_vector(24 downto 0);
signal s4sgb,s4sgc : std_logic;
begin
 
process (clk)
begin
if clk'event and clk='1' then
--!Registro de entrada
sa <= a32;
sb <= b32;
sc <= c32;
 
--!Primera etapa a vs. b
if sa(30 downto 23) >= sb (30 downto 23) then
--!signo,exponente,mantissa
ssb(31) <= sb(31);
ssb(30 downto 23) <= sb(30 downto 23);
ssb(22 downto 0) <= sb(22 downto 0);
--!clasifica a
ssa <= sa;
else
--!signo,exponente,mantissa
ssb(31) <= sa(31);
ssb(30 downto 23) <= sa(30 downto 23);
ssb(22 downto 0) <= sa(22 downto 0);
--!clasifica b
ssa <= sb;
end if;
ssc <= sc;
--!Segunda Etapa, ganador de a/b vs c, resta de exponentes para saber cuanto se debe correr.
if ssa(30 downto 23) >= ssc (30 downto 23) then
--!signo,exponente,mantissa
sssc(31) <= ssc(31);
sssc(30 downto 23) <= ssa(30 downto 23)-ssc(30 downto 23);
sssb(30 downto 23) <= ssa(30 downto 23)-ssb(30 downto 23);
sssc(22 downto 0) <= ssc(22 downto 0);
--!clasifica ganador de ab
sssa <= ssa;
else
--!signo,exponente,mantissa
sssc(31) <= ssa(31);
sssc(30 downto 23) <= ssc(30 downto 23)-ssa(30 downto 23);
sssb(30 downto 23) <= ssc(30 downto 23)-ssb(30 downto 23);
sssc(22 downto 0) <= ssa(22 downto 0);
--!clasifica c
sssa <= ssc;
end if;
sssb(31) <= ssb(31);
sssb(22 downto 0) <= ssb(22 downto 0);
--! Tercera etapa corrimiento y normalizaci&oacute;n de mantissas
s4a <= sssa;
s4sgb <= sssb(31);
s4sgc <= sssc(31);
s4umb <= shr('1'&sssb(22 downto 0),sssb(30 downto 23));
s4umc <= shr('1'&sssc(22 downto 0),sssc(30 downto 23));
--! Cuarta etapa signar la mantissa y entregar el exponente.
sma <= s4sma + s4a(31);
smb <= s4smb + s4sgb;
smc <= s4smc + s4sgc;
exp <= s4a(30 downto 23);
end if;
end process;
--! Combinatorial Gremlin
--!Signar b y c
signbc:
for i in 23 downto 0 generate
s4smb(i) <= s4sgb xor s4umb(i);
s4smc(i) <= s4sgc xor s4umc(i);
end generate;
s4smb(24) <= s4sgb;
s4smc(24) <= s4sgc;
--!Signar a
signa:
for i in 22 downto 0 generate
s4sma(i) <= s4a(31) xor s4a(i);
end generate;
s4sma(23) <= not(s4a(31));
s4sma(24) <= s4a(31);
end ema3_arch;
 
/fpbranch/add2.vhd
0,0 → 1,127
--! Operar la mantissa y normalizar a ieee 754, float32
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
 
entity add2 is
port (
clk,dpc : in std_logic;
exp : in std_logic_vector(7 downto 0);
sma,smb : in std_logic_vector (24 downto 0);
res32 : out std_logic_vector(31 downto 0)
);
end add2;
 
architecture add2_arch of add2 is
signal s0exp,s1exp,s2exp,s2expnrmr,s2expnrml,s3expnrmr,s3expnrml,s3exp : std_logic_vector(7 downto 0);
signal s0sma,s0smb,s1res,s2res,s2resnrmr,s2resnrml : std_logic_vector(25 downto 0);
signal s3resnrml,s3resnrmr,s3smant,s3umant : std_logic_vector(22 downto 0);
signal s3sign,s1rsl,s2rsl,s3rsl : std_logic;
signal s1rshift,s2rshift : std_logic_vector(1 downto 0);
signal s1lshift,s2lshift : std_logic_vector(4 downto 0);
begin
--! formato ieee 754
res32(31) <= s3sign;
res32(30 downto 23) <= s3exp;
res32(22 downto 0) <= s3umant+s3sign;
process (clk)
begin
if clk'event and clk='1' then
--! etapa de registro de entradas
s0sma(24 downto 0) <= sma;
s0smb(24 downto 0) <= smb;
s0exp <= exp;
--! etapa 0 suma
if dpc='0' then
s1res <= s0sma+s0smb;
else
s1res <= s0sma-s0smb;
end if;
s1exp <= s0exp;
--! etapa 1 codficar el corrimeinto
s2exp <= s1exp;
s2rshift <= s1rshift;
s2lshift <= s1lshift;
s2rsl <= s1rsl;
s2res <= s1res;
--! etapa 2 normalizar la mantissa y el exponente
s3sign <= s2res(25);
s3rsl <= s2rsl;
s3resnrmr <= s2resnrmr(22 downto 0);
s3resnrml <= s2resnrml(22 downto 0);
s3expnrml <= s2expnrml;
s3expnrmr <= s2expnrmr;
end if;
end process;
s0sma(25) <= s0sma(24);
s0smb(25) <= s0smb(24);
process (s1res(25 downto 23))
begin
s1rsl <= (s1res(25) xor s1res(24)) or (s1res(25) xor s1res(23));
end process;
process (s1res)
variable rshift : integer range 1 downto 0;
variable lshift : integer range 23 downto 1;
begin
lshift:=1;
for i in 1 downto 0 loop
rshift:=i;
exit when (s1res(25) xor s1res(23+i))='1';
end loop;
for i in 22 downto 0 loop
exit when (s1res(25) xor s1res(i))='1';
lshift:=lshift+1;
end loop;
s1rshift <= conv_std_logic_vector(rshift,2);
s1lshift <= conv_std_logic_vector(lshift,5);
end process;
process(s2exp,s2res,s2rshift,s2lshift)
begin
s2resnrmr <= shr(s2res,s2rshift);
s2resnrml <= shl(s2res,s2lshift);
s2expnrml <= s2exp-s2lshift;
s2expnrmr <= s2exp+s2rshift;
end process;
process (s3rsl,s3resnrmr,s3resnrml,s3expnrmr,s3expnrml,s3sign,s3smant)
begin
if s3rsl='1' then
s3smant <= s3resnrmr;
s3exp <= s3expnrmr;
else
s3smant <= s3resnrml;
s3exp <= s3expnrml;
end if;
end process;
umantissa:
for i in 22 downto 0 generate
s3umant(i) <= s3sign xor s3smant(i);
end generate;
end add2_arch;
/fpbranch/add3.vhd
0,0 → 1,129
--! Operar la mantissa y normalizar a ieee 754, float32
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
 
entity add3 is
port (
clk,dpc : in std_logic;
exp : in std_logic_vector(7 downto 0);
sma,smb,smc : in std_logic_vector (24 downto 0);
res32 : out std_logic_vector(31 downto 0)
);
end add3;
 
architecture add3_arch of add3 is
signal s0exp,s1exp,s2exp,s2expnrmr,s2expnrml,s3expnrmr,s3expnrml,s3exp : std_logic_vector(7 downto 0);
signal s0sma,s0smb,s0smc,s1res,s2res,s2resnrmr,s2resnrml : std_logic_vector(26 downto 0);
signal s3resnrml,s3resnrmr,s3smant,s3umant : std_logic_vector(22 downto 0);
signal s3sign,s1rsl,s2rsl,s3rsl : std_logic;
signal s1rshift,s2rshift : std_logic_vector(1 downto 0);
signal s1lshift,s2lshift : std_logic_vector(4 downto 0);
begin
--! formato ieee 754
res32(31) <= s3sign;
res32(30 downto 23) <= s3exp;
res32(22 downto 0) <= s3umant+s3sign;
process (clk)
begin
if clk'event and clk='1' then
--! etapa de registro de entradas
s0sma(24 downto 0) <= sma;
s0smb(24 downto 0) <= smb;
s0smc(24 downto 0) <= smc;
s0exp <= exp;
--! etapa 0 suma
if dpc='0' then
s1res <= s0sma+s0smb+s0smc;
else
s1res <= s0sma-s0smb;
end if;
s1exp <= s0exp;
--! etapa 1 codficar el corrimeinto
s2exp <= s1exp;
s2rshift <= s1rshift;
s2lshift <= s1lshift;
s2rsl <= s1rsl;
s2res <= s1res;
--! etapa 2 normalizar la mantissa y el exponente
s3sign <= s2res(26);
s3rsl <= s2rsl;
s3resnrmr <= s2resnrmr(22 downto 0);
s3resnrml <= s2resnrml(22 downto 0);
s3expnrml <= s2expnrml;
s3expnrmr <= s2expnrmr;
end if;
end process;
s0sma(26 downto 25) <= s0sma(24)&s0sma(24);
s0smb(26 downto 25) <= s0smb(24)&s0smb(24);
s0smc(26 downto 25) <= s0smc(24)&s0smc(24);
process (s1res(26 downto 23))
begin
s1rsl <= (s1res(26) xor s1res(25)) or (s1res(26) xor s1res(24)) or (s1res(26) xor s1res(23));
end process;
process (s1res)
variable rshift : integer range 2 downto 0;
variable lshift : integer range 23 downto 1;
begin
lshift:=1;
for i in 2 downto 0 loop
rshift:=i;
exit when (s1res(26) xor s1res(23+i))='1';
end loop;
for i in 22 downto 0 loop
exit when (s1res(26) xor s1res(i))='1';
lshift:=lshift+1;
end loop;
s1rshift <= conv_std_logic_vector(rshift,2);
s1lshift <= conv_std_logic_vector(lshift,5);
end process;
process(s2exp,s2res,s2rshift,s2lshift)
begin
s2resnrmr <= shr(s2res,s2rshift);
s2resnrml <= shl(s2res,s2lshift);
s2expnrml <= s2exp-s2lshift;
s2expnrmr <= s2exp+s2rshift;
end process;
process (s3rsl,s3resnrmr,s3resnrml,s3expnrmr,s3expnrml,s3sign,s3smant)
begin
if s3rsl='1' then
s3smant <= s3resnrmr;
s3exp <= s3expnrmr;
else
s3smant <= s3resnrml;
s3exp <= s3expnrml;
end if;
end process;
umantissa:
for i in 22 downto 0 generate
s3umant(i) <= s3sign xor s3smant(i);
end generate;
end add3_arch;

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