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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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  • This comparison shows the changes necessary to convert path 
    /raytrac
    from Rev 153 to Rev 152
    ↔ Reverse comparison
  •

Rev 153 → Rev 152

/branches/fp/sm.vhd
163,7 → 163,7
generic map(
EOBFLAG => "NO",
ZEROFLAG => "YES",
BACKWARDS => "YES",
BACWARDS => "YES",
EQUALFLAG => "NO",
width => 5,
subwidth => 0
/branches/fp/arithblock.vhd
111,49 → 111,55
mul_i_0 : fmul32
port map (
clk => clk,
a32 => f( 31 downto 0),
b32 => f( 63 downto 32),
p32 => p( 31 downto 0)
dpc => dpc,
a32 => a( 95 downto 64),
b32 => a( 127 downto 96),
c32 => s( 63 downto 32)
);
--!TBXINSTANCESTART
mul_i_1 : fmul32
port map (
clk => clk,
a32 => f( 95 downto 64),
b32 => f( 127 downto 96),
p32 => p( 63 downto 32)
dpc => dpc,
a32 => a( 159 downto 128),
b32 => a( 191 downto 160),
c32 => s( 95 downto 64)
);
--!TBXINSTANCESTART
mul_i_2 : fmul32
port map (
clk => clk,
a32 => f( 159 downto 128),
b32 => f( 191 downto 160),
p32 => p( 95 downto 64)
dpc => dpc,
a32 => a( 223 downto 192),
b32 => a( 255 downto 224),
c32 => s( 127 downto 96)
);
--!TBXINSTANCESTART
mul_i_3 : fmul32
port map (
clk => clk,
a32 => f( 223 downto 192),
b32 => f( 255 downto 224),
p32 => p( 127 downto 96)
dpc => dpc,
a32 => a( 95 downto 64),
b32 => a( 127 downto 96),
c32 => s( 63 downto 32)
);
--!TBXINSTANCESTART
mul_i_4 : fmul32
port map (
clk => clk,
a32 => f( 287 downto 256),
b32 => f( 319 downto 288),
p32 => p( 159 downto 128)
dpc => dpc,
a32 => a( 159 downto 128),
b32 => a( 191 downto 160),
c32 => s( 95 downto 64)
);
--!TBXINSTANCESTART
mul_i_5 : fmul32
port map (
clk => clk,
a32 => f( 351 downto 320),
b32 => f( 383 downto 352),
p32 => p( 191 downto 160)
dpc => dpc,
a32 => a( 223 downto 192),
b32 => a( 255 downto 224),
c32 => s( 127 downto 96)
);
/branches/fp/fadd32.vhd
36,7 → 36,7
a32,b32 : in std_logic_vector (31 downto 0);
c32 : out std_logic_vector(31 downto 0)
);
end entity;
end fadd32;
architecture fadd32_arch of fadd32 is
component lpm_mult
256,6 → 256,6
end architecture;
end fadd32_arch;
 
/branches/fp/invr32.vhd
34,7 → 34,7
dvd32 : in std_logic_vector(31 downto 0);
qout32 : out std_logic_vector(31 downto 0)
);
end entity;
end invr32;
architecture invr32_arch of invr32 is
 
component altsyncram
125,4 → 125,4
end process;
qout32(6 downto 0) <= (others => '0');
 
end architecture;
end invr32_arch;
/branches/fp/arithpack.vhd
1,11 → 1,6
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
 
library std;
use std.textio.all;
 
--! Memory Compiler Library
library lpm;
use lpm.all;
30,10 → 25,7
type vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);
type vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
type v3f is array(02 downto 0) of std_logic_vector(31 downto 0);
--! Constante de reseteo
constant rstMasterValue : std_logic :='0';
--! Constantes periodicas.
309,120 → 301,5
qout32 : out std_logic_vector(31 downto 0)
);
end component;
type apCamera is record
resx,resy : integer;
width,height : real;
dist : real;
end record;
--! Funci&oacute;n que convierte un std_logic_vector en un numero entero
function ap_slv2int(sl:std_logic_vector) return integer;
--! Funci&oacute;n que convierte un n&uacute;mero flotante IEE754 single float, en un n&uacute;mero std_logic_vector.
function ap_fp2slv (f:real) return std_logic_vector;
--! Funci&oacute;n que convierte un n&uacute;mero std_logic_vector en un ieee754 single float.
function ap_slv2fp (sl:std_logic_vector) return real;
--! Funci&oacute;n que devuelve un vector en punto flotante IEEE754 a trav&eacute;s de un
function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;
end package;
 
 
package body arithpack is
 
function ap_slv2int (sl:std_logic_vector) return integer is
alias s : std_logic_vector (sl'high downto sl'low) is sl;
variable i : integer;
begin
i:=0;
for index in s'high downto s'low loop
if s(index)='1' then
i:=i*2+1;
else
i:=i*2;
end if;
end loop;
return i;
end function;
function ap_fp2slv (f:real) return std_logic_vector is
variable faux : real;
variable sef : std_logic_vector (31 downto 0);
begin
--! Signo
if (f<0.0) then
sef(31) := '1';
else
sef(31) := '0';
end if;
--! Exponente
sef(30 downto 23) := conv_std_logic_vector(integer(floor(log(f,2.0))),8);
--! Fraction
faux :=f/floor(log(f,2.0));
faux := faux - 1.0;
sef(22 downto 0) := conv_std_logic_vector(integer(faux),23);
return sef;
end function;
 
function ap_slv2fp(sl:std_logic_vector) return real is
variable expo,frc:integer;
alias s: std_logic_vector(31 downto 0) is sl;
variable f: real;
begin
expo:=ap_slv2int(s(30 downto 23)) - 127;
expo:=2**expo;
frc:=ap_slv2int('1'&s(22 downto 0));
f:=real(frc)*(2.0**(-23.0));
f:=f*real(expo);
if s(31)='1' then
return -f;
else
return f;
end if;
end function;
 
function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f is
variable dx,dy : real;
variable v : v3f;
begin
dx := cam.width/real(cam.resx);
dy := cam.height/real(cam.resy);
--! Eje X: Tomando el dedo &iacute;ndice de la mano derecha, este eje queda apuntando en la direcci&on en la que mira la c&aacute;mara u observador siempre.
v(0):=ap_fp2slv(cam.dist);
--! Eje Y: Tomando el dedo coraz&oacute;n de la mano derecha, este eje queda apuntando a la izquierda del observador, desde el observador.
v(1):=ap_fp2slv(dx*real(cam.resx)*0.5-dx*0.5);
--! Eje Z: Tomando el dedo pulgar de la mano derecha, este eje queda apuntando hacia arriba del observador, desde el observador.
v(2):=ap_fp2slv(dy*real(cam.resy)*0.5-dy*0.5);
return v;
end function;
 
end package body;
/branches/fp/dpc.vhd
51,7 → 51,7
resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operaci&oacute;n que est&aacute; en curso.
resultoutput : out std_logic_vector ((08*floatwidth)-1 downto 0) --! 8 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
);
end entity;
end dpc;
 
architecture dpc_arch of dpc is
348,4 → 348,4
end architecture;
end dpc_arch;
/branches/fp/fmul32.vhd
33,7 → 33,7
p32 : out std_logic_vector(31 downto 0)
);
end entity;
end fmul32;
architecture fmul32_arch of fmul32 is
 
148,4 → 148,4
end architecture;
end fmul32_arch;
/branches/fp/memblock.vhd
48,7 → 48,7
int_d : in std_logic_vector(external_readable_blocks*floatwidth-1 downto 0);
--!Python
ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
ext_q,instr fifo_q : out std_logic_vector(floatwidth-1 downto 0);
int_q : out std_logic_vector(external_writeable_blocks*floatwidth-1 downto 0);
int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
56,7 → 56,7
dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
);
end entity;
end memblock;
 
architecture memblock_arch of memblock is
 
332,5 → 332,5
when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
end case;
end process;
end architecture;
end memblock_arch;
 
/branches/fp/customCounter.vhd
150,11 → 150,8
begin
case set is
--! Si subwidth es cero, p.ej. cuando se quiere hacer un contador simple y no detectar el final de bloques de 4 bits de ancho, el compilador ignora el statement con la expresi&oacute;n por fuera del rango.
when '1' =>
scount_d(subwidth-1 downto 0) <= (others => '0');
scount_d(width-1 downto subwidth) <= setValue;
when others =>
scount_d <= scount_q+sgo;
when '1' => scount_d(subwidth-1 downto 0) <= (others => '0');scount_d(width-1 downto subwidth) <= setValue;
when others => scount_d <= scount_q+sgo;
end case;
end process;
/branches/fp/sqrt32.vhd
34,7 → 34,7
rd32: in std_logic_vector(31 downto 0);
sq32: out std_logic_vector(31 downto 0)
);
end entity;
end sqrt32;
architecture sqrt32_arch of sqrt32 is
 
component altsyncram
111,4 → 111,4
)
port map (rden_a => '1', clock0 => clk, address_a => rd32(23 downto 14), q_a => s0q);
 
end architecture;
end sqrt32_arch;

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