OpenCores
URL https://opencores.org/ocsvn/robust_axi2apb/robust_axi2apb/trunk

Subversion Repositories robust_axi2apb

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    from Rev 7 to Rev 8
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Rev 7 → Rev 8

/robust_axi2apb/trunk/run/run.bat
1,6 → 1,4
 
echo off
 
..\..\..\robust.exe ../src/base/axi2apb.v -od out -I ../src/gen -list list.txt -listpath -header
 
echo Completed RobustVerilog axi2apb run - results in run/out/
..\..\..\robust.exe ../src/base/axi2apb.v -od out -I ../src/gen -list list.txt -listpath -header -gui
/robust_axi2apb/trunk/run/run.sh
1,5 → 1,3
#!/bin/bash
 
../../../robust ../src/base/axi2apb.v -od out -I ../src/gen -list list.txt -listpath -header ${@}
 
echo Completed RobustVerilog axi2apb run - results in run/out/
../../../robust ../src/base/axi2apb.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
/robust_axi2apb/trunk/src/base/axi2apb_rd.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_rd.v
OUTFILE PREFIX_rd.v
 
module PREFIX_axi2apb_rd (PORTS);
module PREFIX_rd (PORTS);
 
input clk;
input reset;
/robust_axi2apb/trunk/src/base/axi2apb_wr.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_wr.v
OUTFILE PREFIX_wr.v
 
module PREFIX_axi2apb_wr (PORTS);
module PREFIX_wr (PORTS);
 
input clk;
input reset;
/robust_axi2apb/trunk/src/base/def_axi2apb.txt
31,21 → 31,21
 
SWAP #FFD #1 ## flip-flop delay
 
SWAP PREFIX soc ## prefix for all modules and file names
SWAP.USER PREFIX axi2apb ## Prefix for all modules and file names
 
SWAP SLAVE_NUM 8 ## number of APB slaves
SWAP.USER SLAVE_NUM 8 ## Number of APB slaves
 
SWAP CMD_DEPTH 2 ## number of AXI command FIFO
SWAP.USER CMD_DEPTH 2 ## Number of AXI command FIFO
 
SWAP ADDR_BITS 24 ## AXI and APB address bits
SWAP ID_BITS 4 ## AXI ID bits
SWAP DEC_BITS 8 ## Address MSBits for slave decoding
SWAP.USER ADDR_BITS 24 ## AXI and APB address bits
SWAP.USER ID_BITS 4 ## AXI ID bits
SWAP.USER DEC_BITS 8 ## Address MSBits for slave decoding
 
SWAP DEC_ADDR0 DEC_BITS'h00 ## Slave 0 address deciding
SWAP DEC_ADDR1 DEC_BITS'h01 ## Slave 1 address deciding
SWAP DEC_ADDR2 DEC_BITS'h02 ## Slave 2 address deciding
SWAP DEC_ADDR3 DEC_BITS'h03 ## Slave 3 address deciding
SWAP DEC_ADDR4 DEC_BITS'h10 ## Slave 4 address deciding
SWAP DEC_ADDR5 DEC_BITS'h11 ## Slave 5 address deciding
SWAP DEC_ADDR6 DEC_BITS'h12 ## Slave 6 address deciding
SWAP DEC_ADDR7 DEC_BITS'h13 ## Slave 7 address deciding
SWAP.USER DEC_ADDR0 'h00 ## Slave 0 address deciding
SWAP.USER DEC_ADDR1 'h01 ## Slave 1 address deciding
SWAP.USER DEC_ADDR2 'h02 ## Slave 2 address deciding
SWAP.USER DEC_ADDR3 'h03 ## Slave 3 address deciding
SWAP.USER DEC_ADDR4 'h10 ## Slave 4 address deciding
SWAP.USER DEC_ADDR5 'h11 ## Slave 5 address deciding
SWAP.USER DEC_ADDR6 'h12 ## Slave 6 address deciding
SWAP.USER DEC_ADDR7 'h13 ## Slave 7 address deciding
/robust_axi2apb/trunk/src/base/axi2apb_mux.v
28,10 → 28,10
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_mux.v
OUTFILE PREFIX_mux.v
 
ITER SX
module PREFIX_axi2apb_mux (PORTS);
module PREFIX_mux (PORTS);
 
 
input clk;
68,7 → 68,7
always @(*)
begin
casex (cmd_addr[ADDR_MSB:ADDR_LSB])
DEC_ADDRSX : slave_num = SLV_BITS'dSX;
DEC_BITSDEC_ADDRSX : slave_num = SLV_BITS'dSX;
default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error
endcase
/robust_axi2apb/trunk/src/base/def_axi2apb_static.txt
27,6 → 27,8
//// ////
//////////////////////////////////////////////////////////////////##>
 
SWAP MODEL_NAME AXI2APB bridge
 
SWAP SLV_BITS LOG2(EXPR(SLAVE_NUM+1)) ##one more for decerr slave
 
LOOP SX SLAVE_NUM
/robust_axi2apb/trunk/src/base/axi2apb.v
28,10 → 28,10
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb.v
OUTFILE PREFIX.v
 
ITER SX
module PREFIX_axi2apb (PORTS);
module PREFIX (PORTS);
 
input clk;
input reset;
73,7 → 73,7
 
CREATE axi2apb_cmd.v
PREFIX_axi2apb_cmd PREFIX_axi2apb_cmd(
PREFIX_cmd PREFIX_cmd(
.clk(clk),
.reset(reset),
.AWGROUP_APB_AXI_A(AWGROUP_APB_AXI_A),
89,7 → 89,7
 
CREATE axi2apb_rd.v
PREFIX_axi2apb_rd PREFIX_axi2apb_rd(
PREFIX_rd PREFIX_rd(
.clk(clk),
.reset(reset),
.GROUP_APB3(GROUP_APB3),
101,7 → 101,7
);
CREATE axi2apb_wr.v
PREFIX_axi2apb_wr PREFIX_axi2apb_wr(
PREFIX_wr PREFIX_wr(
.clk(clk),
.reset(reset),
.GROUP_APB3(GROUP_APB3),
116,7 → 116,7
 
CREATE axi2apb_ctrl.v
PREFIX_axi2apb_ctrl PREFIX_axi2apb_ctrl(
PREFIX_ctrl PREFIX_ctrl(
.clk(clk),
.reset(reset),
.finish_wr(finish_wr),
133,7 → 133,7
IFDEF TRUE(SLAVE_NUM>1)
CREATE axi2apb_mux.v
PREFIX_axi2apb_mux PREFIX_axi2apb_mux(
PREFIX_mux PREFIX_mux(
.clk(clk),
.reset(reset),
.cmd_addr(cmd_addr),
/robust_axi2apb/trunk/src/base/axi2apb_cmd.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_cmd.v
OUTFILE PREFIX_cmd.v
 
module PREFIX_axi2apb_cmd (PORTS);
module PREFIX_cmd (PORTS);
 
input clk;
input reset;
/robust_axi2apb/trunk/src/base/axi2apb_ctrl.v
28,9 → 28,9
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_ctrl.v
OUTFILE PREFIX_ctrl.v
 
module PREFIX_axi2apb_ctrl (PORTS);
module PREFIX_ctrl (PORTS);
 
 
input clk;

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