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URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

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  • This comparison shows the changes necessary to convert path 
    /soc_maker/trunk/core_lib/cores/wb_connect
    from Rev 5 to Rev 7
    ↔ Reverse comparison
  •

Rev 5 → Rev 7

/wb_connect.yaml
8,11 → 8,39
authormail: lampret@opencores.org
toplevel: minsoc_tc_top
interfaces:
 
 
:clk: SOCM_IFC
name: clk
dir: 1
version: "1"
ports:
:wb_clk_i: SOCM_PORT
len: 1
defn: clk
:rst: SOCM_IFC
name: rst
dir: 1
version: "1"
ports:
:wb_rst_i: SOCM_PORT
len: 1
defn: rst
 
 
 
:i0: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i0_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i0_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i0_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
24,7 → 52,7
len: 32
:i0_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i0_wb_we_i: SOCM_PORT
defn: we
len: 1
42,9 → 70,15
len: 1
:i1: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i1_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i1_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i1_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
56,7 → 90,7
len: 32
:i1_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i1_wb_we_i: SOCM_PORT
defn: we
len: 1
74,9 → 108,15
len: 1
:i2: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i2_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i2_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i2_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
88,7 → 128,7
len: 32
:i2_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i2_wb_we_i: SOCM_PORT
defn: we
len: 1
106,9 → 146,15
len: 1
:i3: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i3_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i3_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i3_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
120,7 → 166,7
len: 32
:i3_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i3_wb_we_i: SOCM_PORT
defn: we
len: 1
138,9 → 184,15
len: 1
:i4: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i4_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i4_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i4_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
152,7 → 204,7
len: 32
:i4_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i4_wb_we_i: SOCM_PORT
defn: we
len: 1
170,9 → 222,15
len: 1
:i5: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i5_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i5_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i5_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
184,7 → 242,7
len: 32
:i5_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i5_wb_we_i: SOCM_PORT
defn: we
len: 1
202,9 → 260,15
len: 1
:i6: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i6_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i6_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i6_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
216,7 → 280,7
len: 32
:i6_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i6_wb_we_i: SOCM_PORT
defn: we
len: 1
234,9 → 298,15
len: 1
:i7: SOCM_IFC
name: wishbone_ma
dir: 1
dir: 0
version: "b3"
ports:
:i7_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:i7_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:i7_wb_cyc_i: SOCM_PORT
defn: cyc
len: 1
248,7 → 318,7
len: 32
:i7_wb_sel_i: SOCM_PORT
defn: sel
len: 1
len: 4
:i7_wb_we_i: SOCM_PORT
defn: we
len: 1
266,9 → 336,15
len: 1
:t0: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t0_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t0_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t0_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
280,12 → 356,12
len: 32
:t0_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t0_wb_we_o: SOCM_PORT
defn: we
len: 1
:t0_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t0_wb_dat_i: SOCM_PORT
defn: dat_i
298,9 → 374,15
len: 1
:t1: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t1_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t1_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t1_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
312,12 → 394,12
len: 32
:t1_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t1_wb_we_o: SOCM_PORT
defn: we
len: 1
:t1_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t1_wb_dat_i: SOCM_PORT
defn: dat_i
330,9 → 412,15
len: 1
:t2: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t2_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t2_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t2_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
344,12 → 432,12
len: 32
:t2_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t2_wb_we_o: SOCM_PORT
defn: we
len: 1
:t2_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t2_wb_dat_i: SOCM_PORT
defn: dat_i
362,9 → 450,15
len: 1
:t3: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t3_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t3_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t3_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
376,12 → 470,12
len: 32
:t3_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t3_wb_we_o: SOCM_PORT
defn: we
len: 1
:t3_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t3_wb_dat_i: SOCM_PORT
defn: dat_i
394,9 → 488,15
len: 1
:t4: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t4_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t4_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t4_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
408,12 → 508,12
len: 32
:t4_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t4_wb_we_o: SOCM_PORT
defn: we
len: 1
:t4_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t4_wb_dat_i: SOCM_PORT
defn: dat_i
426,9 → 526,15
len: 1
:t5: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t5_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t5_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t5_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
440,12 → 546,12
len: 32
:t5_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t5_wb_we_o: SOCM_PORT
defn: we
len: 1
:t5_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t5_wb_dat_i: SOCM_PORT
defn: dat_i
458,9 → 564,15
len: 1
:t6: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t6_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t6_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t6_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
472,12 → 584,12
len: 32
:t6_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t6_wb_we_o: SOCM_PORT
defn: we
len: 1
:t6_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t6_wb_dat_i: SOCM_PORT
defn: dat_i
490,9 → 602,15
len: 1
:t7: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t7_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t7_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t7_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
504,12 → 622,12
len: 32
:t7_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t7_wb_we_o: SOCM_PORT
defn: we
len: 1
:t7_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t7_wb_dat_i: SOCM_PORT
defn: dat_i
522,9 → 640,15
len: 1
:t8: SOCM_IFC
name: wishbone_sl
dir: 1
dir: 0
version: "b3"
ports:
:t8_wb_clk_o: SOCM_PORT
defn: clk
len: 1
:t8_wb_rst_o: SOCM_PORT
defn: rst
len: 1
:t8_wb_cyc_o: SOCM_PORT
defn: cyc
len: 1
536,12 → 660,12
len: 32
:t8_wb_sel_o: SOCM_PORT
defn: sel
len: 1
len: 4
:t8_wb_we_o: SOCM_PORT
defn: we
len: 1
:t8_wb_dat_o: SOCM_PORT
defn: dat_i
defn: dat_o
len: 32
:t8_wb_dat_i: SOCM_PORT
defn: dat_i
/minsoc_tc_top.v
98,6 → 98,8
wb_clk_i,
wb_rst_i,
 
i0_wb_clk_o,
i0_wb_rst_o,
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_adr_i,
108,6 → 110,8
i0_wb_ack_o,
i0_wb_err_o,
 
i1_wb_clk_o,
i1_wb_rst_o,
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_adr_i,
118,6 → 122,8
i1_wb_ack_o,
i1_wb_err_o,
 
i2_wb_clk_o,
i2_wb_rst_o,
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_adr_i,
128,6 → 134,8
i2_wb_ack_o,
i2_wb_err_o,
 
i3_wb_clk_o,
i3_wb_rst_o,
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_adr_i,
138,6 → 146,8
i3_wb_ack_o,
i3_wb_err_o,
 
i4_wb_clk_o,
i4_wb_rst_o,
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_adr_i,
148,6 → 158,8
i4_wb_ack_o,
i4_wb_err_o,
 
i5_wb_clk_o,
i5_wb_rst_o,
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_adr_i,
158,6 → 170,8
i5_wb_ack_o,
i5_wb_err_o,
 
i6_wb_clk_o,
i6_wb_rst_o,
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_adr_i,
168,6 → 182,8
i6_wb_ack_o,
i6_wb_err_o,
 
i7_wb_clk_o,
i7_wb_rst_o,
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_adr_i,
178,6 → 194,8
i7_wb_ack_o,
i7_wb_err_o,
 
t0_wb_clk_o,
t0_wb_rst_o,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_adr_o,
188,6 → 206,8
t0_wb_ack_i,
t0_wb_err_i,
 
t1_wb_clk_o,
t1_wb_rst_o,
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_adr_o,
198,6 → 218,8
t1_wb_ack_i,
t1_wb_err_i,
 
t2_wb_clk_o,
t2_wb_rst_o,
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_adr_o,
208,6 → 230,8
t2_wb_ack_i,
t2_wb_err_i,
 
t3_wb_clk_o,
t3_wb_rst_o,
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_adr_o,
218,6 → 242,8
t3_wb_ack_i,
t3_wb_err_i,
 
t4_wb_clk_o,
t4_wb_rst_o,
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_adr_o,
228,6 → 254,8
t4_wb_ack_i,
t4_wb_err_i,
 
t5_wb_clk_o,
t5_wb_rst_o,
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_adr_o,
238,6 → 266,8
t5_wb_ack_i,
t5_wb_err_i,
 
t6_wb_clk_o,
t6_wb_rst_o,
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_adr_o,
248,6 → 278,8
t6_wb_ack_i,
t6_wb_err_i,
 
t7_wb_clk_o,
t7_wb_rst_o,
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_adr_o,
258,6 → 290,8
t7_wb_ack_i,
t7_wb_err_i,
 
t8_wb_clk_o,
t8_wb_rst_o,
t8_wb_cyc_o,
t8_wb_stb_o,
t8_wb_adr_o,
515,6 → 549,49
input t8_wb_ack_i;
input t8_wb_err_i;
 
 
output i0_wb_clk_o;
output i0_wb_rst_o;
output i1_wb_clk_o;
output i1_wb_rst_o;
output i2_wb_clk_o;
output i2_wb_rst_o;
output i3_wb_clk_o;
output i3_wb_rst_o;
output i4_wb_clk_o;
output i4_wb_rst_o;
output i5_wb_clk_o;
output i5_wb_rst_o;
output i6_wb_clk_o;
output i6_wb_rst_o;
output i7_wb_clk_o;
output i7_wb_rst_o;
output t0_wb_clk_o;
output t0_wb_rst_o;
output t1_wb_clk_o;
output t1_wb_rst_o;
output t2_wb_clk_o;
output t2_wb_rst_o;
output t3_wb_clk_o;
output t3_wb_rst_o;
output t4_wb_clk_o;
output t4_wb_rst_o;
output t5_wb_clk_o;
output t5_wb_rst_o;
output t6_wb_clk_o;
output t6_wb_rst_o;
output t7_wb_clk_o;
output t7_wb_rst_o;
output t8_wb_clk_o;
output t8_wb_rst_o;
 
 
 
 
 
 
 
 
//
// Internal wires & registers
//
585,7 → 662,48
wire z_wb_ack_t;
wire z_wb_err_t;
 
 
//
// Assign clock and resets
//
assign i0_wb_clk_o = wb_clk_i;
assign i0_wb_rst_o = wb_rst_i;
assign i1_wb_clk_o = wb_clk_i;
assign i1_wb_rst_o = wb_rst_i;
assign i2_wb_clk_o = wb_clk_i;
assign i2_wb_rst_o = wb_rst_i;
assign i3_wb_clk_o = wb_clk_i;
assign i3_wb_rst_o = wb_rst_i;
assign i4_wb_clk_o = wb_clk_i;
assign i4_wb_rst_o = wb_rst_i;
assign i5_wb_clk_o = wb_clk_i;
assign i5_wb_rst_o = wb_rst_i;
assign i6_wb_clk_o = wb_clk_i;
assign i6_wb_rst_o = wb_rst_i;
assign i7_wb_clk_o = wb_clk_i;
assign i7_wb_rst_o = wb_rst_i;
assign t0_wb_clk_o = wb_clk_i;
assign t0_wb_rst_o = wb_rst_i;
assign t1_wb_clk_o = wb_clk_i;
assign t1_wb_rst_o = wb_rst_i;
assign t2_wb_clk_o = wb_clk_i;
assign t2_wb_rst_o = wb_rst_i;
assign t3_wb_clk_o = wb_clk_i;
assign t3_wb_rst_o = wb_rst_i;
assign t4_wb_clk_o = wb_clk_i;
assign t4_wb_rst_o = wb_rst_i;
assign t5_wb_clk_o = wb_clk_i;
assign t5_wb_rst_o = wb_rst_i;
assign t6_wb_clk_o = wb_clk_i;
assign t6_wb_rst_o = wb_rst_i;
assign t7_wb_clk_o = wb_clk_i;
assign t7_wb_rst_o = wb_rst_i;
assign t8_wb_clk_o = wb_clk_i;
assign t8_wb_rst_o = wb_rst_i;
 
 
 
//
// Outputs for initiators are ORed from both mi_to_st blocks
//
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;

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