URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk/altera_work/spw_fifo_ulight/hps_isw_handoff/ulight_fifo_hps_0
- from Rev 32 to Rev 40
- ↔ Reverse comparison
Rev 32 → Rev 40
/emif.xml
88,7 → 88,7
<define name="RDIMM" value="0"/> |
<define name="READ_AFTER_WRITE_CALIBRATION" value="1"/> |
<define name="READ_VALID_FIFO_SIZE" value="16"/> |
<define name="REG_FILE_INIT_SEQ_SIGNATURE" value="0x555504aa"/> |
<define name="REG_FILE_INIT_SEQ_SIGNATURE" value="0x555504ab"/> |
<define name="RLDRAM3" value="0"/> |
<define name="RLDRAMII" value="0"/> |
<define name="RLDRAMX" value="0"/> |
/hps.xml
3,7 → 3,7
<config name='DEVICE_FAMILY' value='Cyclone V' /> |
<config name='DMA_Enable' value='No No No No No No No No' /> |
<config name='dbctrl_stayosc1' value='true' /> |
<config name='main_pll_m' value='73' /> |
<config name='main_pll_m' value='36' /> |
<config name='main_pll_n' value='0' /> |
<config name='main_pll_c0_internal' value='1' /> |
<config name='main_pll_c1_internal' value='4' /> |
13,7 → 13,7
<config name='main_pll_c5' value='18' /> |
<config name='l4_mp_clk_div' value='0' /> |
<config name='l4_sp_clk_div' value='0' /> |
<config name='periph_pll_m' value='39' /> |
<config name='periph_pll_m' value='19' /> |
<config name='periph_pll_n' value='0' /> |
<config name='periph_pll_c0' value='511' /> |
<config name='periph_pll_c1' value='511' /> |
28,8 → 28,8
<config name='gpio_db_clk_div' value='16777215' /> |
<config name='main_pll_vco_hz' value='1850000000' /> |
<config name='periph_pll_vco_hz' value='1000000000' /> |
<config name='eosc1_clk_hz' value='25000000' /> |
<config name='eosc2_clk_hz' value='25000000' /> |
<config name='eosc1_clk_hz' value='50000000' /> |
<config name='eosc2_clk_hz' value='50000000' /> |
<config name='F2SCLK_PERIPHCLK_FREQ' value='0' /> |
<config name='F2SCLK_SDRAMCLK_FREQ' value='0' /> |
<config name='l3_mp_clk_div' value='1' /> |
/id
1,3 → 1,3
Do not change the content of this file |
MD5 : 476476d4d42b136c630e3f6118c98143 |
CRC32 : 0xB6DD9FCC |
MD5 : 56c42ee44828e36e5f40ec1d7a772dda |
CRC32 : 0xE8C0D498 |
/sequencer_defines.h
117,7 → 117,7
#define RDIMM 0 |
#define READ_AFTER_WRITE_CALIBRATION 1 |
#define READ_VALID_FIFO_SIZE 16 |
#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504aa |
#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504ab |
#define RLDRAM3 0 |
#define RLDRAMII 0 |
#define RLDRAMX 0 |