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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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Rev 19 → Rev 20

/trunk/rtl/verilog/T6507LP_FSM.v
45,12 → 45,21
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2009/03/06 16:52:14 creep
// First version of the FSM.
// Nothing works.
//
//
 
`timescale 1ns / 1ps
 
parameter FETCH_0 = 3'b000;
parameter FETCH_1 = 3'b000;
parameter FETCH_OP = 3'b000;
parameter FETCH_1 = 3'b001;
parameter FETCH_HIGH_TO_PC = 3'b010;
parameter FETCH_HIGH_TO_TEMP = 3'b011;
parameter READ_EFFECTIVE = 3'b100;
parameter DO_OPERATION = 3'b101;
parameter WRITE_EFFECTIVE = 3'b110;
 
 
module t6507lp_fsm(clk_in, n_rst_in, data, address);
57,9 → 66,9
input clk_in;
input n_rst_in;
inout [7:0] data;
output [13:0] address;
output [12:0] address;
 
reg [15:0] PC;
reg [12:0] PC;
reg [7:0] SP;
 
reg [3:0] state;
68,7 → 77,7
begin
if (n_rst_in == 1'b0) begin
// TODO: all the reset stuff
state <= FETCH_0;
state <= FETCH_OP;
end
else begin
 
76,9 → 85,15
state <= next_state;
case (state)
FETCH_0: begin
FETCH_OP: begin // TODO: bus controller enables memory or cpu enables it?
address = PC;
end
FETCH_1: begin
address = PC;
end
FETCH_HIGH_TO_PC: begin
address = PC;
end
endcase
end
end
85,13 → 100,59
 
always @ (*)
if (n_rst_in == 1'b0) begin
next_state = FETCH_0;
next_state = FETCH_OP;
end
else begin
case (state)
FETCH_0: begin
FETCH_OP: begin
next_state = FETCH_1;
end
FETCH_1: begin
if (implied or immediate) begin
next_state = FETCH_OP;
end
else if (absolute) begin
if (jump) begin
next_state = FETCH_HIGH_TO_PC;
end
else
next_state = FETCH_HIGH_TO_TEMP;
end
else if (zeropage) begin
if (write_operations) begin // STA, STX, STY, SAX
next_state = WRITE_EFFECTIVE;
end
else begin
next_state = READ_EFFECTIVE;
end
end
end
FETCH_HIGH_TO_PC: begin
next_state = FETCH_OP;
end
FETCH_HIGH_TO_TEMP: begin
if (write_operations) begin // STA, STX, STY, SAX
next_state = WRITE_EFFECTIVE;
end
else begin
next_state = READ_EFFECTIVE;
end
end
READ_EFFECTIVE: begin
if (read_instructions) begin // (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, LAX, ?NOP?)
next_state = FETCH_OP;
end
else begin // this are the Read_Modify_Write_(ASL, LSR, ROL, ROR, INC, DEC, SLO, SRE, RLA, RRA, ISB, DCP)
next_state = DO_OPERATION;
end
end
DO_OPERATION: begin
next_state = WRITE_EFFECTIVE;
end
WRITE_EFFECTIVE: begin
next_state = FETCH_OP;
end
 
endcase
end
begin

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