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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev 215 → Rev 216

/t6507lp/trunk/rtl/verilog/video.v
64,162 → 64,137
assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
 
reg VSYNC; // vertical sync set-clear
reg VBLANK; // 1 1 1 vertical blank set-clear
reg [2:0] VBLANK; // vertical blank set-clear
reg WSYNC; // s t r o b e wait for leading edge of horizontal blank
reg RSYNC; // s t r o b e reset horizontal sync counter
reg NUSIZ0; // 1 1 1 1 1 1 number-size player-missile 0
reg NUSIZ1; // 1 1 1 1 1 1 number-size player-missile 1
reg COLUP0; // 1 1 1 1 1 1 1 color-lum player 0
reg COLUP1; // 1 1 1 1 1 1 1 color-lum player 1
reg COLUPF; // 1 1 1 1 1 1 1 color-lum playfield
reg COLUBK; // 1 1 1 1 1 1 1 color-lum background
reg CTRLPF; // 1 1 1 1 1 control playfield ball size & collisions
reg REFP0; // 1 reflect player 0
reg REFP1; // 1 reflect player 1
reg PF0; // 1 1 1 1 playfield register byte 0
reg PF1; // 1 1 1 1 1 1 1 1 playfield register byte 1
reg PF2; // 1 1 1 1 1 1 1 1 playfield register byte 2
reg [5:0] NUSIZ0; // number-size player-missile 0
reg [5:0] NUSIZ1; // number-size player-missile 1
reg [6:0] COLUP0; // color-lum player 0
reg [6:0] COLUP1; // color-lum player 1
reg [6:0] COLUPF; // color-lum playfield
reg [6:0] COLUBK; // color-lum background
reg [4:0] CTRLPF; // control playfield ball size & collisions
reg REFP0; // reflect player 0
reg REFP1; // reflect player 1
reg [3:0] PF0; // playfield register byte 0
reg [7:0] PF1; // playfield register byte 1
reg [7:0] PF2; // playfield register byte 2
reg RESP0; // s t r o b e reset player 0
reg RESP1; // s t r o b e reset player 1
reg RESM0; // s t r o b e reset missile 0
reg RESM1; // s t r o b e reset missile 1
reg RESBL; // s t r o b e reset ball
reg AUDC0; // 1 1 1 1 audio control 0
reg AUDC1; // 1 1 1 1 1 audio control 1
reg AUDF0; // 1 1 1 1 1 audio frequency 0
reg AUDF1; // 1 1 1 1 audio frequency 1
reg AUDV0; // 1 1 1 1 audio volume 0
reg AUDV1; // 1 1 1 1 audio volume 1
reg GRP0; // 1 1 1 1 1 1 1 1 graphics player 0
reg GRP1; // 1 1 1 1 1 1 1 1 graphics player 1
reg ENAM0; // 1 graphics (enable) missile 0
reg ENAM1; // 1 graphics (enable) missile 1
reg ENABL; // 1 graphics (enable) ball
reg HMP0; // 1 1 1 1 horizontal motion player 0
reg HMP1; // 1 1 1 1 horizontal motion player 1
reg HMM0; // 1 1 1 1 horizontal motion missile 0
reg HMM1; // 1 1 1 1 horizontal motion missile 1
reg HMBL; // 1 1 1 1 horizontal motion ball
reg VDELP0; // 1 vertical delay player 0
reg VDEL01; // 1 vertical delay player 1
reg VDELBL; // 1 vertical delay ball
reg RESMP0; // 1 reset missile 0 to player 0
reg RESMP1; // 1 reset missile 1 to player 1
reg [3:0] AUDC0; // audio control 0
reg [4:0] AUDC1; // audio control 1
reg [4:0] AUDF0; // audio frequency 0
reg [3:0] AUDF1; // audio frequency 1
reg [3:0] AUDV0; // audio volume 0
reg [3:0] AUDV1; // audio volume 1
reg [7:0] GRP0; // graphics player 0
reg [7:0] GRP1; // graphics player 1
reg ENAM0; // graphics (enable) missile 0
reg ENAM1; // graphics (enable) missile 1
reg ENABL; // graphics (enable) ball
reg [3:0] HMP0; // horizontal motion player 0
reg [3:0] HMP1; // horizontal motion player 1
reg [3:0] HMM0; // horizontal motion missile 0
reg [3:0] HMM1; // horizontal motion missile 1
reg [3:0] HMBL; // horizontal motion ball
reg VDELP0; // vertical delay player 0
reg VDEL01; // vertical delay player 1
reg VDELBL; // vertical delay ball
reg RESMP0; // reset missile 0 to player 0
reg RESMP1; // reset missile 1 to player 1
reg HMOVE; // s t r o b e apply horizontal motion
reg HMCLR; // s t r o b e clear horizontal motion registers
reg CXCLR ; // s t r o b e clear collision latches
reg CXCLR ; // s t r o b e clear collision latches
 
always @(posedge clk or negedge reset_n) begin // R/W register/memory handling
reg [1:0] CXM0P; // read collision MO P1 M0 P0
reg [1:0] CXM1P; // read collision M1 P0 M1 P1
reg [1:0] CXP0FB; // read collision P0 PF P0 BL
reg [1:0] CXP1FB; // read collision P1 PF P1 BL
reg [1:0] CXM0FB; // read collision M0 PF M0 BL
reg [1:0] CXM1FB; // read collision M1 PF M1 BL
reg CXBLPF; // read collision BL PF unused
reg [1:0] CXPPMM; // read collision P0 P1 M0 M1
reg INPT0; // read pot port
reg INPT1; // read pot port
reg INPT2; // read pot port
reg INPT3; // read pot port
reg INPT4; // read input
reg INPT5; // read input
 
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) begin
data_drv <= 8'h00;
end
else begin
if (reading) begin // reading!
if (mem_rw == 1'b0) begin // reading!
case (address)
10'h280: data_drv <= port_a;
10'h281: data_drv <= ddra;
10'h282: data_drv <= port_b;
10'h283: data_drv <= 8'h00; // portb ddr is always input
10'h284: data_drv <= timer;
default: data_drv <= ram[address];
6'h00: data_drv <= {CXM0P, 6'b000000};
6'h01: data_drv <= {CXM1P, 6'b000000};
6'h02: data_drv <= {CXP0FB, 6'b000000};
6'h03: data_drv <= {CXP1FB, 6'b000000};
6'h04: data_drv <= {CXM0FB, 6'b000000};
6'h05: data_drv <= {CXM1FB, 6'b000000};
6'h06: data_drv <= {CXBLPF, 7'b000000};
6'h07: data_drv <= {CXPPMM, 6'b000000};
6'h08: data_drv <= {INPT0, 7'b000000};
6'h09: data_drv <= {INPT1, 7'b000000};
6'h0A: data_drv <= {INPT2, 7'b000000};
6'h0B: data_drv <= {INPT3, 7'b000000};
6'h0C: data_drv <= {INPT4, 7'b000000};
6'h0D: data_drv <= {INPT5, 7'b000000};
default: ;
endcase
end
else if (writing) begin // writing!
else begin // writing!
case (address)
10'h281: begin
ddra <= data;
end
10'h294: begin
c1_timer <= 1'b1;
c8_timer <= 1'b0;
c64_timer <= 1'b0;
c1024_timer <= 1'b0;
timer <= data;
flipped <= 1'b0;
counter <= 11'd1;
6'h00: begin
VSYNC <= data;
end
10'h295: begin
c1_timer <= 1'b0;
c8_timer <= 1'b1;
c64_timer <= 1'b0;
c1024_timer <= 1'b0;
timer <= data;
flipped <= 1'b0;
counter <= 11'd7;
6'h01: begin
VBLANK <= data;
end
10'h296: begin
c1_timer <= 1'b0;
c8_timer <= 1'b0;
c64_timer <= 1'b1;
c1024_timer <= 1'b0;
timer <= data;
flipped <= 1'b0;
counter <= 11'd63;
6'h02: begin
WSYNC <= data;
end
10'h297: begin
c1_timer <= 1'b0;
c8_timer <= 1'b0;
c64_timer <= 1'b0;
c1024_timer <= 1'b1;
timer <= data;
flipped <= 1'b0;
counter <= 11'd1023;
6'h03: begin
RSYNC <= data;
end
6'h04: begin
NUSIZ0 <= data;
end
6'h05: begin
NUSIZ1 <= data;
end
6'h06: begin
COLUP0 <= data;
end
6'h07: begin
COLUP1 <= data;
end
6'h08: begin
COLUPF <= data;
end
6'h09: begin
COLUBK <= data;
end
6'h0a: begin
CTRLPF <= data;
end
6'h0b: begin
NUSIZ1 <= data;
end
6'h0c: begin
NUSIZ1 <= data;
end
default: begin
ram[address] <= data;
end
endcase
end
if (!writing_at_timer) begin
if (flipped || timer == 8'd0) begin // finished counting
counter <= 11'd0;
timer <= timer - 8'd1;
flipped <= 1'b1;
end
else begin
if (counter == 11'd0) begin
timer <= timer - 8'd1;
if (c1_timer) begin
counter <= 11'd0;
end
if (c8_timer) begin
counter <= 11'd7;
end
if (c64_timer) begin
counter <= 11'd63;
end
if (c1024_timer) begin
counter <= 11'd1023;
end
end
else begin
counter <= counter - 11'd1;
end
end
end
end
end
always @(*) begin // logic for easier controlling
reading = 1'b0;
writing = 1'b0;
writing_at_timer = 1'b0;
 
if (enable && reset_n) begin
if (mem_rw == 1'b0) begin
reading = 1'b1;
end
else begin
writing = 1'b1;
 
if ( (address == 10'h294) || (address == 10'h295) || (address == 10'h296) || (address == 10'h297) ) begin
writing_at_timer = 1'b1;
end
end
end
end
endmodule
 
/t6507lp/trunk/fv/fsm_opcodes.e
45,11 → 45,11
CMP_IDX = 8'hC1,
CMP_IDY = 8'hD1,
CPX_IMM = 8'hE0,
//CPX_ZPG = 8'hE4,
//CPX_ABS = 8'hEC,
CPX_ZPG = 8'hE4,
CPX_ABS = 8'hEC,
CPY_IMM = 8'hC0,
//CPY_ZPG = 8'hC4,
//CPY_ABS = 8'hCC,
CPY_ZPG = 8'hC4,
CPY_ABS = 8'hCC,
DEC_ZPG = 8'hC6,
DEC_ZPX = 8'hD6,
DEC_ABS = 8'hCE,
71,7 → 71,7
INX_IMP = 8'hE8,
INY_IMP = 8'hC8,
JMP_ABS = 8'h4C,
//JMP_IND = 8'h6C,
JMP_IND = 8'h6C,
//JSR_ABS = 8'h20,
LDA_IMM = 8'hA9,
LDA_ZPG = 8'hA5,
135,10 → 135,10
STA_ZPG = 8'h85,
STA_ZPX = 8'h95,
STA_ABS = 8'h8D,
//STA_ABX = 8'h9D,
//STA_ABY = 8'h99,
STA_ABX = 8'h9D,
STA_ABY = 8'h99,
STA_IDX = 8'h81,
//STA_IDY = 8'h91,
STA_IDY = 8'h91,
STX_ZPG = 8'h86,
STX_ZPY = 8'h96,
STX_ABS = 8'h8E,
/t6507lp/trunk/fv/fsm_chk.e
16,6 → 16,8
keep soft SP == 0;
!pointer : byte;
keep soft pointer == 0;
!pointer_h : byte;
keep soft pointer_h == 0;
 
!more_cycles : bool;
keep soft more_cycles == FALSE;
174,6 → 176,8
instruction == BIT_ABS ||
instruction == AND_ABS ||
instruction == CMP_ABS ||
instruction == CPX_ABS ||
instruction == CPY_ABS ||
instruction == DEC_ABS ||
instruction == EOR_ABS ||
instruction == INC_ABS ||
198,6 → 202,8
instruction == ADC_ZPG ||
instruction == SBC_ZPG ||
instruction == CMP_ZPG ||
instruction == CPX_ZPG ||
instruction == CPY_ZPG ||
instruction == BIT_ZPG ||
instruction == STA_ZPG ||
instruction == STX_ZPG ||
228,6 → 234,8
instruction == STY_ZPX ||
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == STA_ABX ||
instruction == STA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
262,13 → 270,14
instruction == CMP_IDX ||
instruction == SBC_IDX ||
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
instruction == ADC_IDY ||
instruction == CMP_IDY ||
instruction == SBC_IDY
instruction == SBC_IDY ||
instruction == JMP_IND
) : {
new_state = CYCLE_3;
pointer = input.data_in;
333,7 → 342,7
};
(
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
345,11 → 354,19
PCL = input.data_in;
};
(
instruction == JMP_IND
) : {
new_state = CYCLE_4;
pointer_h = input.data_in;
};
(
instruction == ADC_ABS ||
instruction == ASL_ABS ||
instruction == BIT_ABS ||
instruction == AND_ABS ||
instruction == CMP_ABS ||
instruction == CPX_ABS ||
instruction == CPY_ABS ||
instruction == DEC_ABS ||
instruction == EOR_ABS ||
instruction == INC_ABS ||
366,6 → 383,8
instruction == STY_ABS ||
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == STA_ABX ||
instruction == STA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
407,7 → 426,8
// new_state = CYCLE_5;
//};
(
instruction == RTS_IMP
instruction == RTS_IMP ||
instruction == JMP_IND
) : {
new_state = CYCLE_5;
PCL = input.data_in;
439,6 → 459,8
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX ||
instruction == STA_ABX ||
instruction == STA_ABY ||
(
more_cycles == TRUE &&
(
478,7 → 500,7
};
(
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
531,11 → 553,11
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX ||
instruction == STA_IDY ||
(
more_cycles == TRUE &&
(
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
560,6 → 582,12
new_state = CYCLE_6;
PCH = input.data_in;
};
(
instruction == JMP_IND
) : {
new_state = CYCLE_1;
PCH = input.data_in;
};
default : {
new_state = CYCLE_1;
};
636,6 → 664,8
last_instruction == AND_IMM ||
last_instruction == BIT_ABS ||
last_instruction == CMP_ABS ||
last_instruction == CPX_ABS ||
last_instruction == CPY_ABS ||
last_instruction == CMP_IMM ||
last_instruction == CPX_IMM ||
last_instruction == CPY_IMM ||
662,6 → 692,8
last_instruction == ADC_ZPG ||
last_instruction == SBC_ZPG ||
last_instruction == CMP_ZPG ||
last_instruction == CPX_ZPG ||
last_instruction == CPY_ZPG ||
last_instruction == BIT_ZPG ||
last_instruction == LDA_ZPX ||
last_instruction == LDX_ZPY ||
780,6 → 812,8
instructions == BIT_ABS ||
instructions == BRK_IMP ||
instructions == CMP_ABS ||
instructions == CPX_ABS ||
instructions == CPY_ABS ||
instructions == CMP_IMM ||
instructions == CPX_IMM ||
instructions == CPY_IMM ||
810,6 → 844,8
instructions == ADC_ZPG ||
instructions == SBC_ZPG ||
instructions == CMP_ZPG ||
instructions == CPX_ZPG ||
instructions == CPY_ZPG ||
instructions == BIT_ZPG ||
instructions == ASL_ZPG ||
instructions == LSR_ZPG ||
837,6 → 873,8
instructions == STA_ZPX ||
instructions == LDA_ABX ||
instructions == LDA_ABY ||
instructions == STA_ABX ||
instructions == STA_ABY ||
instructions == LDX_ABY ||
instructions == LDY_ABX ||
instructions == EOR_ABX ||
866,13 → 904,14
instructions == CMP_IDX ||
instructions == SBC_IDX ||
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
instructions == ADC_IDY ||
instructions == CMP_IDY ||
instructions == SBC_IDY
instructions == SBC_IDY ||
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
1117,7 → 1156,7
instructions == CMP_IDX ||
instructions == SBC_IDX ||
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
1144,6 → 1183,8
instructions == ASL_ABS ||
instructions == BIT_ABS ||
instructions == CMP_ABS ||
instructions == CPX_ABS ||
instructions == CPY_ABS ||
instructions == DEC_ABS ||
instructions == EOR_ABS ||
instructions == INC_ABS ||
1218,6 → 1259,25
};
};
(
instructions == STA_ABX ||
instructions == STA_ABY ||
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (addr != PC) {
dut_error("ADDR should be equal SP!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
PC = PC + 1;
};
(
instructions == LDA_ZPG ||
instructions == LDX_ZPG ||
instructions == LDY_ZPG ||
1227,6 → 1287,8
instructions == ADC_ZPG ||
instructions == SBC_ZPG ||
instructions == CMP_ZPG ||
instructions == CPX_ZPG ||
instructions == CPY_ZPG ||
instructions == BIT_ZPG ||
instructions == ASL_ZPG ||
instructions == LSR_ZPG ||
1334,6 → 1396,58
// SP = SP - 1;
//};
(
instructions == STA_ABX
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == STA_ABY
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + Y > 255) {
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR should be equal SP!");
};
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == LDA_ZPX ||
instructions == LDY_ZPX ||
instructions == EOR_ZPX ||
1439,7 → 1553,7
};
(
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
1464,6 → 1578,25
};
};
(
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != pointer) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != pointer_h[4:0]) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == LDX_ZPY ||
instructions == LDA_ABY ||
instructions == LDX_ABY ||
1501,6 → 1634,8
instructions == ASL_ABS ||
instructions == BIT_ABS ||
instructions == CMP_ABS ||
instructions == CPX_ABS ||
instructions == CPY_ABS ||
instructions == DEC_ABS ||
instructions == EOR_ABS ||
instructions == INC_ABS ||
1690,6 → 1825,37
};
SP = SP - 1;
};
(
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (pointer + 1 > 255) {
if (addr[7:0] != pointer + 1 - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != pointer + 1) {
dut_error("ADDR should be equal SP!");
};
};
-- TODO: This is the correct behaviour expected from spec
--if (addr[12:8] != pointer_h[4:0]) {
-- print addr[7:0], pointer;
-- print addr[12:8], pointer_h[4:0];
-- dut_error("ADDR should be equal SP!");
--};
PC[7:0] = PCL;
PC[12:8] = PCH[4:0];
};
//JSR_ABS : {
// if (alu_opcode.as_a(byte) != 0) {
// dut_error("Opcode is Wrong!");
1736,10 → 1902,14
dut_error("ADDR is wrong");
};
};
if (addr[12:8] != 0) {
print addr[12:8], PCH[4:0];
dut_error("ADDR is wrong");
};
};
(
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
1766,6 → 1936,12
dut_error("ADDR is wrong");
};
};
-- TODO: This is the expected behavior (took from spec)
-- addr[12:8] is 0 or 1 acording to PCL + Y > 255
--if (addr[12:8] != PCH[4:0]) {
-- print addr[12:8], PCH[4:0];
-- dut_error("ADDR is wrong");
--};
};
(
instructions == STA_IDX
1791,6 → 1967,64
};
};
(
instructions == STA_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH + 1) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == STA_ABY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + Y > 255) {
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH + 1) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == RTI_IMP
) : {
if (alu_opcode != instructions) {
2076,6 → 2310,35
};
};
(
instructions == STA_IDY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (PCL + Y > 255) {
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR is wrong");
};
if (addr[12:8] != PCH[4:0] + 1) {
dut_error("ADDR is wrong");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR is wrong");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR is wrong");
};
};
};
(
instructions == STA_IDX
) : {
if (alu_opcode.as_a(byte) != 0) {

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