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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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    from Rev 230 to Rev 231
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Rev 230 → Rev 231

/t6507lp/trunk/rtl/verilog/controller_test.v
86,9 → 86,8
 
always @ (posedge clk_358 or negedge reset_n) begin
if (reset_n == 1'b0) begin
vert_counter <= 6'd0;
hor_counter <= 8'd0;
vert_counter = 9'd0;
vert_counter <= 9'd0;
end
else begin
if (hor_counter == 8'd227) begin // last colum
/t6507lp/trunk/rtl/verilog/test_top.v
56,7 → 56,7
output VGA_VS;
output VGA_HS;
 
//wire [11:0] pixel;
wire [11:0] pixel;
wire [8:0] vert_counter;
 
vga_controller vga_controller (

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