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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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    /t6507lp/trunk/rtl/verilog
    from Rev 129 to Rev 136
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Rev 129 → Rev 136

/T6507LP_ALU_TestBench.v File deleted
/t6507lp.v
55,10 → 55,10
localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
 
// note: in the top level inputs are just inputs, outputs are just outputs and the internal signals are wired.
input clk;
input reset_n;
input [DATA_SIZE_:0] data_in;
output rw_mem;
input clk;
input reset_n;
input [DATA_SIZE_:0] data_in;
output rw_mem;
output [DATA_SIZE_:0] data_out;
output [ADDR_SIZE_:0] address;
 
71,7 → 71,7
wire alu_enable;
 
// `include "T6507LP_Package.v"
//TODO change rw_mem to mem_rw
//TODO change rw_mem to mem_rw
t6507lp_fsm #(DATA_SIZE, ADDR_SIZE) t6507lp_fsm(
.clk (clk),
.reset_n (reset_n),
88,15 → 88,15
.alu_enable (alu_enable)
);
 
T6507LP_ALU T6507LP_ALU (
.clk_i (clk),
.n_rst_i (reset_n),
.alu_enable (alu_enable),
.alu_result (alu_result),
.alu_status (alu_status),
.alu_opcode (alu_opcode),
.alu_a (alu_a),
.alu_x (alu_x),
.alu_y (alu_y)
);
T6507LP_ALU T6507LP_ALU (
.clk (clk),
.rst_n (reset_n),
.alu_enable (alu_enable),
.alu_result (alu_result),
.alu_status (alu_status),
.alu_opcode (alu_opcode),
.alu_a (alu_a),
.alu_x (alu_x),
.alu_y (alu_y)
);
endmodule
/T6507LP_ALU.v
46,10 → 46,10
 
// TODO: verify code identation
 
module T6507LP_ALU( clk_i, n_rst_i, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
module T6507LP_ALU( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
 
input wire clk_i;
input wire n_rst_i;
input wire clk;
input wire reset_n;
input wire alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
64,21 → 64,14
 
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] temp1;
reg [7:0] temp2;
reg [7:0] bcd1;
reg [7:0] bcd2;
 
`include "T6507LP_Package.v"
`include "t6507lp_package.v"
 
//always @ * begin
// STATUS[Z] = (result == 0) ? 1 : 0;
// STATUS[N] = result[7];
// STATUS[5] = 1;
//end
 
 
always @ (posedge clk_i or negedge n_rst_i)
always @ (posedge clk or negedge reset_n)
begin
if (n_rst_i == 0) begin
if (reset_n == 0) begin
//$display("RESTART");
alu_result <= 0;
alu_status[C] <= 0;
93,72 → 86,42
Y <= 0;
alu_x <= 0;
alu_y <= 0;
//STATUS[C] <= 0;
//STATUS[N] <= 0;
//STATUS[V] <= 0;
//STATUS[Z] <= 1;
//STATUS[I] <= 0;
//STATUS[B] <= 0;
//STATUS[D] <= 0;
end
else if ( alu_enable == 1 ) begin
//A <= A;
//X <= X;
//Y <= Y;
case (alu_opcode)
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
ASL_ACC,
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY,
LSR_ACC,
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY,
ROL_ACC, ROR_ACC,
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY,
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
PLA_IMP,
TXA_IMP, TYA_IMP :
ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
begin
A <= result;
alu_result <= result;
A <= result;
alu_status <= STATUS;
end
// LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
//PLA_IMP:
//begin
// A <= result;
// alu_status <= STATUS;
//$display("A <= result;");
//$display("%h <= %h", A, result);
//$display("alu_status <= STATUS;");
//$display("%h <= %h", alu_status, STATUS);
//end
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
begin
//$display("Aqui deu erro");
//$display("X <= Result");
//$display("%h <= %h", X, result);
X <= result;
alu_x <= result;
X <= result;
alu_x <= result;
alu_status <= STATUS;
end
TXS_IMP :
begin
X <= result;
X <= result;
alu_x <= result;
end
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
begin
Y <= result;
alu_y <= result;
Y <= result;
alu_y <= result;
alu_status <= STATUS;
end
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX,
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX,
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
CPX_IMM, CPX_ZPG, CPX_ABS,
CPY_IMM, CPY_ZPG, CPY_ABS,
PHP_IMP :
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX,
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS,
CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,
CPY_ZPG, CPY_ABS, PHP_IMP :
begin
alu_status <= STATUS;
end
218,9 → 181,9
end
 
always @ (*) begin
temp1 = A;
temp2 = alu_a;
result = alu_result;
bcd1 = A;
bcd2 = alu_a;
result = alu_result;
STATUS[C] = alu_status[C];
STATUS[V] = alu_status[V];
STATUS[Z] = (result == 0) ? 1 : 0;
229,12 → 192,11
STATUS[B] = alu_status[B];
STATUS[I] = alu_status[I];
STATUS[D] = alu_status[D];
 
case (alu_opcode)
// BIT - Bit Test
BIT_ZPG, BIT_ABS:
begin
BIT_ZPG, BIT_ABS: begin
result = A & alu_a;
//STATUS[V] = alu_a[6];
end
 
// BRK - Force Interrupt
277,8 → 239,7
// PHA - Push A
// TAX - Transfer Accumulator to X
// TAY - Transfer Accumulator to Y
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY :
begin
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
result = A;
end
 
285,15 → 246,13
// STX - Store X Register
// TXA - Transfer X to Accumulator
// TXS - Transfer X to Stack pointer
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP :
begin
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
result = X;
end
// STY - Store Y Register
// TYA - Transfer Y to Accumulator
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP :
begin
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
result = Y;
end
 
313,8 → 272,7
end
 
// INC - Increment memory
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX :
begin
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
result = alu_a + 1;
end
 
329,8 → 287,7
end
 
// DEC - Decrement memory
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX :
begin
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
result = alu_a - 1;
end
 
345,27 → 302,24
end
 
// ADC - Add with carry
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY :
begin
//temp1 = A;
//temp2 = alu_a;
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
if (alu_status[D] == 1) begin
if (A[3:0] > 9) begin
temp1 = A + 6; // A = A - 10 and A = A + 16
bcd1 = A + 6; // A = A - 10 and A = A + 16
end
if (temp1[7:4] > 9) begin
temp1 = temp1[7:4] + 6; // A = A - 10 and A = A + 16
if (bcd1[7:4] > 9) begin
bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
end
if (alu_a[3:0] > 9) begin
temp2 = alu_a + 6;
bcd2 = alu_a + 6;
end
if (temp2[7:4] > 9) begin
temp2 = temp2[7:4] + 6; // A = A - 10 and A = A + 16
if (bcd2[7:4] > 9) begin
bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
end
end
 
{STATUS[C],result} = temp1 + temp2 + alu_status[C];
if ((temp1[7] == temp2[7]) && (temp1[7] != alu_result[7]))
{STATUS[C],result} = bcd1 + bcd2 + alu_status[C];
if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
STATUS[V] = 1;
else
STATUS[V] = 0;
382,21 → 336,18
end
// AND - Logical AND
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY :
begin
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
result = A & alu_a;
end
 
// CMP - Compare
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY :
begin
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
result = A - alu_a;
STATUS[C] = (A >= alu_a) ? 1 : 0;
end
 
// EOR - Exclusive OR
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY :
begin
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
result = A ^ alu_a ;
end
 
407,42 → 358,34
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
TSX_IMP :
begin
TSX_IMP : begin
result = alu_a;
//$display("result = %h alu_a = %h",result, alu_a);
end
 
// ORA - Logical OR
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY :
begin
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
result = A | alu_a;
end
 
// SBC - Subtract with Carry
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY :
begin
//temp1 = A;
//temp2 = alu_a;
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
if (alu_status[D] == 1) begin
if (A[3:0] > 9) begin
temp1 = A + 6; // A = A - 10 and A = A + 16
bcd1 = A + 6; // A = A - 10 and A = A + 16
end
if (temp1[7:4] > 9) begin
temp1 = temp1[7:4] + 6; // A = A - 10 and A = A + 16
if (bcd1[7:4] > 9) begin
bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
end
if (alu_a[3:0] > 9) begin
temp2 = alu_a + 6;
bcd2 = alu_a + 6;
end
if (temp2[7:4] > 9) begin
temp2 = temp2[7:4] + 6; // A = A - 10 and A = A + 16
if (bcd2[7:4] > 9) begin
bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
end
end
 
{STATUS[C],result} = temp1 - temp2 - ~alu_status[C];
//$display("STATUS[C] = %h result = %h", STATUS[C],result);
//$display("temp1 = %h temp2 = %h alu_status = %h", temp1,temp2,alu_status[C]);
if ((temp1[7] == temp2[7]) && (temp1[7] != alu_result[7]))
{STATUS[C],result} = bcd1 - bcd2 - ~alu_status[C];
if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
STATUS[V] = 1;
else
STATUS[V] = 0;
452,8 → 395,7
ASL_ACC : begin
{STATUS[C],result} = A << 1;
end
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX :
begin
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
{STATUS[C],result} = alu_a << 1;
end
 
461,8 → 403,7
LSR_ACC: begin
{result, STATUS[C]} = A >> 1;
end
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX :
begin
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
{result, STATUS[C]} = alu_a >> 1;
end
470,8 → 411,7
ROL_ACC : begin
{STATUS[C],result} = {A,alu_status[C]}; //TODO: does it really work?
end
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX :
begin
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
{STATUS[C],result} = {alu_a,alu_status[C]};
end
 
479,21 → 419,18
ROR_ACC : begin
{result,STATUS[C]} = {alu_status[C],A};
end
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
begin
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
{result, STATUS[C]} = {alu_status[C], alu_a};
end
 
// CPX - Compare X Register
CPX_IMM, CPX_ZPG, CPX_ABS :
begin
CPX_IMM, CPX_ZPG, CPX_ABS : begin
result = X - alu_a;
STATUS[C] = (X >= alu_a) ? 1 : 0;
end
 
// CPY - Compare Y Register
CPY_IMM, CPY_ZPG, CPY_ABS :
begin
CPY_IMM, CPY_ZPG, CPY_ABS : begin
result = Y - alu_a;
STATUS[C] = (Y >= alu_a) ? 1 : 0;
end
/t6507lp_alu_tb.v
0,0 → 1,579
`include "timescale.v"
module t6507lp_alu_tb;
 
`include "t6507lp_package.v"
 
reg clk;
reg reset;
reg alu_enable;
wire [7:0] alu_result;
wire [7:0] alu_status;
reg [7:0] alu_opcode;
reg [7:0] alu_a;
wire [7:0] alu_x;
wire [7:0] alu_y;
reg [31:0] i;
 
reg [7:0] alu_result_expected;
reg [7:0] alu_status_expected;
reg [7:0] alu_x_expected;
reg [7:0] alu_y_expected;
 
reg c_aux;
reg [7:0] temp;
 
t6507lp_alu DUT (
.clk (clk),
.reset_n (reset_n),
.alu_enable (alu_enable),
.alu_result (alu_result),
.alu_status (alu_status),
.alu_opcode (alu_opcode),
.alu_a (alu_a),
.alu_x (alu_x),
.alu_y (alu_y)
);
 
 
localparam period = 10;
 
task check;
begin
$display(" RESULTS EXPECTED");
$display("alu_result %h %h ", alu_result, alu_result_expected);
$display("alu_status %b %b ", alu_status, alu_status_expected);
$display("alu_x %h %h ", alu_x, alu_x_expected );
$display("alu_y %h %h ", alu_y, alu_y_expected );
if ((alu_result_expected != alu_result) || (alu_status_expected != alu_status) || (alu_x_expected != alu_x) || (alu_y_expected != alu_y))
begin
$display("ERROR at instruction %h",alu_opcode);
$finish;
end
else
begin
$display("Instruction %h... OK!", alu_opcode);
end
end
endtask
 
 
always begin
#(period/2) clk = ~clk;
end
 
initial
begin
// Reset
clk = 0;
reset_n = 0;
@(negedge clk_i);
@(negedge clk_i);
reset_n = 1;
alu_enable = 1;
alu_result_expected = 8'h00;
alu_status_expected = 8'b00100010;
alu_x_expected = 8'h00;
alu_y_expected = 8'h00;
 
// LDA
alu_a = 0;
alu_opcode = LDA_IMM;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
@(negedge clk_i);
alu_result_expected = 8'h00;
// NV1BDIZC
alu_status_expected = 8'b00100010;
check();
 
// ADC
alu_opcode = ADC_IMM;
alu_a = 1;
for (i = 0; i < 1000; i = i + 1)
begin
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
{alu_status_expected[C], alu_result_expected} = alu_a + alu_result_expected + alu_status_expected[C];
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
check();
end
 
// SBC
alu_opcode = SBC_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
{alu_status_expected[C], alu_result_expected} = alu_result_expected - alu_a - ~alu_status_expected[C];
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
check();
end
 
// LDA
alu_opcode = LDA_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
alu_result_expected = i;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// LDX
alu_opcode = LDX_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
alu_x_expected = i;
//alu_result_expected = i;
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_x_expected[7];
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// LDY
alu_opcode = LDY_IMM;
for (i = 0; i < 1001; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
alu_y_expected = i;
//alu_result_expected = i;
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_y_expected[7];
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// STA
alu_opcode = STA_ABS;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// STX
alu_opcode = STX_ABS;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//alu_result_expected = i;
//alu_x_expected = i;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// STY
alu_opcode = STY_ABS;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//alu_result_expected = i;
//alu_y_expected = i;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// CMP
alu_opcode = CMP_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
temp = alu_result_expected - alu_a;
alu_status_expected[Z] = (temp == 0) ? 1 : 0;
alu_status_expected[N] = temp[7];
alu_status_expected[C] = (alu_result_expected >= alu_a) ? 1 : 0;
//alu_result_expected = i;
//alu_y_expected = i;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// CPX
alu_opcode = CPX_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
temp = alu_x_expected - alu_a;
alu_status_expected[Z] = (temp == 0) ? 1 : 0;
alu_status_expected[N] = temp[7];
alu_status_expected[C] = (alu_x_expected >= alu_a) ? 1 : 0;
//alu_result_expected = i;
//alu_y_expected = i;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// CPY
alu_opcode = CPY_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
temp = alu_y_expected - alu_a;
alu_status_expected[Z] = (temp == 0) ? 1 : 0;
alu_status_expected[N] = temp[7];
alu_status_expected[C] = (alu_y_expected >= alu_a) ? 1 : 0;
//alu_result_expected = i;
//alu_y_expected = i;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// AND
alu_opcode = AND_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
alu_result_expected = i & alu_result_expected;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// ASL
alu_opcode = ASL_ACC;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
alu_status_expected[C] = alu_result_expected[7];
alu_result_expected[7:0] = alu_result_expected << 1;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
check();
end
 
// INC
alu_opcode = INC_ZPG;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_result_expected = alu_a + 1;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
check();
end
 
// INX
alu_opcode = INX_IMP;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_x_expected = alu_x_expected + 1;
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_x_expected[7];
check();
end
 
// INY
alu_opcode = INY_IMP;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_y_expected = alu_y_expected + 1;
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_y_expected[7];
check();
end
 
// DEC
alu_opcode = DEC_ZPG;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_result_expected = alu_a - 1;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
check();
end
 
// DEX
alu_opcode = DEX_IMP;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_x_expected = alu_x_expected - 1;
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_x_expected[7];
check();
end
 
// DEY
alu_opcode = DEY_IMP;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_y_expected = alu_y_expected - 1;
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_y_expected[7];
check();
end
 
 
// LDA
alu_a = 0;
alu_opcode = LDA_IMM;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
@(negedge clk_i);
alu_result_expected = 8'h00;
// NV1BDIZC
alu_status_expected = 8'b00100010;
check();
 
// BIT
alu_opcode = BIT_ZPG;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk_i);
$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_status_expected[Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0;
alu_status_expected[V] = alu_a[6];
alu_status_expected[N] = alu_a[7];
check();
end
// SEC
alu_opcode = SEC_IMP;
@(negedge clk_i);
alu_status_expected[C] = 1;
check();
 
// SED
alu_opcode = SED_IMP;
@(negedge clk_i);
alu_status_expected[D] = 1;
check();
 
// SEI
alu_opcode = SEI_IMP;
@(negedge clk_i);
alu_status_expected[I] = 1;
check();
 
// CLC
alu_opcode = CLC_IMP;
@(negedge clk_i);
alu_status_expected[C] = 0;
check();
 
// CLD
alu_opcode = CLD_IMP;
@(negedge clk_i);
alu_status_expected[D] = 0;
check();
 
// CLI
alu_opcode = CLI_IMP;
@(negedge clk_i);
alu_status_expected[I] = 0;
check();
 
// CLV
alu_opcode = CLV_IMP;
@(negedge clk_i);
alu_status_expected[V] = 0;
check();
 
// LDA
alu_opcode = LDA_IMM;
alu_a = 8'h76;
@(negedge clk_i);
alu_result_expected = alu_a;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
check();
 
// TAX
alu_opcode = TAX_IMP;
@(negedge clk_i);
alu_x_expected = alu_result_expected;
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_x_expected[7];
check();
 
// TAY
alu_opcode = TAY_IMP;
@(negedge clk_i);
alu_y_expected = alu_result_expected;
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_y_expected[7];
check();
// TSX
alu_opcode = TSX_IMP;
@(negedge clk_i);
alu_x_expected = alu_a;
//alu_result_expected = alu_a;
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_x_expected[7];
check();
 
// TXA
alu_opcode = TXA_IMP;
@(negedge clk_i);
alu_result_expected = alu_x_expected;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
check();
 
// TXS
alu_opcode = TXS_IMP;
@(negedge clk_i);
alu_result_expected = alu_x_expected;
check();
 
// TYA
alu_opcode = TYA_IMP;
@(negedge clk_i);
alu_result_expected = alu_y_expected;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
check();
 
// Nothing should happen
// BCC
alu_opcode = BCC_REL;
@(negedge clk_i);
check();
 
// BCS
alu_opcode = BCS_REL;
@(negedge clk_i);
check();
 
// BEQ
alu_opcode = BEQ_REL;
@(negedge clk_i);
check();
 
// BMI
alu_opcode = BMI_REL;
@(negedge clk_i);
check();
 
// BNE
alu_opcode = BNE_REL;
@(negedge clk_i);
check();
 
// BPL
alu_opcode = BPL_REL;
@(negedge clk_i);
check();
 
// BVC
alu_opcode = BVC_REL;
@(negedge clk_i);
check();
 
// BVS
alu_opcode = BVS_REL;
@(negedge clk_i);
check();
// JMP
alu_opcode = JMP_ABS;
@(negedge clk_i);
check();
 
// JMP
alu_opcode = JMP_IND;
@(negedge clk_i);
check();
// JSR
alu_opcode = JSR_ABS;
@(negedge clk_i);
check();
// NOP
alu_opcode = NOP_IMP;
@(negedge clk_i);
check();
 
// RTS
alu_opcode = RTS_IMP;
@(negedge clk_i);
check();
$display("TEST PASSED");
$finish;
end
 
endmodule
 

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