URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl/verilog
- from Rev 142 to Rev 143
- ↔ Reverse comparison
Rev 142 → Rev 143
/t6507lp_alu_wrapper.v
42,7 → 42,7
//////////////////////////////////////////////////////////////////////////// |
|
`include "timescale.v" |
`include "T6507LP_ALU.v" |
`include "t6507lp_alu.v" |
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module t6507lp_alu_wrapper(); |
parameter [3:0] DATA_SIZE = 4'd8; |
50,10 → 50,10
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// all inputs are regs |
reg clk; |
reg reset_n; |
reg alu_enable; |
reg [DATA_SIZE_:0] alu_opcode; |
reg [DATA_SIZE_:0] alu_a; |
wire reset_n; |
wire alu_enable; |
wire [DATA_SIZE_:0] alu_opcode; |
wire [DATA_SIZE_:0] alu_a; |
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// all outputs are wires |
wire [DATA_SIZE_:0] alu_result; |
64,11 → 64,16
initial clk = 0; |
always #10 clk <= ~clk; |
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//always #100 $write("working"); |
always @(posedge clk) begin |
$display("reset is %b", reset_n); |
$display("alu_enable is %b", alu_enable); |
$display("alu_opcode is %h", alu_opcode); |
$display("alu_a is %d", alu_a); |
end |
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T6507LP_ALU T6507LP_ALU ( |
.clk_i (clk), |
.n_rst_i (reset_n), |
t6507lp_alu t6507lp_alu ( |
.clk (clk), |
.reset_n (reset_n), |
.alu_enable (alu_enable), |
.alu_result (alu_result), |
.alu_status (alu_status), |
/t6507lp_alu_tb.v
68,7 → 68,7
reset_n = 0; |
@(negedge clk); |
@(negedge clk); |
reset_n = 1; |
//reset_n = 1; |
alu_enable = 1; |
alu_result_expected = 8'h00; |
alu_status_expected = 8'b00100010; |