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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path
    /t6507lp/trunk/rtl/verilog
    from Rev 148 to Rev 149
    Reverse comparison

Rev 148 → Rev 149

/t6507lp_alu.v
101,7 → 101,7
SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
begin
$display("A = %h result = %h", A, result);
//$display("A = %h result = %h", A, result);
//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
A <= result;
alu_result <= result;
188,12 → 188,12
always @ (*) begin
bcd1 = A;
bcd2 = alu_a;
result = alu_result;
STATUS[C] = alu_status[C];
STATUS[V] = alu_status[V];
STATUS[B] = alu_status[B];
STATUS[I] = alu_status[I];
STATUS[D] = alu_status[D];
//result = alu_result;
//STATUS[C] = STATUS[C];
//STATUS[V] = STATUS[V];
//STATUS[B] = STATUS[B];
//STATUS[I] = STATUS[I];
//STATUS[D] = STATUS[D];
 
case (alu_opcode)
// BIT - Bit Test
319,8 → 319,8
bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
end
end
$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
//$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
{STATUS[C],result} = bcd1 + bcd2 + alu_status[C];
if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
STATUS[V] = 1;
/t6507lp_alu_tb.v
83,7 → 83,7
@(negedge clk);
alu_result_expected = 8'h00;
// NV1BDIZC
alu_status_expected = 8'b00100010;
alu_status_expected = 8'b00100010;
check();
 
// ADC
91,10 → 91,11
alu_a = 1;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = $random;
@(negedge clk);
$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], DUT.result);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], DUT.result);
{alu_status_expected[C], alu_result_expected} = alu_a + alu_result_expected + alu_status_expected[C];
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
426,9 → 427,9
begin
alu_a = i;
@(negedge clk);
$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
alu_status_expected[Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0;
alu_status_expected[V] = alu_a[6];
alu_status_expected[N] = alu_a[7];

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