OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /t6507lp/trunk/rtl/verilog
    from Rev 225 to Rev 226
    Reverse comparison

Rev 225 → Rev 226

/test_top.v
44,9 → 44,9
 
`include "timescale.v"
 
module test_top(reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
module test_top(reset_n, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
 
input reset;
input reset_n;
input clk_50;
input [8:0] SW;
output [3:0] VGA_R;
56,14 → 56,13
output VGA_VS;
output VGA_HS;
 
//wire [479:0] line;
//wire [4:0] vert_counter;
wire [479:0] line;
wire [4:0] vert_counter;
 
vga_controller vga_controller (
.reset(reset),
.reset_n(reset_n),
.clk_50(clk_50),
.line(line),
.vert_counter(vert_counter),
.line(line),
.SW(SW),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
70,11 → 69,12
.VGA_B(VGA_B),
.LEDR(LEDR),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS)
.VGA_HS(VGA_HS),
.vert_counter(vert_counter)
);
 
controller_test controller_test (
.reset(reset),
controller_test controller_test (
.reset_n(reset_n),
.clk_50(clk_50),
.line(line),
.vert_counter(vert_counter)

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.