URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl/verilog
- from Rev 226 to Rev 225
- ↔ Reverse comparison
Rev 226 → Rev 225
/test_top.v
44,9 → 44,9
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`include "timescale.v" |
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module test_top(reset_n, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS); |
module test_top(reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS); |
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input reset_n; |
input reset; |
input clk_50; |
input [8:0] SW; |
output [3:0] VGA_R; |
56,13 → 56,14
output VGA_VS; |
output VGA_HS; |
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wire [479:0] line; |
wire [4:0] vert_counter; |
//wire [479:0] line; |
//wire [4:0] vert_counter; |
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vga_controller vga_controller ( |
.reset_n(reset_n), |
.reset(reset), |
.clk_50(clk_50), |
.line(line), |
.line(line), |
.vert_counter(vert_counter), |
.SW(SW), |
.VGA_R(VGA_R), |
.VGA_G(VGA_G), |
69,12 → 70,11
.VGA_B(VGA_B), |
.LEDR(LEDR), |
.VGA_VS(VGA_VS), |
.VGA_HS(VGA_HS), |
.vert_counter(vert_counter) |
.VGA_HS(VGA_HS) |
); |
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controller_test controller_test ( |
.reset_n(reset_n), |
controller_test controller_test ( |
.reset(reset), |
.clk_50(clk_50), |
.line(line), |
.vert_counter(vert_counter) |