URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl
- from Rev 111 to Rev 112
- ↔ Reverse comparison
Rev 111 → Rev 112
/verilog/t6507lp_fsm_tb.v
44,9 → 44,8
//// //// |
//////////////////////////////////////////////////////////////////////////// |
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`include "timescale.v" |
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`timescale 1ns / 1ps |
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module t6507lp_fsm_tb(); |
reg clk; |
reg reset_n; |
66,7 → 65,7
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integer my_i; |
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`include "../T6507LP_Package.v" // TODO: remove this include |
`include "T6507LP_Package.v" // TODO: remove this include |
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t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y); |
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/verilog/t6507lp_fsm.v
43,7 → 43,7
//// //// |
//////////////////////////////////////////////////////////////////////////// |
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`timescale 1ns / 1ps |
`include "timescale.v" |
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module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y); |
parameter [3:0] DATA_SIZE = 4'd8; |
100,7 → 100,7
localparam RESET = 5'b11111; |
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// OPCODES TODO: verify how this get synthesised |
`include "../T6507LP_Package.v" |
`include "T6507LP_Package.v" |
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// control signals |
localparam MEM_READ = 1'b0; |
/verilog/timescale.v
0,0 → 1,46
//////////////////////////////////////////////////////////////////////////// |
//// //// |
//// T6507LP IP Core //// |
//// //// |
//// This file is part of the T6507LP project //// |
//// http://www.opencores.org/cores/t6507lp/ //// |
//// //// |
//// Description //// |
//// 6507 FSM //// |
//// //// |
//// TODO: //// |
//// - Fix relative mode, bit 7 means negative //// |
//// - Comment the code //// |
//// //// |
//// Author(s): //// |
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com //// |
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com //// |
//// //// |
//////////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
//////////////////////////////////////////////////////////////////////////// |
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`timescale 1ns / 1ps |