OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk
    from Rev 128 to Rev 129
    ↔ Reverse comparison
  •

Rev 128 → Rev 129

/rtl/verilog/t6507lp_alu_wrapper.v
42,27 → 42,29
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "T6507LP_ALU.v"
 
module wrapper_alu();
module t6507lp_alu_wrapper();
parameter [3:0] DATA_SIZE = 4'd8;
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
 
// all inputs are regs
reg clk;
reg n_rst_i;
reg reset_n;
reg alu_enable;
reg alu_opcode;
reg alu_a;
reg [DATA_SIZE_:0] alu_opcode;
reg [DATA_SIZE_:0] alu_a;
// all outputs are wires
wire alu_result;
wire alu_status;
wire alu_x;
wire alu_y;
wire [DATA_SIZE_:0] alu_result;
wire [DATA_SIZE_:0] alu_status;
wire [DATA_SIZE_:0] alu_x;
wire [DATA_SIZE_:0] alu_y;
initial clk = 0;
always #10 clk <= ~clk;
 
//always #100 $write("working");
T6507LP_ALU T6507LP_ALU (
.clk_i (clk),
/fv/alu_sync.e
1,9 → 1,8
alu_sync.e;
<'
unit alu_sync_u {
clk: in event_port is instance;
keep bind(clk, external);
keep clk.hdl_path() == "clk";
keep clk.edge() == rise;
clk_p: in simple_port of bit is instance;
keep bind(clk_p, external);
event clk is rise (clk_p$) @sys.any;
};
'>
/fv/alu_agent.e
6,14 → 6,14
smp: alu_signal_map_u is instance;
mon: alu_mon_u is instance;
bfm: alu_bfm_u is instance;
sync: alu_sync_u is instance;
 
event main_clk;
keep bfm.rst == smp.rst;
 
keep bfm.agent == me;
keep bfm.reset_n == smp.reset_n;
keep bfm.alu_enable == smp.alu_enable;
keep bfm.alu_opcode == smp.alu_opcode;
//keep bfm.alu_a == smp.alu_a;
keep bfm.alu_a == smp.alu_a;
 
keep mon.alu_result == smp.alu_result;
keep mon.alu_status == smp.alu_status;
20,12 → 20,28
keep mon.alu_x == smp.alu_x;
keep mon.alu_y == smp.alu_y;
 
help() @ main_clk is {
out ("Hello World");
};
//on main_clk {
//while TRUE {
//counter = counter +1;
 
//if (counter == 37) {
//dut_error();
//}
//else {
//out("\n",counter);
//}
//}
//};
 
run() is also {
start help();
//start help();
};
};
 
extend alu_bfm_u {
agent: alu_agent_u;
event main_clk is only @agent.main_clk;
};
 
 
'>
/fv/alu_sigmap.e
1,9 → 1,9
alu_sig_map.e;
<'
unit alu_signal_map_u {
rst : out simple_port of bool is instance;
keep bind(rst, external);
keep rst.hdl_path() == "n_rst_i";
reset_n : out simple_port of bool is instance;
keep bind(reset_n, external);
keep reset_n.hdl_path() == "reset_n";
 
alu_enable : out simple_port of bool is instance;
keep bind(alu_enable, external);
/fv/alu_bfm.e
2,15 → 2,26
import alu_components.e;
 
unit alu_bfm_u {
//event clock_e;
//send_pkt(pkt: alu_packet_s) @clock_e is {
//Send in packet using the DUT protocol
//};
 
rst: out simple_port of bool;
reset_n: out simple_port of bool;
alu_enable: out simple_port of bool;
alu_opcode: out simple_port of byte;
//alu_a: out simple_port of byte;
alu_a: out simple_port of byte;
 
event main_clk;
 
on main_clk {
//Send in packet using the DUT protocol
var data : alu_input_s;
gen data;
 
emit data.T1_cover_event;
 
reset_n$ = data.reset_n;
alu_enable$ = data.alu_enable;
alu_opcode$ = data.alu_opcode;
alu_a$ = data.alu_a;
 
};
 
};
'>
/fv/alu_components.e
6,4 → 6,5
import alu_sigmap;
import alu_sync;
import alu_agent;
import alu_input;
'>
/fv/alu_env.e
3,10 → 3,11
unit alu_env_u {
agent: alu_agent_u is instance;
sync: alu_sync_u is instance;
teste: list of alu_input_s;
keep teste.size() == 10;
 
 
keep agent.env == me;
 
 
};
 
extend alu_agent_u {
16,5 → 17,6
 
extend sys {
env: alu_env_u is instance;
keep env.hdl_path() == "~/t6507lp_alu_wrapper";
};
'>

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.