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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk
    from Rev 184 to Rev 185
    ↔ Reverse comparison
  •

Rev 184 → Rev 185

/fv/cvrg/t6507lp/alu/icc.data Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/fv/cvrg/t6507lp/alu/icc.data
fv/cvrg/t6507lp/alu/icc.data Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: fv/cvrg/t6507lp/3f6bfca4_00000000.model =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: fv/cvrg/t6507lp/3f6bfca4_00000000.model =================================================================== --- fv/cvrg/t6507lp/3f6bfca4_00000000.model (nonexistent) +++ fv/cvrg/t6507lp/3f6bfca4_00000000.model (revision 185)
fv/cvrg/t6507lp/3f6bfca4_00000000.model Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: fv/alu_input.e =================================================================== --- fv/alu_input.e (revision 184) +++ fv/alu_input.e (revision 185) @@ -12,7 +12,7 @@ alu_opcode: valid_opcodes; alu_a: byte; - keep test_kind == RAND; +// keep test_kind == RAND; when REGULAR'test_kind alu_input_s { keep soft input_kind == select { @@ -46,7 +46,7 @@ event T1_cover_event; cover T1_cover_event is { - item input_kind using no_collect=TRUE; + item input_kind using no_collect=TRUE, ignore = (input_kind == ENABLED_RAND || input_kind == DISABLED_RAND); item alu_opcode using num_of_buckets=256, radix=HEX, no_collect=TRUE; cross input_kind, alu_opcode; //item alu_a; @@ -74,7 +74,7 @@ when DISABLED_RAND'input_kind alu_input_s { keep reset_n == TRUE; // remember this is active low - keep alu_enable == TRUE; + keep alu_enable == FALSE; keep alu_a in [0..255]; keep rand_op in [0..255]; };
/fv/alu_bfm.e
28,13 → 28,15
 
if (data.test_kind == REGULAR) {
emit data.T1_cover_event;
alu_opcode$ = data.rand_op;
alu_opcode$ = data.alu_opcode.as_a(byte);
}
else {
emit data.T2_cover_event;
alu_opcode$ = data.alu_opcode.as_a(byte);
};
alu_opcode$ = data.rand_op;
};
 
 
reset_n$ = data.reset_n;
alu_enable$ = data.alu_enable;
alu_a$ = data.alu_a;
/fv/alu_chk.e
56,12 → 56,12
reg_x = 0;
reg_y = 0;
reg_status = 8'b00100010;
reg_a = 0; // TODO: check this
reg_a = 0;
reg_result = 0;
}
else {
out ("CYCLE ", count_cycles, " COMPARE:");
print inst;
//out ("CYCLE ", count_cycles, " COMPARE:");
//print inst;
 
if (count_cycles == 99999) {
out("ENOUGH!");
79,7 → 79,52
case inst.input_kind {
ENABLED_VALID: {
//out("CYCLE ", count_cycles, ": executing and comparing");
execute();
execute(inst.alu_opcode);
 
if (reg_status[3:3] == 1) {
case inst.alu_opcode {
SBC_IMM: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ZPG: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ZPX: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ABS: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ABX: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ABY: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_IDX: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_IDY: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
};
};
};
RESET: {
reg_x = 0;
91,7 → 136,53
return;
};
ENABLED_RAND: {
execute();
execute(inst.rand_op.as_a(valid_opcodes));
if (reg_status[3:3] == 1) {
case inst.rand_op.as_a(valid_opcodes) {
SBC_IMM: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ZPG: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ZPX: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ABS: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ABX: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_ABY: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_IDX: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
SBC_IDY: {
reg_a = alu_result;
reg_result = alu_result;
reg_status = alu_status;
};
};
};
 
};
default: {
};
114,8 → 205,8
};
};
 
execute() is {
case inst.alu_opcode {
execute(opcode : valid_opcodes) is {
case opcode {
ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
ADC_ZPG: { exec_sum(); };
ADC_ZPX: { exec_sum(); };
257,12 → 348,12
reg_status[5:5] = 1; // this is always one
};
 
ROL_ACC: { exec_rot(TRUE, reg_a); };
ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
ROR_ACC: { exec_rot(FALSE, reg_a); };
ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
303,8 → 394,10
TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
TXA_IMP: { exec_transfer(reg_x, reg_a); };
TXS_IMP: { };
TYA_IMP: { exec_transfer(reg_y, reg_a); reg_result = reg_y; }; // A = Y
TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
 
// note: tya and txa do not update the result register
 
default: {
// all the random generated opcodes will fall here
}
322,6 → 415,8
var op1 : int;
var op2 : int;
 
warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
 
//out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
 
op1 = inst.alu_a[3:0];
349,7 → 444,7
};
reg_result[3:0] = op1;
reg_result[7:4] = op2;
reg_result[7:4] = op2;
}
else {
reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
370,25 → 465,24
 
};
 
exec_rot(left : bool, arg1 : *byte) is {
exec_rot(left : bool, arg1 : byte) is {
var oldcarry : bit;
 
if (left) {
oldcarry = reg_status[0:0];
reg_status[0:0] = arg1[7:7];
arg1 = arg1 << 1;
arg1[0:0] = oldcarry;
reg_result = arg1 << 1;
reg_result[0:0] = oldcarry;
}
else {
oldcarry = reg_status[0:0];
reg_status[0:0] = arg1[0:0];
arg1 = arg1 >> 1;
arg1[7:7] = oldcarry;
reg_result = arg1 >> 1;
reg_result[7:7] = oldcarry;
};
 
reg_result = arg1;
update_z(arg1);
update_n(arg1);
update_z(reg_result);
update_n(reg_result);
};
 
exec_or() is {

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