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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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  • This comparison shows the changes necessary to convert path
    /t6507lp/trunk
    from Rev 232 to Rev 233
    Reverse comparison

Rev 232 → Rev 233

/rtl/verilog/vga_controller.v
44,13 → 44,13
 
`include "timescale.v"
 
module vga_controller ( reset_n, clk_50, pixel, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS, clk_358);
module vga_controller ( reset_n, clk_50, pixel, read_data, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS, read_addr);
 
input reset_n;
input clk_50;
input [8:0] SW;
input [11:0] pixel;
input [4:0] vert_counter;
input [2:0] pixel;
input [2:0] read_data;
output reg [3:0] VGA_R;
output reg [3:0] VGA_G;
output reg [3:0] VGA_B;
57,7 → 57,7
output [9:0] LEDR;
output reg VGA_VS;
output reg VGA_HS;
input clk_358;
output reg [10:0] read_addr;
 
reg clk_25;
reg [9:0] hc;
65,6 → 65,8
reg vsenable;
wire vidon;
 
reg [11:0] vid_data;
 
assign LEDR[8:0] = SW;
assign LEDR[9] = reset_n;
 
141,47 → 143,57
end
end
 
reg [11:0] pixel_reg;
always @ (posedge clk_25) begin
//if (reset_n == 1'b0) begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
//end
//else
if (vidon == 1) begin
if (hc < 480 && vc < 400) begin
VGA_R[0] <= vid_data[0];
VGA_R[1] <= vid_data[1];
VGA_R[2] <= vid_data[2];
VGA_R[3] <= vid_data[3];
VGA_G[0] <= vid_data[4];
VGA_G[1] <= vid_data[5];
VGA_G[2] <= vid_data[6];
VGA_G[3] <= vid_data[7];
VGA_B[0] <= vid_data[8];
VGA_B[1] <= vid_data[9];
VGA_B[2] <= vid_data[10];
VGA_B[3] <= vid_data[11];
end
end
end
 
always @ (posedge clk_358 or negedge reset_n) begin
if (!reset_n) begin
pixel_reg <= 12'd0;
always @ (*) begin
if (hc < 400 && vc < 480) begin
read_addr = hc/10 + (vc/10)*48;
//case (read_data)
// default: begin
vid_data = 12'd10;
// end
//endcase
end
else begin
pixel_reg <= pixel;
read_addr = 10'd0;
vid_data = 12'b101010101010;
end
end
 
always @ (posedge clk_25) begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
 
if (vidon == 1) begin
VGA_R[0] <= pixel_reg[0];
VGA_R[1] <= pixel_reg[1];
VGA_R[2] <= pixel_reg[2];
VGA_R[3] <= pixel_reg[3];
VGA_G[0] <= pixel_reg[4];
VGA_G[1] <= pixel_reg[5];
VGA_G[2] <= pixel_reg[6];
VGA_G[3] <= pixel_reg[7];
VGA_B[0] <= pixel_reg[8];
VGA_B[1] <= pixel_reg[9];
VGA_B[2] <= pixel_reg[10];
VGA_B[3] <= pixel_reg[11];
end
end
 
assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
 
endmodule
/rtl/verilog/controller_test.v
44,33 → 44,37
 
`include "timescale.v"
 
module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter, clk_358);
module controller_test(reset_n, clk_50, pixel, write_addr, write_data, write_enable_n, clk_358);
 
input reset_n;
input clk_50;
output reg [11:0] pixel;
output reg [8:0] vert_counter;
output reg [7:0] hor_counter;
output reg [2:0] pixel;
output reg [10:0] write_addr;
output reg [2:0] write_data;
output reg write_enable_n;
output reg clk_358; // 3.58mhz
 
output reg clk_358; // 3.58mhz
reg [3:0] counter;
 
reg [3:0] red;
reg [3:0] green;
reg [3:0] blue;
//reg [3:0] red;
//reg [3:0] green;
//reg [3:0] blue;
 
reg [8:0] vert_counter;
reg [7:0] hor_counter;
 
always @ (posedge clk_50 or negedge reset_n) begin
if (reset_n == 1'b0) begin
clk_358 <= 1'b0;
counter <= 4'd0;
red <= 4'b1010;
green <= 4'b0001;
blue <= 4'b1110;
//red <= 4'b1010;
//green <= 4'b0001;
//blue <= 4'b1110;
end
else begin
red <= 4'b1010;
green <= 4'b0001;
blue <= 4'b1110;
//red <= 4'b1010;
//green <= 4'b0001;
//blue <= 4'b1110;
 
if (counter == 4'h6) begin
clk_358 <= !clk_358;
105,11 → 109,17
end
 
always @(*) begin // comb logic
if (hor_counter < 10) begin
pixel = {red, green, blue};
if (hor_counter < 68 || vert_counter < 40 || vert_counter > 232) begin
pixel = 3'd0;
write_enable_n = 1'b1;
write_addr = 0;
write_data = vert_counter[2:0];
end
else begin
pixel = {red, red, green};
pixel = 3'd4;
write_enable_n = 1'b0;
write_addr = (hor_counter - 68) + (vert_counter - 40)*160;
write_data = 3'd4;
end
end
 
/rtl/verilog/t6507lp_alu.v
68,7 → 68,7
 
reg [7:0] A;
reg [7:0] STATUS;
reg [7:0] result;
reg [9:0] result;
reg [7:0] op1;
reg [7:0] op2;
reg [7:0] bcdl;
108,25 → 108,25
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY,
SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP : begin
A <= result;
alu_result <= result;
A <= result[7:0];
alu_result <= result[7:0];
alu_status <= STATUS;
end
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP,
TSX_IMP, INX_IMP, DEX_IMP : begin
alu_x <= result;
alu_x <= result[7:0];
alu_status <= STATUS;
end
TXS_IMP : begin
alu_x <= result;
alu_x <= result[7:0];
end
TXA_IMP, TYA_IMP : begin
A <= result;
A <= result[7:0];
alu_status <= STATUS;
end
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP,
INY_IMP, DEY_IMP : begin
alu_y <= result;
alu_y <= result[7:0];
alu_status <= STATUS;
end
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY,
136,13 → 136,13
end
PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY,
STA_IDX, STA_IDY : begin
alu_result <= result;
alu_result <= result[7:0];
end
STX_ZPG, STX_ZPY, STX_ABS : begin
alu_x <= result;
alu_x <= result[7:0];
end
STY_ZPG, STY_ZPX, STY_ABS : begin
alu_y <= result;
alu_y <= result[7:0];
end
SEC_IMP : begin
alu_status[C] <= 1;
188,7 → 188,7
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX,
ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
begin
alu_result <= result;
alu_result <= result[7:0];
alu_status <= STATUS;
end
default : begin
201,7 → 201,8
if (alu_enable == 1) begin
op1 = A;
op2 = alu_a;
result = A;
result = A[7:0];
result[9:8] = 0;
STATUS[N] = alu_status[N];
STATUS[C] = alu_status[C];
STATUS[V] = alu_status[V];
221,7 → 222,7
case (alu_opcode)
// BIT - Bit Test
BIT_ZPG, BIT_ABS: begin
result = A & alu_a;
result[7:0] = A & alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
228,7 → 229,7
// PLA - Pull Accumulator
PLA_IMP : begin
result = alu_a;
result[7:0] = alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
239,7 → 240,7
// STA - Store Accumulator
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,
STA_ABY, STA_IDX, STA_IDY : begin
result = A;
result[7:0] = A;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
248,7 → 249,7
// TXA - Transfer X to Accumulator
// TXS - Transfer X to Stack pointer
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
result = alu_x;
result[7:0] = alu_x;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
256,7 → 257,7
// STY - Store Y Register
// TYA - Transfer Y to Accumulator
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
result = alu_y;
result[7:0] = alu_y;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
263,7 → 264,7
// INC - Increment memory
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
result = alu_a + 1;
result[7:0] = alu_a + 1;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
270,7 → 271,7
// INX - Increment X Register
INX_IMP: begin
result = alu_x + 1;
result[7:0] = alu_x + 1;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
277,7 → 278,7
// INY - Increment Y Register
INY_IMP : begin
result = alu_y + 1;
result[7:0] = alu_y + 1;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
284,7 → 285,7
// DEC - Decrement memory
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
result = alu_a - 1;
result[7:0] = alu_a - 1;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
291,7 → 292,7
// DEX - Decrement X register
DEX_IMP: begin
result = alu_x - 1;
result[7:0] = alu_x - 1;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
298,7 → 299,7
// DEY - Decrement Y Register
DEY_IMP: begin
result = alu_y - 1;
result[7:0] = alu_y - 1;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
307,10 → 308,11
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,
ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
if (!alu_status[D]) begin
{STATUS[C],result} = op1 + op2 + alu_status[C];
result = op1 + op2 + alu_status[C];
STATUS[N] = result[7];
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1 : 0;
STATUS[C] = result[8];
end
else begin
AL = op1[3:0] + op2[3:0] + alu_status[C];
333,7 → 335,7
bcdh2 = bcdh;
end
STATUS[C] = bcdh2[4] || bcdh2[5];
result = {bcdh2[3:0],bcdl[3:0]};
result[7:0] = {bcdh2[3:0],bcdl[3:0]};
end
end
340,7 → 342,7
// AND - Logical AND
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,
AND_IDY : begin
result = A & alu_a;
result[7:0] = A & alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
348,7 → 350,7
// CMP - Compare
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,
CMP_IDY : begin
result = A - alu_a;
result[7:0] = A - alu_a;
STATUS[C] = (A >= alu_a) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
357,7 → 359,7
// EOR - Exclusive OR
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,
EOR_IDX, EOR_IDY : begin
result = A ^ alu_a;
result[7:0] = A ^ alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
369,7 → 371,7
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX,
LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,
LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin
result = alu_a;
result[7:0] = alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
377,7 → 379,7
// ORA - Logical OR
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,
ORA_IDY : begin
result = A | alu_a;
result[7:0] = A | alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
387,9 → 389,9
SBC_IDY : begin
result = op1 - op2 - (1 - alu_status[C]);
STATUS[N] = result[7];
STATUS[V] = ((op1[7] == op2[7]) && (op1[7] == result[7])) ? 1 : 0;
STATUS[V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[C] = ~result[7];
STATUS[C] = ~(result[8] || result[9]);
if (alu_status[D]) begin
AL = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
AH = op1[7:4] - op2[7:4];
407,18 → 409,18
else begin
bcdh2 = bcdh;
end
result = {bcdh2[3:0],bcdl[3:0]};
result[7:0] = {bcdh2[3:0],bcdl[3:0]};
end
end
// ASL - Arithmetic Shift Left
ASL_ACC : begin
{STATUS[C],result} = {A,1'b0};
{STATUS[C],result[7:0]} = {A,1'b0};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
{STATUS[C],result} = {alu_a,1'b0};
{STATUS[C],result[7:0]} = {alu_a,1'b0};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
425,12 → 427,12
// LSR - Logical Shift Right
LSR_ACC: begin
{result,STATUS[C]} = {1'b0,A};
{result[7:0],STATUS[C]} = {1'b0,A};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
{result,STATUS[C]} = {1'b0,alu_a};
{result[7:0],STATUS[C]} = {1'b0,alu_a};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
437,12 → 439,12
// ROL - Rotate Left
ROL_ACC : begin
{STATUS[C],result} = {A,alu_status[C]};
{STATUS[C],result[7:0]} = {A,alu_status[C]};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
{STATUS[C],result} = {alu_a,alu_status[C]};
{STATUS[C],result[7:0]} = {alu_a,alu_status[C]};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
449,12 → 451,12
// ROR - Rotate Right
ROR_ACC : begin
{result,STATUS[C]} = {alu_status[C],A};
{result[7:0],STATUS[C]} = {alu_status[C],A};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
{result, STATUS[C]} = {alu_status[C], alu_a};
{result[7:0], STATUS[C]} = {alu_status[C], alu_a};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
end
461,7 → 463,7
// CPX - Compare X Register
CPX_IMM, CPX_ZPG, CPX_ABS : begin
result = alu_x - alu_a;
result[7:0] = alu_x - alu_a;
STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
469,7 → 471,7
// CPY - Compare Y Register
CPY_IMM, CPY_ZPG, CPY_ABS : begin
result = alu_y - alu_a;
result[7:0] = alu_y - alu_a;
STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[N] = result[7];
/rtl/verilog/test_top.v
56,8 → 56,13
output VGA_VS;
output VGA_HS;
 
wire [11:0] pixel;
wire [8:0] vert_counter;
wire [2:0] pixel;
wire [10:0] read_addr;
wire [10:0] write_addr;
wire [2:0] read_data;
wire [2:0] write_data;
wire write_enable_n;
wire clk_358;
 
vga_controller vga_controller (
.reset_n(reset_n),
70,8 → 75,8
.LEDR(LEDR),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.vert_counter(vert_counter),
.clk_358(clk_358)
.read_addr(read_addr),
.read_data(read_data)
);
 
controller_test controller_test (
78,8 → 83,20
.reset_n(reset_n),
.clk_50(clk_50),
.pixel(pixel),
.vert_counter(vert_counter),
.write_addr(write_addr),
.write_data(write_data),
.write_enable_n(write_enable_n),
.clk_358(clk_358)
);
 
video_mem video_mem (
.clk_358(clk_358),
.reset_n(reset_n),
.write_addr(write_addr),
.write_enable_n(write_enable_n),
.read_addr(read_addr),
.write_data(write_data),
.read_data(read_data)
);
 
endmodule
/fv/alu_input.e
12,7 → 12,7
alu_opcode: valid_opcodes;
alu_a: byte;
 
// keep test_kind == RAND;
keep test_kind == REGULAR;
when REGULAR'test_kind alu_input_s {
keep soft input_kind == select {
/fv/alu_chk.e
411,7 → 411,7
};
 
exec_sub() is {
if (reg_status[3:3] == 1) {
if (reg_status[3:3] == 1) { // decimal
var op1 : int;
var op2 : int;
 
445,24 → 445,40
reg_result[3:0] = op1;
reg_result[7:4] = op2;
 
update_n(reg_result);
update_z(reg_result);
update_v(reg_a, inst.alu_a, reg_result);
reg_a = reg_result;
}
else {
reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
if (reg_result[7:7] == 1) {
var temp: int;
 
temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
 
reg_status[7:7] = temp[7:7]; // N
print (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
if (reg_result == 0) {
reg_status[1:1] = 1; // Z
} else {
reg_status[1:1] = 0; // Z
};
 
reg_a = temp.as_a(byte);
 
print (temp & 0xff00);
print (temp & 0xff00) != 0x0000;
 
if ( (temp & 0xff00) != 0x0000 ) {
reg_status[0:0] = 0;
} else {
reg_status[0:0] = 1;
}
else {
reg_status[0:0] = 1;
};
 
};
 
update_z(reg_result);
update_n(reg_result);
update_v(reg_a, inst.alu_a, reg_result);
reg_a = reg_result;
 
};
 
exec_rot(left : bool, arg1 : byte) is {
611,12 → 627,13
update_v(reg_a, inst.alu_a, reg_result);
reg_a = reg_result;
}
else {
else { // stella checked
reg_result = reg_a + inst.alu_a + reg_status[0:0];
update_c(reg_a, inst.alu_a, reg_status[0:0]);
update_n(reg_result);
update_v(reg_a, inst.alu_a, reg_result);
update_z(reg_result);
update_n(reg_result);
update_c(reg_a, inst.alu_a, reg_status[0:0]);
reg_a = reg_result;
};
};

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