OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path
    /t6507lp
    from Rev 183 to Rev 184
    Reverse comparison

Rev 183 → Rev 184

/trunk/rtl/verilog/t6507lp_alu.v
102,7 → 102,7
EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP :
begin
A <= result;
alu_result <= result;
119,6 → 119,11
//X <= result;
alu_x <= result;
end
TXA_IMP, TYA_IMP :
begin
A <= result;
alu_status <= STATUS;
end
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
begin
//Y <= result;
/trunk/rtl/verilog/t6507lp_alu_tb.v
203,6 → 203,7
alu_status_expected[D] = 0;
check;
 
/*
// SBC BCD
// LDA
alu_a = 0;
222,7 → 223,7
alu_status_expected[D] = 1;
check;
 
// ADC
// SBC
alu_opcode = SBC_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
235,24 → 236,6
AH = alu_a[7:4];
BL = ~alu_result_expected[3:0];
BH = ~alu_result_expected[7:4];
/*
if (AL > 9) begin
AL = AL - 10;
AH = AH + 1;
end
if ( AH > 9 ) begin
AH = AH - 10;
C_temp = 1;
end
if (BL > 9) begin
BL = BL - 10;
BH = BH + 1;
end
if ( BH > 9 ) begin
BH = BH - 10;
C_temp = 1;
end
*/
//$display("AL = %h BL = %h", AL, BL, );
temp1 = AL + BL + alu_status_expected[C];
294,7 → 277,8
@(negedge clk);
alu_status_expected[D] = 0;
check;
*/
 
// ASL
alu_opcode = ASL_ABS;
for (i = 0; i < 1000; i = i + 1)

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