OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /t6507lp
    from Rev 193 to Rev 194
    ↔ Reverse comparison
  •

Rev 193 → Rev 194

/trunk/rtl/verilog/t6532.v
58,25 → 58,50
input [ADDR_SIZE_:0] address;
inout [DATA_SIZE_:0] data;
 
wire [DATA_SIZE_:0] ram [127:0];
wire [DATA_SIZE_:0] io_ports [3:0]; // porta, portaddr, portb, portbddr
reg [DATA_SIZE_:0] ram [127:0];
reg [DATA_SIZE_:0] port_a;
reg [DATA_SIZE_:0] port_b;
reg [DATA_SIZE_:0] ddra;
wire [DATA_SIZE_:0] ddrb;
 
reg [DATA_SIZE_:0] data_drv;
 
assign data = (rw_mem) ? 8'bZ: data_drv; // if i am writing the bus receives the data from cpu
assign data = (rw_mem) ? 8'bZ: data_drv; // if i am writing the bus receives the data from cpu, else local data.
 
t6532_io t6532_io (
.clk (clk),
.io_lines (io_lines),
.ddra (io_ports[1]),
.A (io_ports[0]),
.B (io_ports[2])
);
always @(clk) begin
port_b[0] <= ~io_lines[0]; // these two are not actually switches
port_b[1] <= ~io_lines[1];
if (io_lines[3]) begin // these are.
port_b[3] <= !port_b[3];
end
if (io_lines[6]) begin
port_b[6] <= !port_b[6];
end
if (io_lines[7]) begin
port_b[7] <= !port_b[7];
end
 
always @(clk) begin
port_a[0] <= (ddra[0] == 0) ? io_lines[8] : port_a[0];
port_a[1] <= (ddra[1] == 0) ? io_lines[9] : port_a[1];
port_a[2] <= (ddra[2] == 0) ? io_lines[10] : port_a[2];
port_a[3] <= (ddra[3] == 0) ? io_lines[11] : port_a[3];
port_a[4] <= (ddra[4] == 0) ? io_lines[12] : port_a[4];
port_a[5] <= (ddra[5] == 0) ? io_lines[13] : port_a[5];
port_a[6] <= (ddra[6] == 0) ? io_lines[14] : port_a[6];
port_a[7] <= (ddra[7] == 0) ? io_lines[15] : port_a[7];
 
if (enable && rw_mem) begin
case (address)
8'h80: data_drv <= io_ports[0];
8'h80: data_drv = port_a;
8'h81: data_drv = ddra;
8'h82: data_drv = port_b;
8'h83: data_drv = ddrb;
8'h84: ;
8'h94: ;
8'h95: ;
8'h96: ;
8'h97: ;
default: ;
endcase
end
83,7 → 108,8
end
 
always @(*) begin
io_ports [3] = 8'h00; // portb ddr is always input
io_ports[3] = 8'h00; // portb ddr is always input
io_ports[1] = ddra;
end
 
// io
/trunk/rtl/verilog/t6507lp_fsm.v
143,7 → 143,9
reg php;
reg pla;
reg plp;
reg jsr;
reg jsr;
reg tsx;
reg txs;
 
wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
assign next_pc = pc + 13'b0000000000001;
204,7 → 206,7
if (reset_n == 1'b0) begin
// all registers must assume default values
pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
sp <= 9'b000000000; // the default is 'h100
sp <= 9'b111111111; // the default is 'h1FF
ir <= 8'h00;
temp_addr <= 13'h0000;
temp_data <= 8'h00;
221,7 → 223,7
case (state)
RESET: begin // The processor was reset
rst_counter <= rst_counter + 1;
sp <= 9'b100000000; // this prevents flipflops with different drivers
//sp <= 9'b111111111; // this prevents flipflops with different drivers
//$write("under reset");
end
/*
242,7 → 244,12
if (accumulator || implied) begin
pc <= pc; // is this better?
address <= pc;
mem_rw <= MEM_READ;
mem_rw <= MEM_READ;
if (txs) begin
sp[7:0] <= data_in;
end
//alu_a
end
else if (immediate || relative) begin
pc <= next_pc;
601,7 → 608,11
if (accumulator || implied) begin
alu_opcode = ir;
alu_enable = 1'b1;
next_state = FETCH_OP;
next_state = FETCH_OP;
if (tsx) begin
alu_a = sp[7:0];
end
end
else if (immediate) begin
next_state = FETCH_OP_CALC_PARAM;
880,10 → 891,12
pla = 1'b0;
plp = 1'b0;
jsr = 1'b0;
tsx = 1'b0;
txs = 1'b0;
 
case (ir)
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP,
SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TXA_IMP, TYA_IMP: begin
implied = 1'b1;
end
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
1045,6 → 1058,12
JSR_ABS: begin
jsr = 1'b1;
end
TSX_IMP: begin
tsx = 1'b1;
end
TXS_IMP: begin
txs = 1'b1;
end
default: begin
//$write("state : %b", state);
if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.