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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path
    /t6507lp
    from Rev 231 to Rev 232
    Reverse comparison

Rev 231 → Rev 232

/trunk/rtl/verilog/vga_controller.v
44,7 → 44,7
 
`include "timescale.v"
 
module vga_controller ( reset_n, clk_50, pixel, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
module vga_controller ( reset_n, clk_50, pixel, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS, clk_358);
 
input reset_n;
input clk_50;
57,6 → 57,7
output [9:0] LEDR;
output reg VGA_VS;
output reg VGA_HS;
input clk_358;
 
reg clk_25;
reg [9:0] hc;
140,8 → 141,18
end
end
 
always @ (posedge clk_25)
begin
reg [11:0] pixel_reg;
 
always @ (posedge clk_358 or negedge reset_n) begin
if (!reset_n) begin
pixel_reg <= 12'd0;
end
else begin
pixel_reg <= pixel;
end
end
 
always @ (posedge clk_25) begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
154,19 → 165,20
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
 
if (vidon == 1) begin
VGA_R[0] <= pixel[0];
VGA_R[1] <= pixel[1];
VGA_R[2] <= pixel[2];
VGA_R[3] <= pixel[3];
VGA_G[0] <= pixel[4];
VGA_G[1] <= pixel[5];
VGA_G[2] <= pixel[6];
VGA_G[3] <= pixel[7];
VGA_B[0] <= pixel[8];
VGA_B[1] <= pixel[9];
VGA_B[2] <= pixel[10];
VGA_B[3] <= pixel[11];
VGA_R[0] <= pixel_reg[0];
VGA_R[1] <= pixel_reg[1];
VGA_R[2] <= pixel_reg[2];
VGA_R[3] <= pixel_reg[3];
VGA_G[0] <= pixel_reg[4];
VGA_G[1] <= pixel_reg[5];
VGA_G[2] <= pixel_reg[6];
VGA_G[3] <= pixel_reg[7];
VGA_B[0] <= pixel_reg[8];
VGA_B[1] <= pixel_reg[9];
VGA_B[2] <= pixel_reg[10];
VGA_B[3] <= pixel_reg[11];
end
end
 
/trunk/rtl/verilog/controller_test.v
44,7 → 44,7
 
`include "timescale.v"
 
module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter);
module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter, clk_358);
 
input reset_n;
input clk_50;
52,7 → 52,7
output reg [8:0] vert_counter;
output reg [7:0] hor_counter;
 
reg clk_358; // 3.58mhz
output reg clk_358; // 3.58mhz
reg [3:0] counter;
 
reg [3:0] red;
82,8 → 82,6
end
end
 
 
 
always @ (posedge clk_358 or negedge reset_n) begin
if (reset_n == 1'b0) begin
hor_counter <= 8'd0;
107,7 → 105,12
end
 
always @(*) begin // comb logic
pixel = {red, green, blue};
if (hor_counter < 10) begin
pixel = {red, green, blue};
end
else begin
pixel = {red, red, green};
end
end
 
endmodule
/trunk/rtl/verilog/test_top.v
70,7 → 70,8
.LEDR(LEDR),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.vert_counter(vert_counter)
.vert_counter(vert_counter),
.clk_358(clk_358)
);
 
controller_test controller_test (
77,7 → 78,8
.reset_n(reset_n),
.clk_50(clk_50),
.pixel(pixel),
.vert_counter(vert_counter)
.vert_counter(vert_counter),
.clk_358(clk_358)
);
 
endmodule

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