OpenCores
URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart2bus_testbench/trunk/tb/agent/sequence
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/uart_sequence.svh
1,27 → 1,31
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------
//
// UART2BUS VERIFICATION
//
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------
// CREATOR : HANY SALAH
// PROJECT : UART2BUS UVM TEST BENCH
// UNIT : SEQUENCE
//-----------------------------------------------------------------------------
// TITLE : UART Sequence
// DESCRIPTION: This
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------
// TITLE : UART SEQUENCE
// DESCRIPTION: THIS FILE INCLUDES THE ALL SEQUENCES THAT WOULD BE FORCED INTO DUT. THE SEQUENCES
// MENTIONED BELOW IS IDENTIFIED IN THE MANNER RELATED TO THE TEST PLAN SECTION IN
// THE DOCUMENT; IT IS IDENTIFIED USING TWO TERMS; SUBSECTION AND ITEM INSIDE SUB-
// SECTION.
//-------------------------------------------------------------------------------------------------
// LOG DETAILS
//-------------
// VERSION NAME DATE DESCRIPTION
// 1 HANY SALAH 01012016 FILE CREATION
// 2 HANY SALAH 02012016 ADD REST OF TESTS
//-----------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
// CREATOR'S PERMISSION
//-----------------------------------------------------------------------------
// 3 HANY SALAH 29012016 INSERT WRONG MODE IN BOTH BINARY AND TEXT COMMUNICATION
// MODES
// 4 HANY SALAH 09022016 REFINE BLOCK DESCRIPTION
//-------------------------------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
//-------------------------------------------------------------------------------------------------
 
 
// Base Sequence Class that hold the common attributes to all sequences
class uart_base_sequence extends uvm_sequence #(uart_transaction);
35,11 → 39,11
endfunction:new
endclass:uart_base_sequence
 
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
//
// WRITE IN TEXT MODE
// WRITE IN TEXT MODE
//
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
// 1.1 Apply UART write request using capital W
class seq_1p1 extends uart_base_sequence;
271,7 → 275,7
length_data == 1;
_eoltype != wrong_eol;
_command == write;
address == 4'hFFFF;
address == 16'hFFFF;
_reqinc == no;
_arbit == accept;
};
325,7 → 329,7
length_data == 1;
_eoltype != wrong_eol;
_command == write;
_data [0] == 2'hff;
_data [0] == 8'hff;
_reqinc == no;
_arbit == accept;
} ;
334,11 → 338,62
endclass:seq_1p11
 
 
//-------------------------------------------------------
// 1.12 Apply UART write request using different EOL character.
class seq_1p12 extends uart_base_sequence;
`uvm_object_utils(seq_1p12)
 
function new (string name = "seq_1p12");
super.new(name);
endfunction:new
 
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == text;
_spacetype1 != wrong_space;
_spacetype2 != wrong_space;
length_data == 1;
_eoltype == wrong_eol;
_command == write;
_reqinc == no;
_arbit == accept;
} ;
finish_item(trans);
endtask:body
endclass:seq_1p12
 
 
// 1.13 Apply UART Write request using wrong prefix
class seq_1p13 extends uart_base_sequence;
`uvm_object_utils(seq_1p13)
 
function new (string name = "seq_1p13");
super.new(name);
endfunction:new
 
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == wrong_mode_text;
_spacetype1 != wrong_space;
_spacetype2 != wrong_space;
length_data == 1;
_eoltype != wrong_eol;
_command == write;
_reqinc == no;
_arbit == accept;
} ;
finish_item(trans);
endtask:body
endclass:seq_1p13
 
//-------------------------------------------------------------------------------------------------
//
// READ IN TEXT MODE
// READ IN TEXT MODE
//
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
// 2.1 Apply UART read request using capital R
class seq_2p1 extends uart_base_sequence;
570,7 → 625,7
length_data == 1;
_eoltype != wrong_eol;
_command == read;
address == 4'hFFFF;
address == 16'hFFFF;
_reqinc == no;
_arbit == accept;
} ;
624,7 → 679,7
length_data == 1;
_eoltype != wrong_eol;
_command == read;
_data [0] == 2'hff;
_data [0] == 8'hff;
_reqinc == no;
_arbit == accept;
} ;
632,11 → 687,63
endtask:body
endclass:seq_2p11
 
//-------------------------------------------------------
 
// 2.12 Apply UART read request using different EOL character.
class seq_2p12 extends uart_base_sequence;
`uvm_object_utils(seq_2p12)
 
function new (string name = "seq_2p12");
super.new(name);
endfunction:new
 
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == text;
_spacetype1 != wrong_space;
_spacetype2 != wrong_space;
length_data == 1;
_eoltype == wrong_eol;
_command == read;
_reqinc == no;
_arbit == accept;
} ;
finish_item(trans);
endtask:body
endclass:seq_2p12
 
 
// 2.13 Apply UART Read request using wrong prefix
class seq_2p13 extends uart_base_sequence;
`uvm_object_utils(seq_2p13)
 
function new (string name = "seq_2p13");
super.new(name);
endfunction:new
 
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == wrong_mode_text;
_spacetype1 != wrong_space;
_spacetype2 != wrong_space;
length_data == 1;
_eoltype != wrong_eol;
_command == read;
_reqinc == no;
_arbit == accept;
} ;
finish_item(trans);
endtask:body
endclass:seq_2p13
 
//-------------------------------------------------------------------------------------------------
//
// NOP IN COMMAND MODE
// NOP IN COMMAND MODE
//
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
// 3.1 Apply UART NOP command with acknowledge request and right command
// mode prefix
657,6 → 764,7
_arbit == accept;
_reqack == yes;
} ;
$display("reached here sequence @time=%0t ,, _mode = %p",$time,trans._mode);
finish_item(trans);
endtask:body
endclass:seq_3p1
674,9 → 782,9
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == wrong_mode;
_mode == wrong_mode_bin;
_command == nop;
address[15:7] != 2'h00;
address != 16'h0;
(length_data > 1) -> (_reqinc == yes);
_arbit == accept;
_reqack == yes;
754,9 → 862,9
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == wrong_mode;
_mode == wrong_mode_bin;
_command == nop;
address[15:7] != 2'h00;
address[15:7] != 8'h00;
(length_data > 1) -> (_reqinc == yes);
_arbit == accept;
_reqack == no;
798,11 → 906,11
endtask:body
endclass:seq_4p3
 
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
//
// WRITE IN COMMAND MODE
// WRITE IN COMMAND MODE
//
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
// 5.1 Apply UART write command with wrong prefix.
class seq_5p1 extends uart_base_sequence;
816,9 → 924,9
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == wrong_mode;
_mode == wrong_mode_bin;
_command == write;
address[15:7] != 2'h00;
address[15:7] != 8'h00;
(length_data > 1) -> (_reqinc == yes);
_arbit == accept;
} ;
924,7 → 1032,7
trans.randomize() with {
_mode == binary;
_command == write;
address == 4'hffff;
address == 16'hFFFF;
(length_data > 1) -> (_reqinc == yes);
_arbit == accept;
} ;
1042,12 → 1150,11
endtask:body
endclass:seq_5p10
 
 
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
//
// READ IN COMMAND MODE
// READ IN COMMAND MODE
//
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
// 6.1 Apply UART read command with wrong prefix.
class seq_6p1 extends uart_base_sequence;
1061,9 → 1168,9
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == wrong_mode;
_mode == wrong_mode_bin;
_command == read;
address[15:7] != 2'h00;
address[15:7] != 8'h00;
(length_data > 1) -> (_reqinc == yes);
_arbit == accept;
} ;
1169,7 → 1276,7
trans.randomize() with {
_mode == binary;
_command == read;
address == 4'hffff;
address == 16'hFFFF;
(length_data > 1) -> (_reqinc == yes);
_arbit == accept;
} ;
1287,11 → 1394,11
endtask:body
endclass:seq_6p10
 
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
//
// INTERNAL BUS
// INTERNAL BUS
//
//-------------------------------------------------------
//-------------------------------------------------------------------------------------------------
 
// 7.1 Apply UART read or write commands and give the UART the bus grant.
class seq_7p1 extends uart_base_sequence;
1335,4 → 1442,54
} ;
finish_item(trans);
endtask:body
endclass:seq_7p2
endclass:seq_7p2
 
//-------------------------------------------------------------------------------------------------
//
// INVALID COMMANDS
//
//-------------------------------------------------------------------------------------------------
 
// 8.1 Apply Invalid UART command in form of write binary command.
class seq_8p1 extends uart_base_sequence;
 
`uvm_object_utils(seq_8p1)
 
function new (string name="seq_8p1");
super.new(name);
endfunction:new
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == binary;
_command == invalid_write;
(length_data > 1) -> (_reqinc == yes);
_arbit == accept;
_reqinc == yes;
} ;
finish_item(trans);
endtask:body
endclass:seq_8p1
 
// 8.2 Apply Invalid UART command in form of read binary command.
class seq_8p2 extends uart_base_sequence;
 
`uvm_object_utils(seq_8p2)
 
function new (string name="seq_8p2");
super.new(name);
endfunction:new
virtual task body ();
start_item(trans);
trans.randomize() with {
_mode == binary;
_command == invalid_read;
(length_data > 1) -> (_reqinc == yes);
_arbit == declain;
_reqinc == yes;
} ;
finish_item(trans);
endtask:body
endclass:seq_8p2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.