OpenCores
URL https://opencores.org/ocsvn/uart_plb/uart_plb/trunk

Subversion Repositories uart_plb

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Rev 2 → Rev 3

/uart_plb/trunk/firmware/platform/system.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
uart_plb/trunk/firmware/platform/system.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: uart_plb/trunk/firmware/platform/system.xml =================================================================== --- uart_plb/trunk/firmware/platform/system.xml (nonexistent) +++ uart_plb/trunk/firmware/platform/system.xml (revision 3) @@ -0,0 +1,4548 @@ + + + + + + + + + + + + + + + + + MicroBlaze + The MicroBlaze 32 bit soft processor + + + + + + + + + + + + + Enable Fault Tolerance Support + + + + + Select implementation to optimize area (with lower instruction throughput) + + + + Select Bus Interfaces + + + Select Stream Interfaces + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Enable Additional Machine Status Register Instructions + + + Enable Pattern Comparator + + + Enable Barrel Shifter + + + Enable Integer Divider + + + Enable Integer Multiplier + + + Enable Floating Point Unit + + + Enable Unaligned Data Exception + + + Enable Illegal Instruction Exception + + + Enable Instruction-side AXI Exception + + + Enable Data-side AXI Exception + + + Enable Instruction-side PLB Exception + + + Enable Data-side PLB Exception + + + Enable Integer Divide Exception + + + Enable Floating Point Unit Exceptions + + + Enable Stream Exception + + + <qt>Enable stack protection</qt> + + + Specifies Processor Version Register + + + Specify USER1 Bits in Processor Version Register + + + Specify USER2 Bits in Processor Version Registers + + + Enable MicroBlaze Debug Module Interface + + + Number of PC Breakpoints + + + Number of Read Address Watchpoints + + + Number of Write Address Watchpoints + + + Sense Interrupt on Edge vs. Level + + + Sense Interrupt on Rising vs. Falling Edge + + + Specify Reset Value for Select MSR Bits + + + <qt>Generate Illegal Instruction Exception for NULL Instruction</qt> + + + Number of Stream Links + + + + Enable Additional Stream Instructions + + + + + + + + + + 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Buffer Size + + + Enable Access to Memory Management Special Registers + + + Number of Memory Protection Zones + + + Privileged Instructions + + + + + + Enable Branch Target Cache + + + Branch Target Cache Size + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature' + + + + + + + Number of PLB Masters + + + Number of PLB Slaves + + + PLB Master ID Bus Width + + + PLB Address Bus Width + + + PLB Data Bus Width + + + Include DCR Interface and Error Registers + + + Base Address + + + High Address + + + DCR Address Bus Width + + + DCR Data Bus Width + + + External Reset Active High + + + IRQ Active State + + + <qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt> + + + Enable Address Pipelining Type + + + Device Family + + + Optimize PLB for Point-to-point Topology + + + Selects the Arbitration Scheme + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Master ID Bus Width of PLB + + + Number of PLB Masters + + + PLB Slave is Capable of Bursts + + + Native Data Bus Width of PLB Slave + + + Frequency of PLB Slave + + + S_AXI_CTRL Clock Frequency + + + S_AXI_CTRL Base Address + + + S_AXI_CTRL High Address + + + S_AXI_CTRL Address Width + + + S_AXI_CTRL Data Width + + + S_AXI_CTRL Protocol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Block RAM (BRAM) Block + The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. + + + + + + + Size of BRAM(s) in Bytes + + + Data Width of Port A and B + + + Address Width of Port A and B + + + Number of Byte Write Enables + + + Device Family + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS UART (Lite) + Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus. + + + + + + + Device Family + + + Clock Frequency of PLB Slave + + + Base Address + + + High Address + + + PLB Address Bus Width + + + PLB Data Bus Width + + + PLB Slave Uses P2P Topology + + + Master ID Bus Width of PLB + + + Number of PLB Masters + + + PLB Slave is Capable of Bursts + + + Native Data Bus Width of PLB Slave + + + UART Lite Baud Rate + Baud Rate + + + Number of Data Bits in a Serial Frame + Data Bits + + + Use Parity + + + Parity Type + + + + + Serial Data In + + + Serial Data Out + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Clock 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Low Peripheral Reset Registered Outputs + + + Device Family + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS Interrupt Controller + intc core attached to the PLBV46 + + + + + + + Device Family + + + Base Address + + + High Address + + + PLB Address Bus Width + + + PLB Data Bus Width + + + PLB Slave Uses P2P Topology + + + Number of PLB Masters + + + Master ID Bus Width of PLB + + + Native Data Bus Width of PLB Slave + + + PLB Slave is Capable of Bursts + + + Number of Interrupt Inputs + + + Type of Interrupt for Each Input + + + Type of Each Edge Senstive Interrupt + + + Type of Each Level Sensitive Interrupt + + + Support IPR + + + Support SIE + + + Support CIE + + + Support IVR + + + IRQ Output Use Level + + + The Sense of IRQ Output + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file Index: uart_plb/trunk/firmware/platform/system_bd.bmm =================================================================== --- uart_plb/trunk/firmware/platform/system_bd.bmm (nonexistent) +++ uart_plb/trunk/firmware/platform/system_bd.bmm (revision 3) @@ -0,0 +1,32 @@ +// BMM LOC annotation file. +// +// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010 +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. + + +/////////////////////////////////////////////////////////////////////////////// +// +// Processor 'microblaze_0', ID 100, memory map. +// +/////////////////////////////////////////////////////////////////////////////// + +ADDRESS_MAP microblaze_0 MICROBLAZE 100 + + + /////////////////////////////////////////////////////////////////////////////// + // + // Processor 'microblaze_0' address space 'lmb_bram_combined' 0x00000000:0x00001FFF (8 KBytes). + // + /////////////////////////////////////////////////////////////////////////////// + + ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x00001FFF] + BUS_BLOCK + lmb_bram/lmb_bram/ramb16_s9_s9_0 [31:24] PLACED = X1Y11; + lmb_bram/lmb_bram/ramb16_s9_s9_1 [23:16] PLACED = X1Y10; + lmb_bram/lmb_bram/ramb16_s9_s9_2 [15:8] PLACED = X1Y13; + lmb_bram/lmb_bram/ramb16_s9_s9_3 [7:0] PLACED = X1Y12; + END_BUS_BLOCK; + END_ADDRESS_SPACE; + +END_ADDRESS_MAP; + Index: uart_plb/trunk/firmware/platform/.project =================================================================== --- uart_plb/trunk/firmware/platform/.project (nonexistent) +++ uart_plb/trunk/firmware/platform/.project (revision 3) @@ -0,0 +1,12 @@ + + + platform + + + + + + + com.xilinx.sdk.hw.HwProject + + Index: uart_plb/trunk/firmware/uart_plb_test/.project =================================================================== --- uart_plb/trunk/firmware/uart_plb_test/.project (nonexistent) +++ uart_plb/trunk/firmware/uart_plb_test/.project (revision 3) @@ -0,0 +1,82 @@ + + + uart_plb_test + standalone_bsp_0 - microblaze_0 + + standalone_bsp_0 + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/uart_plb_test/Debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + Index: uart_plb/trunk/firmware/uart_plb_test/.cproject =================================================================== --- uart_plb/trunk/firmware/uart_plb_test/.cproject (nonexistent) +++ uart_plb/trunk/firmware/uart_plb_test/.cproject (revision 3) @@ -0,0 +1,1402 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: uart_plb/trunk/firmware/uart_plb_test/src/platform_config.h =================================================================== --- uart_plb/trunk/firmware/uart_plb_test/src/platform_config.h (nonexistent) +++ uart_plb/trunk/firmware/uart_plb_test/src/platform_config.h (revision 3) @@ -0,0 +1,8 @@ +#ifndef __PLATFORM_CONFIG_H_ +#define __PLATFORM_CONFIG_H_ + +#ifdef __PPC__ +#define CACHEABLE_REGION_MASK 0x80000000 +#endif + +#endif Index: uart_plb/trunk/firmware/uart_plb_test/src/platform.c =================================================================== --- uart_plb/trunk/firmware/uart_plb_test/src/platform.c (nonexistent) +++ uart_plb/trunk/firmware/uart_plb_test/src/platform.c (revision 3) @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2010 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include "xparameters.h" +#include "xil_cache.h" + +#include "platform_config.h" + +#ifdef STDOUT_IS_16550 +#include "xuartns550_l.h" +#endif + +void +enable_caches() +{ +#ifdef __PPC__ + Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK); + Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK); +#elif __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheEnable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheEnable(); +#endif +#endif +} + +void +disable_caches() +{ + Xil_DCacheDisable(); + Xil_ICacheDisable(); +} + +void +init_platform() +{ + enable_caches(); + + /* if we have a uart 16550, then that needs to be initialized */ +#ifdef STDOUT_IS_16550 + XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600); + XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); +#endif +} + +void +cleanup_platform() +{ + disable_caches(); +} Index: uart_plb/trunk/firmware/uart_plb_test/src/uart_plb_test.c =================================================================== --- uart_plb/trunk/firmware/uart_plb_test/src/uart_plb_test.c (nonexistent) +++ uart_plb/trunk/firmware/uart_plb_test/src/uart_plb_test.c (revision 3) @@ -0,0 +1,35 @@ +/* + * helloworld.c: simple uart test application + */ + +#include +#include "platform.h" +#include "xparameters.h" + +int main() +{ + unsigned int data; + + init_platform(); + + print("Hello World\n\r"); + + data = 0x000019; // baudrate 115200Hz @ 50MHz clock + *((volatile int *)(XPAR_UART_PLB_0_BASEADDR + 0x10)) = data; + data = 3; // reset RX FIFO & TX FIFO + *((volatile int *)(XPAR_UART_PLB_0_BASEADDR + 0x08)) = data; + data = 0; // enable RX FIFO & TX FIFO + *((volatile int *)(XPAR_UART_PLB_0_BASEADDR + 0x08)) = data; + while(1) { + data = *((volatile int *)(XPAR_UART_PLB_0_BASEADDR + 0x0C)); + if (data & 0x3000000) + { + data = *((volatile int *)(XPAR_UART_PLB_0_BASEADDR)); + *((volatile int *)(XPAR_UARTLITE_1_BASEADDR + 0x04)) = data; + } + } + + cleanup_platform(); + + return 0; +} Index: uart_plb/trunk/firmware/uart_plb_test/src/platform.h =================================================================== --- uart_plb/trunk/firmware/uart_plb_test/src/platform.h (nonexistent) +++ uart_plb/trunk/firmware/uart_plb_test/src/platform.h (revision 3) @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2008 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __PLATFORM_H_ +#define __PLATFORM_H_ + +#include "platform_config.h" + +void init_platform(); +void cleanup_platform(); + +#endif Index: uart_plb/trunk/firmware/uart_plb_test/src/lscript.ld =================================================================== --- uart_plb/trunk/firmware/uart_plb_test/src/lscript.ld (nonexistent) +++ uart_plb/trunk/firmware/uart_plb_test/src/lscript.ld (revision 3) @@ -0,0 +1,212 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: Xilinx EDK 13.1 EDK_O.40d */ +/* */ +/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : MicroBlaze Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400; + +/* Define Memories in the system */ + +MEMORY +{ + ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000050, LENGTH = 0x00001FB0 +} + +/* Specify the default entry point to the program */ + +ENTRY(_start) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.vectors.reset 0x00000000 : { + *(.vectors.reset) +} + +.vectors.sw_exception 0x00000008 : { + *(.vectors.sw_exception) +} + +.vectors.interrupt 0x00000010 : { + *(.vectors.interrupt) +} + +.vectors.hw_exception 0x00000020 : { + *(.vectors.hw_exception) +} + +.text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) +} > ilmb_cntlr_dlmb_cntlr + +.init : { + KEEP (*(.init)) +} > ilmb_cntlr_dlmb_cntlr + +.fini : { + KEEP (*(.fini)) +} > ilmb_cntlr_dlmb_cntlr + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.sdata2 : { + . = ALIGN(8); + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + . = ALIGN(8); + __sdata2_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.data : { + . = ALIGN(4); + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __data_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.got : { + *(.got) +} > ilmb_cntlr_dlmb_cntlr + +.got1 : { + *(.got1) +} > ilmb_cntlr_dlmb_cntlr + +.got2 : { + *(.got2) +} > ilmb_cntlr_dlmb_cntlr + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > ilmb_cntlr_dlmb_cntlr + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > ilmb_cntlr_dlmb_cntlr + +.eh_frame : { + *(.eh_frame) +} > ilmb_cntlr_dlmb_cntlr + +.jcr : { + *(.jcr) +} > ilmb_cntlr_dlmb_cntlr + +.gcc_except_table : { + *(.gcc_except_table) +} > ilmb_cntlr_dlmb_cntlr + +.sdata : { + . = ALIGN(8); + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.sbss : { + . = ALIGN(4); + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + . = ALIGN(8); + __sbss_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; +} > ilmb_cntlr_dlmb_cntlr + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap : { + . = ALIGN(8); + _heap = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.stack : { + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(8); + _stack = .; + __stack = _stack; +} > ilmb_cntlr_dlmb_cntlr + +_end = .; +} + Index: uart_plb/trunk/firmware/standalone_bsp_0/libgen.log =================================================================== --- uart_plb/trunk/firmware/standalone_bsp_0/libgen.log (nonexistent) +++ uart_plb/trunk/firmware/standalone_bsp_0/libgen.log (revision 3) @@ -0,0 +1,20 @@ +Release 13.1 - libgen Xilinx EDK 13.1 Build EDK_O.40d + (nt) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. + +Command Line: libgen -hw ../platform/system.xml -pe microblaze_0 -log libgen.log +system.mss + + +Staging source files. +Running DRCs. +Running generate. +Running post_generate. +Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar" +"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare +-mcpu=v8.10.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'. + +Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar" +"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare +-mcpu=v8.10.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'. +Running execs_generate. Index: uart_plb/trunk/firmware/standalone_bsp_0/.project =================================================================== --- uart_plb/trunk/firmware/standalone_bsp_0/.project (nonexistent) +++ uart_plb/trunk/firmware/standalone_bsp_0/.project (revision 3) @@ -0,0 +1,77 @@ + + + standalone_bsp_0 + + + platform + + + + org.eclipse.cdt.make.core.makeBuilder + clean,full,incremental, + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + Index: uart_plb/trunk/firmware/standalone_bsp_0/system.mss =================================================================== --- uart_plb/trunk/firmware/standalone_bsp_0/system.mss (nonexistent) +++ uart_plb/trunk/firmware/standalone_bsp_0/system.mss (revision 3) @@ -0,0 +1,57 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 3.01.a + PARAMETER PROC_INSTANCE = microblaze_0 + PARAMETER STDIN = RS232_DCE + PARAMETER STDOUT = RS232_DCE +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 1.13.a + PARAMETER HW_INSTANCE = microblaze_0 +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = RS232_DCE +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 3.00.a + PARAMETER HW_INSTANCE = dlmb_cntlr +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 3.00.a + PARAMETER HW_INSTANCE = ilmb_cntlr +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = mdm_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = uart_plb_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = intc + PARAMETER DRIVER_VER = 2.02.a + PARAMETER HW_INSTANCE = xps_intc_0 +END + + Index: uart_plb/trunk/firmware/standalone_bsp_0/.sdkproject =================================================================== --- uart_plb/trunk/firmware/standalone_bsp_0/.sdkproject (nonexistent) +++ uart_plb/trunk/firmware/standalone_bsp_0/.sdkproject (revision 3) @@ -0,0 +1,3 @@ +THIRPARTY=false +PROCESSOR=microblaze_0 +MSS_FILE=system.mss Index: uart_plb/trunk/firmware/standalone_bsp_0/.cproject =================================================================== --- uart_plb/trunk/firmware/standalone_bsp_0/.cproject (nonexistent) +++ uart_plb/trunk/firmware/standalone_bsp_0/.cproject (revision 3) @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + Index: uart_plb/trunk/firmware/standalone_bsp_0/libgen.options =================================================================== --- uart_plb/trunk/firmware/standalone_bsp_0/libgen.options (nonexistent) +++ uart_plb/trunk/firmware/standalone_bsp_0/libgen.options (revision 3) @@ -0,0 +1,3 @@ +PROCESSOR=microblaze_0 +REPOSITORIES= +HWSPEC=../platform/system.xml Index: uart_plb/trunk/firmware/standalone_bsp_0/Makefile =================================================================== --- uart_plb/trunk/firmware/standalone_bsp_0/Makefile (nonexistent) +++ uart_plb/trunk/firmware/standalone_bsp_0/Makefile (revision 3) @@ -0,0 +1,21 @@ +# Makefile generated by Xilinx SDK. + +-include libgen.options + +LIBRARIES = ${PROCESSOR}/lib/libxil.a +MSS = system.mss + +all: libs + @echo 'Finished building libraries' + +libs: $(LIBRARIES) + +$(LIBRARIES): $(MSS) + libgen -hw ${HWSPEC}\ + ${REPOSITORIES}\ + -pe ${PROCESSOR} \ + -log libgen.log \ + $(MSS) + +clean: + rm -rf ${PROCESSOR}

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