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/AddSubBCD.vhd
0,0 → 1,85
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
 
entity AddSubBCD is
port(
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
CI : in std_logic;
ADD : in std_logic;
BCD : in std_logic;
w16 : in std_logic;
S : out std_logic_vector(15 downto 0);
CO : out std_logic;
VO : out std_logic
);
end AddSubBCD;
 
architecture rtl of AddSubBCD is
 
signal VO1, VO3 : std_logic;
signal CO0, CO1, CO2, CO3 : std_logic;
 
begin
add0 : entity work.BCDAdder
port map (
A => A(3 downto 0),
B => B(3 downto 0),
CI => CI,
S => S(3 downto 0),
CO => CO0,
ADD => ADD,
BCD => BCD
);
add1 : entity work.BCDAdder
port map (
A => A(7 downto 4),
B => B(7 downto 4),
CI => CO0,
S => S(7 downto 4),
CO => CO1,
VO => VO1,
ADD => ADD,
BCD => BCD
);
add2 : entity work.BCDAdder
port map (
A => A(11 downto 8),
B => B(11 downto 8),
CI => CO1,
S => S(11 downto 8),
CO => CO2,
ADD => ADD,
BCD => BCD
);
add3 : entity work.BCDAdder
port map (
A => A(15 downto 12),
B => B(15 downto 12),
CI => CO2,
S => S(15 downto 12),
CO => CO3,
VO => VO3,
ADD => ADD,
BCD => BCD
);
VO <= VO1 when w16 = '0' else VO3;
CO <= CO1 when w16 = '0' else CO3;
 
end rtl;
/BCDAdder.vhd
0,0 → 1,131
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
library work;
 
entity bit_adder is
port(
A : in std_logic;
B : in std_logic;
CI : in std_logic;
S : out std_logic;
CO : out std_logic
);
end bit_adder;
 
architecture rtl of bit_adder is
begin
S <= (not A and not B and CI) or
(not A and B and not CI) or
( A and not B and not CI) or
( A and B and CI);
CO <= (not A and B and CI) or
( A and not B and CI) or
( A and B and not CI) or
( A and B and CI);
 
end rtl;
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
library work;
 
entity adder4 is
port(
A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
CI : in std_logic;
S : out std_logic_vector(3 downto 0);
CO : out std_logic
);
end adder4;
 
architecture rtl of adder4 is
 
component bit_adder is
port(
A : in std_logic;
B : in std_logic;
CI : in std_logic;
S : out std_logic;
CO : out std_logic
);
end component;
signal CO0, CO1, CO2 : std_logic;
 
begin
b_add0: bit_adder port map (A(0), B(0), CI, S(0), CO0);
b_add1: bit_adder port map (A(1), B(1), CO0, S(1), CO1);
b_add2: bit_adder port map (A(2), B(2), CO1, S(2), CO2);
b_add3: bit_adder port map (A(3), B(3), CO2, S(3), CO);
 
end rtl;
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
library work;
 
entity BCDAdder is
port(
A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
CI : in std_logic;
S : out std_logic_vector(3 downto 0);
CO : out std_logic;
VO : out std_logic;
ADD : in std_logic;
BCD : in std_logic
);
end BCDAdder;
 
architecture rtl of BCDAdder is
 
signal B2 : std_logic_vector(3 downto 0);
signal BIN_S : std_logic_vector(3 downto 0);
signal BIN_CO : std_logic;
signal BCD_B : std_logic_vector(3 downto 0);
signal BCD_CO : std_logic;
 
begin
B2 <= B xor (3 downto 0 => not ADD);
bin_adder : entity work.adder4
port map(
A => A,
B => B2,
CI => CI,
S => BIN_S,
CO => BIN_CO
);
BCD_CO <= (BIN_S(3) and BIN_S(2)) or (BIN_S(3) and BIN_S(1)) or (BIN_CO xor not ADD);
BCD_B <= not ADD & ((BCD_CO and BCD) xor not ADD) & ((BCD_CO and BCD) xor not ADD) & not ADD;
bcd_corr_adder : entity work.adder4
port map(
A => BIN_S,
B => BCD_B,
CI => not ADD,
S => S
);
CO <= BIN_CO when BCD = '0' else BCD_CO xor not ADD;
VO <= (not (A(3) xor B2(3))) and (A(3) xor BIN_S(3));
 
end rtl;
/V65C816.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
V65C816.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: addrmux.vhd =================================================================== --- addrmux.vhd (nonexistent) +++ addrmux.vhd (revision 2) @@ -0,0 +1,42 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit two-way multiplexer +entity addrmux is + port( sel: in STD_LOGIC_VECTOR(2 downto 0); + a: in STD_LOGIC_VECTOR(23 downto 0); + b: in STD_LOGIC_VECTOR(23 downto 0); + dbr: in STD_LOGIC_VECTOR(7 downto 0); + s: in STD_LOGIC_VECTOR(15 downto 0); + xr: in STD_LOGIC_VECTOR(15 downto 0); + yr: in STD_LOGIC_VECTOR(15 downto 0); + y: out STD_LOGIC_VECTOR(23 downto 0) + ); +end addrmux; + +architecture comb of addrmux is +constant ADPC: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- select PC +constant ADMP: STD_LOGIC_VECTOR(2 downto 0) := "001"; -- select MP +constant ADSP: STD_LOGIC_VECTOR(2 downto 0) := "010"; -- select SP +constant ADDI: STD_LOGIC_VECTOR(2 downto 0) := "011"; -- select Direct +constant ADXR: STD_LOGIC_VECTOR(2 downto 0) := "100"; -- select X register +constant ADYR: STD_LOGIC_VECTOR(2 downto 0) := "101"; -- select Y register +constant ADNP: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- no operation (PC) +begin + process(sel,a,b,s,xr,yr,dbr) + begin + case sel is + when ADPC => y <= a; -- program counter + when ADMP => y <= b; -- memory data pointer + when ADSP => y <= "00000000" & s; -- stack address space + when ADDI => y <= "00000000" & b(15 downto 0); -- direct address space + when ADXR => y <= dbr & xr; -- DBR\X register + when ADYR => y <= dbr & yr; -- DBR\Y register + when others => y <= a; + end case; + end process; +end comb; + + Index: alu_bin.vhd =================================================================== --- alu_bin.vhd (nonexistent) +++ alu_bin.vhd (revision 2) @@ -0,0 +1,390 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8/16 bit binary alu +-- Written by Valerio Venturi +entity alu_bin is + port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation) + bcd: in STD_LOGIC; -- BCD mode + size: in STD_LOGIC; -- operations size: 1 = 8 bit, 0 = 16 bit + cin: in STD_LOGIC; -- carry/borrow in + vin: in STD_LOGIC; -- overflow in + op1: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #1 + op2: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #2 + fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code + cf: out STD_LOGIC; -- carry/borrow out + zf: out STD_LOGIC; -- zero flag out + nf: out STD_LOGIC; -- negative flag out + vf: out STD_LOGIC; -- overflow flag out + pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation + dout: out STD_LOGIC_VECTOR(15 downto 0) -- 16 bit result out + ); +end alu_bin; + +architecture comb of alu_bin is +-- ALU function codes +constant NOP_A: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- no operation +constant SUM_A: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- sum with carry +constant SUB_A: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- subtract with borrow +constant AND_A: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- and +constant OR_A: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- or +constant XOR_A: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- xor +constant INC_A: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- increment by 1 +constant DEC_A: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- decrement by 1 +constant SHL_A: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- shift left +constant SHR_A: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- shift right +constant ROL_A: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- rotation left +constant ROR_A: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- rotation right +constant SWC_A: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- sum without carry (used for indexing and branches) +constant SWC_N: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- subtract without borrow (used only by branches with negative offset) +constant BIT_A: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- bit test (used by BIT opcode) +constant DAA_A: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- decimal adjustement for BCD sum +constant DAS_A: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- decimal adjustement for BCD subtract +constant CMP_A: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- compare +constant TSB_A: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- test and set bit +constant TRB_A: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- test and reset bit +constant EXT_A: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- extend sign +constant NEG_A: STD_LOGIC_VECTOR(4 downto 0) := "10100"; -- negate + +signal c: STD_LOGIC; +signal pc_c: STD_LOGIC; +signal v_8: STD_LOGIC; +signal v_16: STD_LOGIC; +signal v_flg: STD_LOGIC; +signal add_op: STD_LOGIC; +signal bcd_c: STD_LOGIC; +signal bcd_v: STD_LOGIC; +signal n_size: STD_LOGIC; +signal bcd_sum: STD_LOGIC_VECTOR(15 downto 0); +signal n8_op2: STD_LOGIC_VECTOR(7 downto 0); +signal n16_op2: STD_LOGIC_VECTOR(15 downto 0); +signal y8: STD_LOGIC_VECTOR(8 downto 0); +signal y16: STD_LOGIC_VECTOR(16 downto 0); +signal y: STD_LOGIC_VECTOR(15 downto 0); +signal i_op1: STD_LOGIC_VECTOR(7 downto 0); +signal i_op2: STD_LOGIC_VECTOR(7 downto 0); + + +component AddSubBCD is + port( + A: in std_logic_vector(15 downto 0); + B: in std_logic_vector(15 downto 0); + CI: in std_logic; + ADD: in std_logic; + BCD: in std_logic; + w16: in std_logic; + S: out std_logic_vector(15 downto 0); + CO: out std_logic; + VO: out std_logic + ); +end component; + + +begin +n_size <= not size; +u1:AddSubBCD port map(A=>op1, + B=>op2, + CI=>cin, + ADD=>add_op, + BCD=>'1', + W16=>n_size, + S=>bcd_sum, + CO=>bcd_c, + vO=>bcd_v + ); + + i_op1 <= op1(7 downto 0); + i_op2 <= op2(7 downto 0); + n8_op2 <= (not i_op2); + n16_op2 <= (not op2); + process(size,bcd,alu_byp,fc,i_op1,i_op2,n8_op2,n16_op2,op1,op2,bcd_sum,cin,y16(7)) + begin + if size = '1' then + -- 8 bit + if alu_byp = '1' then + y8(y8'left) <= '0'; + y8(y8'left-1 downto y8'right) <= i_op1; + add_op <= '0'; + else + case fc is + when SUM_A => + add_op <= '1'; + if bcd = '0' then + y8 <= ('0' & i_op1) + ('0' & i_op2) + ("00000000" & cin); -- ADC with carry in + else + y8 <= '0' & bcd_sum(7 downto 0); + end if; + when SUB_A => + add_op <= '0'; + if bcd = '0' then + y8 <= ('0' & i_op1) + ('0' & n8_op2) + ("00000000" & cin); -- SBC with borrow in + else + y8 <= '0' & bcd_sum(7 downto 0); + end if; + when BIT_A => y8 <= ('0' & i_op1) and ('0' & i_op2); -- BIT test + add_op <= '0'; + when AND_A => y8 <= ('0' & i_op1) and ('0' & i_op2); -- AND + add_op <= '0'; + when OR_A => y8 <= ('0' & i_op1) or ('0' & i_op2); -- OR + add_op <= '0'; + when XOR_A => y8 <= ('0' & i_op1) xor ('0' & i_op2); -- XOR + add_op <= '0'; + when INC_A => y8 <= i_op1 + "000000001"; -- INC + add_op <= '0'; + when DEC_A => y8 <= i_op1 - "000000001"; -- DEC + add_op <= '0'; + when SHL_A => y8(8 downto 1) <= i_op1; y8(0) <= '0'; -- ASL + add_op <= '0'; + when SHR_A => y8 <= "00" & i_op1(i_op1'left downto i_op1'right+1); -- LSR + add_op <= '0'; + when ROL_A => y8(8 downto 1) <= i_op1; y8(0) <= cin; -- ROL + add_op <= '0'; + when ROR_A => y8 <= '0' & cin & i_op1(i_op1'left downto i_op1'right+1); -- ROR + add_op <= '0'; + when SWC_A => y8 <= ('0' & i_op1) + ('0' & i_op2); -- ADD without carry in + add_op <= '0'; + when DAA_A => y8 <= '0' & bcd_sum(7 downto 0); -- ADD without carry in (used for DAA decimal adjustement) + add_op <= '0'; + when DAS_A => y8 <= '0' & bcd_sum(7 downto 0); -- SUB without borrow in (used for DAS decimal adjustement) + add_op <= '1'; + when CMP_A => y8 <= ('1' & i_op1) - ('0' & i_op2); -- SBC without borrow in (used for compare) + add_op <= '0'; + when TSB_A => y8 <= ('0' & i_op1) or ('0' & i_op2); -- TSB + add_op <= '0'; + when TRB_A => y8 <= ('0' & not i_op1) and ('0' & i_op2); -- TRB + add_op <= '0'; + when NEG_A => y8 <= "000000000" - ('0' & i_op1); -- NEG + add_op <= '0'; + when EXT_A => y8(y8'left) <= '0'; y8(y8'left-1 downto y8'right) <= i_op1; -- NOP + add_op <= '0'; + when others => y8(y8'left) <= '0'; y8(y8'left-1 downto y8'right) <= i_op1; -- NOP + add_op <= '0'; + end case; + end if; + y16 <= (others => '0'); + else + -- 16 bit + if alu_byp = '1' then + y16(y16'left) <= '0'; + y16(y16'left-1 downto y16'right) <= op1; + add_op <= '0'; + else + case fc is + when SUM_A => + add_op <= '1'; + if bcd = '0' then + y16 <= ('0' & op1) + ('0' & op2) + ("0000000000000000" & cin); -- ADC with carry in + else + y16 <= '0' & bcd_sum; + end if; + when SUB_A => + add_op <= '0'; + if bcd = '0' then + y16 <= ('0' & op1) + ('0' & n16_op2) + ("0000000000000000" & cin); -- SBC with borrow in + else + y16 <= '0' & bcd_sum; + end if; + when BIT_A => y16 <= ('0' & op1) and ('0' & op2); -- BIT test + add_op <= '0'; + when AND_A => y16 <= ('0' & op1) and ('0' & op2); -- AND + add_op <= '0'; + when OR_A => y16 <= ('0' & op1) or ('0' & op2); -- OR + add_op <= '0'; + when XOR_A => y16 <= ('0' & op1) xor ('0' & op2); -- XOR + add_op <= '0'; + when INC_A => y16 <= op1 + "00000000000000001"; -- INC + add_op <= '0'; + when DEC_A => y16 <= op1 - "00000000000000001"; -- DEC + add_op <= '0'; + when SHL_A => y16(16 downto 1) <= op1; y16(0) <= '0'; -- ASL + add_op <= '0'; + when SHR_A => y16 <= "00" & op1(op1'left downto op1'right+1); -- LSR + add_op <= '0'; + when ROL_A => y16(16 downto 1) <= op1; y16(0) <= cin; -- ROL + add_op <= '0'; + when ROR_A => y16 <= '0' & cin & op1(op1'left downto op1'right+1); -- ROR + add_op <= '0'; + when SWC_A => y16 <= ('0' & op1) + ('0' & op2); -- ADD without carry in + add_op <= '0'; + when DAA_A => y16 <= '0' & bcd_sum; -- ADD without carry in (used for DAA decimal adjustement) + add_op <= '0'; + when DAS_A => y16 <= '0' & bcd_sum; -- SUB without borrow in (used for DAS decimal adjustement) + add_op <= '1'; + when CMP_A => y16 <= ('1' & op1) - ('0' & op2); -- SBC without borrow in (used for compare) + add_op <= '0'; + when TSB_A => y16 <= ('0' & op1) or ('0' & op2); -- TSB + add_op <= '0'; + when TRB_A => y16 <= ('0' & not op1) and ('0' & op2); -- TRB + add_op <= '0'; + when EXT_A => if op1(7) = '1' then -- if negative + y16(16 downto 8) <= "111111111"; -- extend sign to msb + y16(7 downto 0) <= op1(7 downto 0); + else + y16(16 downto 8) <= "000000000"; + y16(7 downto 0) <= op1(7 downto 0); + end if; + add_op <= '0'; + when NEG_A => y16 <= "00000000000000000" - ('0' & op1); -- NEG + add_op <= '0'; + when others => y16(y16'left) <= '0'; y16(y16'left-1 downto y16'right) <= op1; -- NOP + add_op <= '0'; + end case; + end if; + y8 <= (others => '0'); + end if; + end process; + + + + -- flag "C" carry/borrow logic + process(size,bcd,bcd_c,fc,op1,y8,y16,cin) + begin + if size = '1' then + case fc is + when SUM_A => + if bcd = '0' then + c <= y8(y8'left); + else + c <= bcd_c; + end if; + pc_c <= '0'; + when SUB_A => + if bcd = '0' then + c <= y8(y8'left); + else + c <= bcd_c; + end if; + pc_c <= '0'; + when SWC_A => pc_c <= y8(y8'left); + c <= cin; + when SHL_A => c <= y8(y8'left); + pc_c <= '0'; + when SHR_A => c <= op1(op1'right); + pc_c <= '0'; + when ROL_A => c <= y8(y8'left); + pc_c <= '0'; + when ROR_A => c <= op1(op1'right); + pc_c <= '0'; + when DAA_A => c <= y8(y8'left); + pc_c <= '0'; + when DAS_A => c <= cin; + pc_c <= '0'; + when BIT_A => c <= cin; + pc_c <= '0'; + when CMP_A => c <= y8(y8'left); + pc_c <= '0'; + when others => c <= cin; + pc_c <= '0'; + end case; + else + case fc is + when SUM_A => + if bcd = '0' then + c <= y16(y16'left); + else + c <= bcd_c; + end if; + pc_c <= '0'; + when SUB_A => + if bcd = '0' then + c <= y16(y16'left); + else + c <= bcd_c; + end if; + pc_c <= '0'; + when SWC_A => pc_c <= y16(8); + c <= cin; + when SHL_A => c <= y16(y16'left); + pc_c <= '0'; + when SHR_A => c <= op1(op1'right); + pc_c <= '0'; + when ROL_A => c <= y16(y16'left); + pc_c <= '0'; + when ROR_A => c <= op1(op1'right); + pc_c <= '0'; + when DAA_A => c <= y16(y16'left); + pc_c <= '0'; + when DAS_A => c <= cin; + pc_c <= '0'; + when BIT_A => c <= cin; + pc_c <= '0'; + when CMP_A => c <= y16(y16'left); + pc_c <= '0'; + when others => c <= cin; + pc_c <= '0'; + end case; + end if; + end process; + + -- flag "V" overflow logic + v_8 <= not (((op1(7) nor op2(7)) and y8(6)) nor ((op1(7) nand op2(7)) nor y8(6))); + v_16 <= not (((op1(15) nor op2(15)) and y16(14)) nor ((op1(15) nand op2(15)) nor y16(14))); + v_flg <= v_8 when size = '1' else v_16; + process(size,fc,bcd,i_op2,op2,v_flg,bcd_v,vin) + begin + case fc is + when SUM_A => + if bcd = '0' then + vf <= v_flg; + else + vf <= bcd_v; + end if; + when SUB_A => + if bcd = '0' then + vf <= v_flg; + else + vf <= bcd_v; + end if; + when BIT_A => + if size = '1' then + vf <= op2(6); + else + vf <= op2(14); + end if; + when others => vf <= vin; + end case; + end process; + + -- flag "N" negative result logic + process(size,fc,i_op2,y8,y16) + begin + if size = '1' then + case fc is + when BIT_A => nf <= i_op2(i_op2'left); + when others => nf <= y8(y8'left-1); + end case; + else + case fc is + when BIT_A => nf <= i_op2(i_op2'left); + when others => nf <= y16(y16'left-1); + end case; + end if; + end process; + + -- flag "Z" zero result logic (always set with zero results) + process(size,y8,y16) + begin + if size = '1' then + if y8(y8'left-1 downto y8'right) = "00000000" then + zf <= '1'; + else + zf <= '0'; + end if; + else + if y16(y16'left-1 downto y16'right) = "0000000000000000" then + zf <= '1'; + else + zf <= '0'; + end if; + end if; + end process; + + y <= op1(15 downto 8) & y8(y8'left-1 downto y8'right) when size = '1' else y16(y16'left-1 downto y16'right); + + + cf <= c; + pc_cf <= pc_c; + dout <= y; +end comb; Index: ar.vhd =================================================================== --- ar.vhd (nonexistent) +++ ar.vhd (revision 2) @@ -0,0 +1,73 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit accumulator register "A" +entity ar is + port( clk: in STD_LOGIC; + fwait: in STD_LOGIC; + size: in STD_LOGIC; + ld_lsb: in STD_LOGIC; + ld_msb: in STD_LOGIC; + ld_mul_lsb: in STD_LOGIC; + d: in STD_LOGIC; + end_count: out STD_LOGIC; + din: in STD_LOGIC_VECTOR(15 downto 0); + mul_lsb: in STD_LOGIC_VECTOR(15 downto 0); + dout: out STD_LOGIC_VECTOR(15 downto 0) + ); +end ar; + +architecture rtl of ar is +signal reg: STD_LOGIC_VECTOR(15 downto 0); +signal op: STD_LOGIC_VECTOR(3 downto 0); +begin + op <= ld_mul_lsb & d & ld_msb & ld_lsb; + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if size = '1' then + case op is + when "0001" => reg(7 downto 0) <= din(7 downto 0); -- load lsb + reg(15 downto 8) <= reg(15 downto 8); + when "0010" => reg(15 downto 8) <= din(7 downto 0); -- load msb + reg(7 downto 0) <= reg(7 downto 0); + when "0011" => reg(7 downto 0) <= din(7 downto 0); -- load msb & lsb + reg(15 downto 8) <= reg(15 downto 8); + when "0100" => reg <= reg - "0000000000000001"; -- decrement + when "1000" => reg <= mul_lsb; -- load multiplication lsb result + when others => reg <= reg; + end case; + else + case op is + when "0001" => reg(7 downto 0) <= din(7 downto 0); -- load lsb + reg(15 downto 8) <= reg(15 downto 8); + when "0010" => reg(15 downto 8) <= din(7 downto 0); -- load msb + reg(7 downto 0) <= reg(7 downto 0); + when "0011" => reg <= din; -- load msb & lsb + when "0100" => reg <= reg - "0000000000000001"; -- decrement + when "1000" => reg <= mul_lsb; -- load multiplication lsb result + when others => reg <= reg; + end case; + end if; + end if; + end if; + end process; + dout <= reg; + + -- used for MVN/MVP instructions + process(reg) + begin + if reg = "1111111111111111" then + end_count <= '1'; + else + end_count <= '0'; + end if; + end process; +end rtl; + + Index: br.vhd =================================================================== --- br.vhd (nonexistent) +++ br.vhd (revision 2) @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8 bit register "B" (DBR) +entity br is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + ld: in STD_LOGIC; + din: in STD_LOGIC_VECTOR(7 downto 0); + dout: out STD_LOGIC_VECTOR(7 downto 0) + ); +end br; + +architecture rtl of br is +signal reg: STD_LOGIC_VECTOR(7 downto 0); +begin + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then + reg <= "00000000"; + else + if ld = '1' then + reg <= din; + else + reg <= reg; + end if; + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: branch.vhd =================================================================== --- branch.vhd (nonexistent) +++ branch.vhd (revision 2) @@ -0,0 +1,36 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- branch resolving logic +entity branch is + port( op: in STD_LOGIC_VECTOR(3 downto 0); + n: in STD_LOGIC; + v: in STD_LOGIC; + z: in STD_LOGIC; + c: in STD_LOGIC; + bres: out STD_LOGIC + ); +end branch; + +architecture comb of branch is +begin + process(op,n,v,z,c) + begin + case op is + when "1000" => bres <= '1'; -- BRA + when "0001" => bres <= not n; -- BPL + when "0011" => bres <= n; -- BMI + when "0101" => bres <= not v; -- BVC + when "0111" => bres <= v; -- BVS + when "1111" => bres <= z; -- BEQ + when "1101" => bres <= not z; -- BNE + when "1001" => bres <= not c; -- BCC + when "1011" => bres <= c; -- BCS + when others => bres <= '0'; + end case; + end process; +end comb; + + Index: cpufsm.vhd =================================================================== --- cpufsm.vhd (nonexistent) +++ cpufsm.vhd (revision 2) @@ -0,0 +1,223 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- CPU FSM main state machine +entity cpufsm is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + ireq: in STD_LOGIC; + aim: in STD_LOGIC; + bcarry: in STD_LOGIC; + icarry: in STD_LOGIC; + p1: in STD_LOGIC_VECTOR(2 downto 0); + e_ei: in STD_LOGIC; + mc_ei: in STD_LOGIC; + addsub: in STD_LOGIC; + dec_mode: in STD_LOGIC; + fetch: out STD_LOGIC; + op_sync: out STD_LOGIC; + pci: out STD_LOGIC; + pq: out STD_LOGIC_VECTOR(2 downto 0); + fb: out STD_LOGIC; + od: out STD_LOGIC; + mc_nop: out STD_LOGIC + ); +end cpufsm; + +architecture rtl of cpufsm is +type states is (s0,s1,s2,s3,s4,s5,s6); +attribute ENUM_ENCODING:STRING; +attribute ENUM_ENCODING of states: type is "000000001 000000010 000000100 000001000 000010000 000100000 001000000"; -- one hot encoding for all states +signal present,nxt:states; +begin + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + present <= present; + else + present <= nxt; + end if; + end if; + end process; + + process(present,ireq,bcarry,icarry,p1,e_ei,mc_ei,aim,clr,addsub,dec_mode) + begin + case present is + -- reset + when s0 => + fetch <= '0'; + op_sync <= '0'; + pci <= '0'; + pq <= "000"; + fb <= '1'; -- force BRK + od <= '1'; -- clear microcode sequencer + mc_nop <= '0'; + if clr = '1' then + nxt <= s0; + else + nxt <= s2; + end if; + + -- fetch opcode + when s1 => + pq <= "000"; + if ireq = '1' then -- if interrupt request + od <= '0'; + fetch <= '0'; + fb <= '0'; + pci <= '0'; -- PC doesn't increment + op_sync <= '0'; + mc_nop <= '1'; -- stop microcode execution + nxt <= s6; -- goto s6 + else + od <= '1'; -- clear microcode sequencer + fetch <= '1'; -- fetch opcode + fb <= '0'; + pci <= '1'; -- PC increment + if addsub = '1'then -- if ADD/SUB opcode may require an extra cycle for DAA/DAS adjustement + op_sync <= '0'; + mc_nop <= '0'; + nxt <= s5; -- goto s5 + else + if e_ei = '1' then -- if end of instruction is reached on fetch + mc_nop <= '1'; + if clr = '1' then -- if reset + op_sync <= '0'; + nxt <= s0; -- goto reset + else + op_sync <= '1'; -- remain in this state to fetch a new opcode + nxt <= s1; + end if; + else + mc_nop <= '0'; + op_sync <= '0'; -- goto s2 + nxt <= s2; + end if; + end if; + end if; + + -- wait until end of instruction + when s2 => + fetch <= '0'; + pq <= p1; + fb <= '0'; + od <= '0'; + mc_nop <= '0'; + pci <= '0'; + if aim = '1' then -- opcode with indexed mode + op_sync <= '0'; + nxt <= s3; + else + if mc_ei = '1' then -- if end of instruction is reached + if clr = '1' then + op_sync <= '0'; + nxt <= s0; + else + op_sync <= '1'; + nxt <= s1; + end if; + else + op_sync <= '0'; + nxt <= s2; + end if; + end if; + + when s3 => -- opcode with absolute indexed mode + fetch <= '0'; + pq <= p1; + fb <= '0'; + od <= '0'; + pci <= '0'; + if mc_ei = '1' then -- if end of instruction is reached + if icarry = '0' then + mc_nop <= '1'; + if clr = '1' then + op_sync <= '0'; + nxt <= s0; + else + op_sync <= '1'; + nxt <= s1; + end if; + else + op_sync <= '0'; + mc_nop <= '0'; + nxt <= s4; + end if; + else + op_sync <= '0'; + mc_nop <= '0'; + nxt <= s3; + end if; + + when s4 => -- opcode with absolute indexed mode: add carry to msb PC + fetch <= '0'; + pq <= p1; + fb <= '0'; + od <= '0'; + pci <= '0'; + if clr = '1' then + mc_nop <= '0'; + op_sync <= '0'; + nxt <= s0; + else + mc_nop <= '1'; + op_sync <= '1'; + nxt <= s1; + end if; + + -- ADD/SUB decimal adjustement extra cycle + when s5 => + fetch <= '0'; + pq <= p1; + fb <= '0'; + od <= '0'; + pci <= '0'; + if mc_ei = '1' then + if dec_mode = '0' then + mc_nop <= '1'; + else + mc_nop <= '0'; + end if; + if clr = '1' then + op_sync <= '0'; + nxt <= s0; + else + op_sync <= '1'; + nxt <= s1; + end if; + else + mc_nop <= '0'; + op_sync <= '0'; + nxt <= s5; + end if; + + when s6 => + pq <= "000"; + od <= '1'; -- clear microcode sequencer + fetch <= '0'; + fb <= '1'; -- force load BRK to opcode register + pci <= '0'; -- PC doesn't increment + op_sync <= '1'; + mc_nop <= '0'; + nxt <= s2; -- goto s2 + + -- illegal state covering + when others => + fetch <= '0'; + op_sync <= '0'; + pci <= '0'; + pq <= "000"; + fb <= '0'; + od <= '1'; + mc_nop <= '0'; + nxt <= s0; + + end case; + end process; +end rtl; + + Index: data_mux.vhd =================================================================== --- data_mux.vhd (nonexistent) +++ data_mux.vhd (revision 2) @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8 bit three-way multiplexer +entity data_mux is + port( s: in STD_LOGIC_VECTOR(3 downto 0); + a: in STD_LOGIC_VECTOR(7 downto 0); + b: in STD_LOGIC_VECTOR(7 downto 0); + c: in STD_LOGIC_VECTOR(7 downto 0); + d: in STD_LOGIC_VECTOR(7 downto 0); + y: out STD_LOGIC_VECTOR(7 downto 0) + ); +end data_mux; + +architecture comb of data_mux is + +begin + process(s,a,b,c,d) + begin + case s is + when "1110" => y <= a; + when "1101" => y <= b; + when "1011" => y <= c; + when "0111" => y <= d; + when others => y <= a; + end case; + end process; +end comb; + + Index: decreg.vhd =================================================================== --- decreg.vhd (nonexistent) +++ decreg.vhd (revision 2) @@ -0,0 +1,110 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- register operation decode +entity decreg is + port( r: in STD_LOGIC_VECTOR(5 downto 0); + y: out STD_LOGIC_VECTOR(29 downto 0) + ); +end decreg; + +architecture comb of decreg is +constant NOP_R: STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- no operation +constant ALL_R: STD_LOGIC_VECTOR(5 downto 0) := "000001"; -- register A load lsb +constant ALM_R: STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- register A load msb +constant A16_R: STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- register A load msb & lsb +constant XLL_R: STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- register X load lsb +constant XLM_R: STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- register X load msb +constant X16_R: STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- register X load msb & lsb +constant YLL_R: STD_LOGIC_VECTOR(5 downto 0) := "000111"; -- register Y load lsb +constant YLM_R: STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- register Y load msb +constant Y16_R: STD_LOGIC_VECTOR(5 downto 0) := "001001"; -- register Y load msb & lsb +constant DLL_R: STD_LOGIC_VECTOR(5 downto 0) := "001010"; -- register D load lsb +constant DLM_R: STD_LOGIC_VECTOR(5 downto 0) := "001011"; -- register D load msb +constant D16_R: STD_LOGIC_VECTOR(5 downto 0) := "001100"; -- register D load msb & lsb +constant OLD_R: STD_LOGIC_VECTOR(5 downto 0) := "001101"; -- register O load lsb +constant OMD_R: STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- register O load msb +constant SLD_R: STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- register S load lsb +constant SLM_R: STD_LOGIC_VECTOR(5 downto 0) := "010000"; -- register S load msb +constant S16_R: STD_LOGIC_VECTOR(5 downto 0) := "010001"; -- register S load msb & lsb +constant SUP_R: STD_LOGIC_VECTOR(5 downto 0) := "010010"; -- register S increment by 1 +constant SDW_R: STD_LOGIC_VECTOR(5 downto 0) := "010011"; -- register S decrement by 1 +constant SAU_R: STD_LOGIC_VECTOR(5 downto 0) := "010100"; -- register A (lsb) load/register S increment by 1 +constant SXU_R: STD_LOGIC_VECTOR(5 downto 0) := "010101"; -- register X (lsb) load/register S increment by 1 +constant SXM_R: STD_LOGIC_VECTOR(5 downto 0) := "010110"; -- register X (msb) load/register S increment by 1 +constant SYU_R: STD_LOGIC_VECTOR(5 downto 0) := "010111"; -- register Y (lsb) load/register S increment by 1 +constant SYM_R: STD_LOGIC_VECTOR(5 downto 0) := "011000"; -- register Y (msb) load/register S increment by 1 +constant KLD_R: STD_LOGIC_VECTOR(5 downto 0) := "011001"; -- register K (PBR) load +constant BLD_R: STD_LOGIC_VECTOR(5 downto 0) := "011010"; -- register B (DBR) load +constant KCL_R: STD_LOGIC_VECTOR(5 downto 0) := "011011"; -- register K (PBR) clear and register S decrement by 1 +constant BCL_R: STD_LOGIC_VECTOR(5 downto 0) := "011100"; -- register B (DBR) clear +constant SKC_R: STD_LOGIC_VECTOR(5 downto 0) := "011101"; -- register B (DBR) clear and register S decrement by 1 +constant DEA_R: STD_LOGIC_VECTOR(5 downto 0) := "011110"; -- register A decrement (MVN/MVP) +constant O16_R: STD_LOGIC_VECTOR(5 downto 0) := "011111"; -- register O load msb & lsb +constant OSU_R: STD_LOGIC_VECTOR(5 downto 0) := "100000"; -- register O load lsb/register S increment by 1 +constant MVN_R: STD_LOGIC_VECTOR(5 downto 0) := "100001"; -- register XY increment by 1, A decremented by 1 +constant MVP_R: STD_LOGIC_VECTOR(5 downto 0) := "100010"; -- register XY decrement by 1, A decremented by 1 +constant MUL_R: STD_LOGIC_VECTOR(5 downto 0) := "100011"; -- register A/B load multiplication lsb result, register X load multiplication msb result +constant MUI_R: STD_LOGIC_VECTOR(5 downto 0) := "100100"; -- multiplication init +constant MUS_R: STD_LOGIC_VECTOR(5 downto 0) := "100101"; -- multiplication (unsigned) start +constant MSS_R: STD_LOGIC_VECTOR(5 downto 0) := "100110"; -- multiplication (signed) start +constant WAI_R: STD_LOGIC_VECTOR(5 downto 0) := "100111"; -- WAI set flipflop +constant STP_R: STD_LOGIC_VECTOR(5 downto 0) := "101000"; -- STP set flipflop +constant BLS_R: STD_LOGIC_VECTOR(5 downto 0) := "101001"; -- register B (DBR) load/register S incremented by 1 +constant DLS_R: STD_LOGIC_VECTOR(5 downto 0) := "101010"; -- register D load msb & lsb/register S incremented by 1 + +begin + process(r) + begin + case r is + when NOP_R => y <= "000000000000000000000000000000"; + when ALL_R => y <= "000000000000000000000000000001"; + when ALM_R => y <= "000000000000000000000000000010"; + when A16_R => y <= "000000000000000000000000000011"; + when DEA_R => y <= "000000000000000000000000000100"; + when XLL_R => y <= "000000000000000000000000001000"; + when XLM_R => y <= "000000000000000000000000010000"; + when X16_R => y <= "000000000000000000000000011000"; + when YLL_R => y <= "000000000000000000000010000000"; + when YLM_R => y <= "000000000000000000000100000000"; + when Y16_R => y <= "000000000000000000000110000000"; + when DLL_R => y <= "000000000000000000100000000000"; + when DLM_R => y <= "000000000000000001000000000000"; + when D16_R => y <= "000000000000000001100000000000"; + when OLD_R => y <= "000000000000000100000000000000"; + when OMD_R => y <= "000000000000001000000000000000"; + when SLD_R => y <= "000000000000010000000000000000"; + when SLM_R => y <= "000000000000100000000000000000"; + when S16_R => y <= "000000000000110000000000000000"; + when SUP_R => y <= "000000000001000000000000000000"; + when SDW_R => y <= "000000000010000000000000000000"; + when SAU_R => y <= "000000000001000000000000000001"; + when SXU_R => y <= "000000000001000000000000001000"; + when SXM_R => y <= "000000000001000000000000010000"; + when SYU_R => y <= "000000000001000000000010000000"; + when SYM_R => y <= "000000000001000000000100000000"; + when KLD_R => y <= "000000000100000000000000000000"; + when BLD_R => y <= "000000001000000000000000000000"; + when KCL_R => y <= "000000010010000000000000000000"; + when BCL_R => y <= "000000100000000000000000000000"; + when SKC_R => y <= "000000100010000000000000000000"; + when O16_R => y <= "000000000000000010000000000000"; + when OSU_R => y <= "000000000001000100000000000000"; + when MVN_R => y <= "000000000000000000010001000100"; + when MVP_R => y <= "000000000000000000001000100100"; + when MUL_R => y <= "000001000000000000000000000000"; + when MUI_R => y <= "000010000000000000000000000000"; + when MUS_R => y <= "000100000000000000000000000000"; + when MSS_R => y <= "001000000000000000000000000000"; + when WAI_R => y <= "010000000000000000000000000000"; + when STP_R => y <= "100000000000000000000000000000"; + when BLS_R => y <= "000000001001000000000000000000"; + when DLS_R => y <= "000000000001000001100000000000"; + when others => y <= "000000000000000000000000000000"; + end case; + end process; +end comb; + + Index: dmux.vhd =================================================================== --- dmux.vhd (nonexistent) +++ dmux.vhd (revision 2) @@ -0,0 +1,35 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8/16 bit three-way multiplexer +-- this multiplexer select the operand source for ALU operand #2 (op2) input +entity dmux is + port( sel: in STD_LOGIC_VECTOR(2 downto 0); + a: in STD_LOGIC_VECTOR(15 downto 0); + b: in STD_LOGIC_VECTOR(7 downto 0); + y: out STD_LOGIC_VECTOR(15 downto 0) + ); +end dmux; + +architecture comb of dmux is +constant NOP_D: STD_LOGIC_VECTOR(2 downto 0) := "000"; +constant ORD_D: STD_LOGIC_VECTOR(2 downto 0) := "001"; -- selects 16 bit operand register +constant EXT_D: STD_LOGIC_VECTOR(2 downto 0) := "010"; -- selects 8 bit external data bus +constant EXM_D: STD_LOGIC_VECTOR(2 downto 0) := "011"; -- selects msb 8 bit external data bus and lsb operand register +constant BCD_D: STD_LOGIC_VECTOR(2 downto 0) := "100"; -- not used + +begin + process(sel,a,b) + begin + case sel is + when ORD_D => y <= a; -- selects 16 bit operand register + when EXT_D => y <= "00000000" & b; -- selects 8 bit external data bus + when EXM_D => y <= b & a(7 downto 0); -- selects msb 8 bit external data bus and lsb operand register + when others => y <= "0000000000000000"; + end case; + end process; +end comb; + + Index: dr.vhd =================================================================== --- dr.vhd (nonexistent) +++ dr.vhd (revision 2) @@ -0,0 +1,47 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit zero page/direct register "D" +entity dr is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + ld_lsb: in STD_LOGIC; -- load lsb + ld_msb: in STD_LOGIC; -- load msb + din: in STD_LOGIC_VECTOR(15 downto 0); + dout: out STD_LOGIC_VECTOR(15 downto 0) + ); +end dr; + +architecture rtl of dr is +signal reg: STD_LOGIC_VECTOR(15 downto 0); +signal op: STD_LOGIC_VECTOR(1 downto 0); +begin + op <= ld_msb & ld_lsb; + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then + reg <= "0000000000000000"; + else + case op is + when "01" => reg(7 downto 0) <= din(7 downto 0); -- load lsb + reg(15 downto 8) <= reg(15 downto 8); + when "10" => reg(15 downto 8) <= din(7 downto 0); -- load msb + reg(7 downto 0) <= reg(7 downto 0); + when "11" => reg <= din; -- load msb & lsb + when others => reg <= reg; + end case; + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: intlog.vhd =================================================================== --- intlog.vhd (nonexistent) +++ intlog.vhd (revision 2) @@ -0,0 +1,151 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- interrupt request logic +entity intlog is + port( clk: in STD_LOGIC; + iack: in STD_LOGIC; -- interrupt acknowledge by microcode + r: in STD_LOGIC; -- RESET request + n: in STD_LOGIC; -- NMI request + i: in STD_LOGIC; -- IRQ request + brk: in STD_LOGIC; -- BRK opcode + cop: in STD_LOGIC; -- COP opcode + e: in STD_LOGIC; -- native\emulation mode + gmask: in STD_LOGIC; -- global interrupt mask valid for IRQ and NMI (used by two byte instruction) + imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ) + ioffs: in STD_LOGIC_VECTOR(7 downto 0); -- interrupt servicing offset + ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI) + voffs: out STD_LOGIC_VECTOR(7 downto 0) -- interrupt vector offset + ); +end intlog; + +architecture rtl of intlog is +signal irq_sync: STD_LOGIC_VECTOR(1 downto 0); +signal nmi_sync: STD_LOGIC_VECTOR(1 downto 0); +signal res_sync: STD_LOGIC_VECTOR(1 downto 0); +signal irq_req: STD_LOGIC; +signal i_nmi_req: STD_LOGIC; +signal nmi_req: STD_LOGIC; +signal res_req: STD_LOGIC; +signal nmi_clr: STD_LOGIC; +signal res_clr: STD_LOGIC; + +begin + process(clk) -- IRQ/NMI synchronization + begin + if(clk'event and clk = '1')then + res_sync <= res_sync(res_sync'left-1 downto res_sync'right) & r; -- RES sampling + nmi_sync <= nmi_sync(nmi_sync'left-1 downto nmi_sync'right) & n; -- NMI sampling + irq_sync <= irq_sync(irq_sync'left-1 downto irq_sync'right) & i; -- IRQ sampling + if res_clr = '1' then -- RES ack + res_req <= '0'; + else + if res_sync = "11" then -- level detection for RES + res_req <= '1'; + else + res_req <= res_req; + end if; + end if; + if nmi_clr = '1' then -- NMI ack + i_nmi_req <= '0'; + else + if nmi_sync = "01" then -- edge detection for NMI + i_nmi_req <= '1'; + else + i_nmi_req <= i_nmi_req; + end if; + end if; + end if; + end process; + nmi_req <= '1' when gmask = '0' and i_nmi_req = '1' else '0'; + + + process(gmask, imask, irq_sync) + begin + if gmask = '0' and imask = '0' then + if irq_sync = "11" then + irq_req <= '1'; + else + irq_req <= '0'; + end if; + else + irq_req <= '0'; + end if; + end process; + + -- priority encoder and vector offset generation (vector bits 7..0) + process(e, res_req, nmi_req, irq_req, brk, cop) + begin + if e = '0' then -- native mode + if res_req = '1' then + voffs <= x"FC"; -- RESET 0x00FFFC + else + if nmi_req = '1' then + voffs <= x"EA"; -- NMI 0x00FFEA + else + if irq_req = '1' then + voffs <= x"EE"; -- IRQ 0x00FFEE + else + if brk = '1' then + voffs <= x"E6"; -- BRK 0x00FFE6 + else + if cop = '1' then + voffs <= x"E4"; -- COP 0x00FFE4 + else + voffs <= "XXXXXXXX"; + end if; + end if; + end if; + end if; + end if; + else -- emulation mode + if res_req = '1' then + voffs <= x"FC"; -- RESET 0x00FFFC + else + if nmi_req = '1' then -- NMI 0x00FFFA + voffs <= x"FA"; + else + if irq_req = '1' then -- IRQ 0x00FFFE + voffs <= x"FE"; + else + if brk = '1' then -- BRK 0x00FFFE + voffs <= x"FE"; + else + if cop = '1' then -- COP 0x00FFF4 + voffs <= x"F4"; + else + voffs <= "XXXXXXXX"; + end if; + end if; + end if; + end if; + end if; + end if; + + end process; + + process(iack,ioffs) -- interrupt acknowledge and flags clear + begin + if iack = '1' then + case ioffs is + when x"FC" => res_clr <= '1'; -- RESET acknowledge + nmi_clr <= '1'; -- also NMI acknowledge + when x"EA" => nmi_clr <= '1'; -- NMI acknowledge (native mode) + res_clr <= '0'; + when x"FA" => nmi_clr <= '1'; -- NMI acknowledge (emulation mode) + res_clr <= '0'; + when others => res_clr <= '0'; + nmi_clr <= '0'; + end case; + else + res_clr <= '0'; + nmi_clr <= '0'; + end if; + end process; + + ireq <= res_req or nmi_req or irq_req; +end rtl; + + Index: kr.vhd =================================================================== --- kr.vhd (nonexistent) +++ kr.vhd (revision 2) @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8 bit register "K" (PBR) +entity kr is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + ld: in STD_LOGIC; + din: in STD_LOGIC_VECTOR(7 downto 0); + dout: out STD_LOGIC_VECTOR(7 downto 0) + ); +end kr; + +architecture rtl of kr is +signal reg: STD_LOGIC_VECTOR(7 downto 0); +begin + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then + reg <= "00000000"; + else + if ld = '1' then + reg <= din; + else + reg <= reg; + end if; + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: mcpla.vhd =================================================================== --- mcpla.vhd (nonexistent) +++ mcpla.vhd (revision 2) @@ -0,0 +1,6610 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- microcode 65C816 +-- Written by Valerio Venturi +-- output fields format: +-- fields: +-- RSEL: registers output multiplexer select +-- REGOP: registers load/increment/decrement etc. +-- ALUOP: ALU operation +-- P_OP: register P set/reset bit +-- MPR: register MP +-- PCR: register PC +-- CLI: clear interrupt request +-- EI: end of microcode sequence +-- W: read/write control +-- PD: PC/MP output multiplexer select +-- VPA: valid program address +-- VDA: valid data address +-- ML: memory lock +entity mcpla is + port(em: in STD_LOGIC; -- emulation mode (1)/native mode (0) + m: in STD_LOGIC; -- M memory/acc. 8 bit (1), M memory/acc. 16 bit (0) + x: in STD_LOGIC; -- X index reg. 8 bit (1), X index reg. 16 bit (0) + a: in STD_LOGIC_VECTOR(12 downto 0); + q: out STD_LOGIC_VECTOR(44 downto 0) + ); +end mcpla; + +architecture comb of mcpla is + +constant MC_ADDR_LENGTH: INTEGER := 12; +-- opcode definition: +-- -- + +------------------------------------ +-- IMPLIED -- +------------------------------------ +constant NOP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111010100000"; -- 0xEA NOP + +-- interrupts/coprocessor +constant BRK_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000000"; -- 0x00 BRK/IRQ/NMI/RES +constant BRK_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000001"; -- 0x00 BRK/IRQ/NMI/RES +constant BRK_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000010"; -- 0x00 BRK/IRQ/NMI/RES +constant BRK_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000011"; -- 0x00 BRK/IRQ/NMI/RES +constant BRK_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000100"; -- 0x00 BRK/IRQ/NMI/RES +constant BRK_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000101"; -- 0x00 BRK/IRQ/NMI/RES +constant BRK_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000110"; -- 0x00 BRK/IRQ/NMI/RES +constant BRK_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000000111"; -- 0x00 BRK/IRQ/NMI/RES + +constant COP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100000"; -- 0x02 COP +constant COP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100001"; -- 0x02 COP +constant COP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100010"; -- 0x02 COP +constant COP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100011"; -- 0x02 COP +constant COP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100100"; -- 0x02 COP +constant COP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100101"; -- 0x02 COP +constant COP_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100110"; -- 0x02 COP +constant COP_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000100111"; -- 0x02 COP + +-- IMPLIED +constant CLC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000110000000"; -- 0x18 CLC 0->C +constant SEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001110000000"; -- 0x38 SEC 1->C +constant CLI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110000000"; -- 0x58 CLI 0->I +constant SEI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110000000"; -- 0x78 SEI 1->I +constant CLV_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101110000000"; -- 0xB8 CLV 0->V +constant CLD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110000000"; -- 0xD8 CLD 0->D +constant SED_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110000000"; -- 0xF8 SED 1->D +constant TAX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101010100000"; -- 0xAA TAX A->X +constant TAY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101010000000"; -- 0xA8 TAY A->Y +constant TXA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100010100000"; -- 0x8A TXA X->A +constant TYA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100110000000"; -- 0x98 TYA Y->A +constant TXY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100110110000"; -- 0x9B TXY X->Y +constant TYX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101110110000"; -- 0xBB TYX Y->X +constant TXS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100110100000"; -- 0x9A TXS X->S +constant TSX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101110100000"; -- 0xBA TSX S->X +constant TCD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110110000"; -- 0x5B TCD C->D +constant TDC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110110000"; -- 0x7B TDC D->C +constant PHP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000010000000"; -- 0x08 PHP P->S +constant PHA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010010000000"; -- 0x48 PHA A->S +constant PHA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010010000001"; -- 0x48 PHA A->S +constant PHX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110100000"; -- 0xDA PHX X->S +constant PHX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110100001"; -- 0xDA PHX X->S +constant PHY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110100000"; -- 0x5A PHY X->S +constant PHY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110100001"; -- 0x5A PHY X->S +constant PHD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000010110000"; -- 0x0B PHD D->S +constant PHD_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000010110001"; -- 0x0B PHD D->S +constant PLP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010000000"; -- 0x28 PLP S->P +constant PLP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010000001"; -- 0x28 PLP S->P +constant PLA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010000000"; -- 0x68 PLA S->A +constant PLA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010000001"; -- 0x68 PLA S->A +constant PLA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010000010"; -- 0x68 PLA S->A +constant PLA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010000011"; -- 0x68 PLA S->A +constant PLX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110100000"; -- 0xFA PLX S->X +constant PLX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110100001"; -- 0xFA PLX S->X +constant PLX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110100010"; -- 0xFA PLX S->X +constant PLX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110100011"; -- 0xFA PLX S->X +constant PLY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110100000"; -- 0x7A PLY S->Y +constant PLY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110100001"; -- 0x7A PLY S->Y +constant PLY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110100010"; -- 0x7A PLY S->Y +constant PLY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110100011"; -- 0x7A PLY S->Y +constant PLD_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010110000"; -- 0x2B PLD S->D +constant PLD_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010110001"; -- 0x2B PLD S->D +constant PLD_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010110010"; -- 0x2B PLD S->D +constant INC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000110100000"; -- 0x1A INC A +1 +constant DEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001110100000"; -- 0x3A DEC A -1 +constant INX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111010000000"; -- 0xE8 INX X +1 +constant DEX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110010100000"; -- 0xCA DEX X -1 +constant INY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110010000000"; -- 0xC8 INY Y +1 +constant DEY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100010000000"; -- 0x88 DEY Y -1 +constant RTS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000000000"; -- 0x60 RTS +constant RTS_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000000001"; -- 0x60 RTS +constant RTS_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000000010"; -- 0x60 RTS +constant RTS_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000000011"; -- 0x60 RTS +constant RTS_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000000100"; -- 0x60 RTS +constant RTI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000000000"; -- 0x40 RTI +constant RTI_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000000001"; -- 0x40 RTI +constant RTI_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000000010"; -- 0x40 RTI +constant RTI_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000000011"; -- 0x40 RTI +constant RTI_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000000100"; -- 0x40 RTI +constant RTI_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000000101"; -- 0x40 RTI +constant RTI_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000000110"; -- 0x40 RTI +constant ASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000010100000"; -- 0x0A ASL A +constant LSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010010100000"; -- 0x4A LSR A +constant ROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010100000"; -- 0x2A ROL A +constant ROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010100000"; -- 0x6A ROR A +constant TCS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000110110000"; -- 0x1B A->S +constant TSC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001110110000"; -- 0x3B S->A +constant XCE_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110110000"; -- 0xFB XCE E<->C +constant WDM_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000100000"; -- 0x42 WDM +constant PHK_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010010110000"; -- 0x4B PHK K->S +constant PHB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100010110000"; -- 0x8B PHB B->S +constant PLB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101010110000"; -- 0xAB PLB S->B +constant PLB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101010110001"; -- 0xAB PLB S->B +constant RTL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010110000"; -- 0x6B RTL +constant RTL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010110001"; -- 0x6B RTL +constant RTL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010110010"; -- 0x6B RTL +constant RTL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010110011"; -- 0x6B RTL +constant RTL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010110100"; -- 0x6B RTL +constant RTL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010110101"; -- 0x6B RTL +constant RTL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010110110"; -- 0x6B RTL +constant XBA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111010110000"; -- 0xEB XBA (swap A) +constant WAI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110010110000"; -- 0xCB WAI +constant WAI_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110010110001"; -- 0xCB WAI +constant STP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110110000"; -- 0xDB STP +constant STP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110110001"; -- 0xDB STP + +------------------------------------ +-- IMMEDIATE -- +------------------------------------ +constant IMLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101010010000"; -- 0xA9 LDA #IMM +constant IMLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101010010001"; -- 0xA9 LDA #IMM +constant IMLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000100000"; -- 0xA2 LDX #IMM +constant IMLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000100001"; -- 0xA2 LDX #IMM +constant IMLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000000000"; -- 0xA0 LDY #IMM +constant IMLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000000001"; -- 0xA0 LDY #IMM +constant IMADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010010000"; -- 0x69 ADC #IMM +constant IMADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010010001"; -- 0x69 ADC #IMM +constant IMADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011010010010"; -- 0x69 ADC #IMM +constant IMSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111010010000"; -- 0xE9 SBC #IMM +constant IMSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111010010001"; -- 0xE9 SBC #IMM +constant IMSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111010010010"; -- 0xE9 SBC #IMM +constant IMAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010010000"; -- 0x29 AND #IMM +constant IMAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001010010001"; -- 0x29 AND #IMM +constant IMORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000010010000"; -- 0x09 ORA #IMM +constant IMORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000010010001"; -- 0x09 ORA #IMM +constant IMEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010010010000"; -- 0x49 EOR #IMM +constant IMEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010010010001"; -- 0x49 EOR #IMM +constant IMCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110010010000"; -- 0xC9 CMP #IMM +constant IMCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110010010001"; -- 0xC9 CMP #IMM +constant IMCPX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000000000"; -- 0xE0 CPX #IMM +constant IMCPX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000000001"; -- 0xE0 CPX #IMM +constant IMCPY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000000000"; -- 0xC0 CPY #IMM +constant IMCPY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000000001"; -- 0xC0 CPY #IMM +constant IMBRK_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100010010000"; -- 0x89 BRK #IMM +constant IMBRK_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100010010001"; -- 0x89 BRK #IMM +constant IMSEP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000100000"; -- 0xE2 SEP #IMM +constant IMREP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000100000"; -- 0xC2 REP #IMM +constant IMBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100010010000"; -- 0x89 BIT #IMM +constant IMBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100010010001"; -- 0x89 BIT #IMM + +------------------------------------ +-- ZERO PAGE -- +------------------------------------ +constant ZPLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001010000"; -- 0xA5 LDA ZP +constant ZPLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001010001"; -- 0xA5 LDA ZP +constant ZPLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001010010"; -- 0xA5 LDA ZP +constant ZPLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001100000"; -- 0xA6 LDX ZP +constant ZPLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001100001"; -- 0xA6 LDX ZP +constant ZPLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001100010"; -- 0xA6 LDX ZP +constant ZPLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001000000"; -- 0xA4 LDY ZP +constant ZPLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001000001"; -- 0xA4 LDY ZP +constant ZPLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001000010"; -- 0xA4 LDY ZP +constant ZPSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001010000"; -- 0x85 STA ZP +constant ZPSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001010001"; -- 0x85 STA ZP +constant ZPSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001010010"; -- 0x85 STA ZP +constant ZPSTX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001100000"; -- 0x86 STX ZP +constant ZPSTX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001100001"; -- 0x86 STX ZP +constant ZPSTX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001100010"; -- 0x86 STX ZP +constant ZPSTY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001000000"; -- 0x84 STY ZP +constant ZPSTY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001000001"; -- 0x84 STY ZP +constant ZPSTY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001000010"; -- 0x84 STY ZP +constant ZPSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001000000"; -- 0x64 STZ ZP +constant ZPSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001000001"; -- 0x64 STZ ZP +constant ZPSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001000010"; -- 0x64 STZ ZP +constant ZPADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001010000"; -- 0x65 ADC ZP +constant ZPADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001010001"; -- 0x65 ADC ZP +constant ZPADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001010010"; -- 0x65 ADC ZP +constant ZPADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001010011"; -- 0x65 ADC ZP +constant ZPSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001010000"; -- 0xE5 SBC ZP +constant ZPSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001010001"; -- 0xE5 SBC ZP +constant ZPSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001010010"; -- 0xE5 SBC ZP +constant ZPSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001010011"; -- 0xE5 SBC ZP +constant ZPCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001010000"; -- 0xC5 CMP ZP +constant ZPCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001010001"; -- 0xC5 CMP ZP +constant ZPCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001010010"; -- 0xC5 CMP ZP +constant ZPCPX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001000000"; -- 0xE4 CPX ZP +constant ZPCPX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001000001"; -- 0xE4 CPX ZP +constant ZPCPX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001000010"; -- 0xE4 CPX ZP +constant ZPCPY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001000000"; -- 0xC4 CPY ZP +constant ZPCPY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001000001"; -- 0xC4 CPY ZP +constant ZPCPY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001000010"; -- 0xC4 CPY ZP +constant ZPAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001010000"; -- 0x25 AND ZP +constant ZPAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001010001"; -- 0x25 AND ZP +constant ZPAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001010010"; -- 0x25 AND ZP +constant ZPORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001010000"; -- 0x05 ORA ZP +constant ZPORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001010001"; -- 0x05 ORA ZP +constant ZPORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001010010"; -- 0x05 ORA ZP +constant ZPEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001010000"; -- 0x45 EOR ZP +constant ZPEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001010001"; -- 0x45 EOR ZP +constant ZPEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001010010"; -- 0x45 EOR ZP +constant ZPBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001000000"; -- 0x24 BIT ZP +constant ZPBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001000001"; -- 0x24 BIT ZP +constant ZPBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001000010"; -- 0x24 BIT ZP +constant ZPASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001100000"; -- 0x06 ASL ZP +constant ZPASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001100001"; -- 0x06 ASL ZP +constant ZPASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001100010"; -- 0x06 ASL ZP +constant ZPASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001100011"; -- 0x06 ASL ZP +constant ZPASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001100100"; -- 0x06 ASL ZP +constant ZPASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001100101"; -- 0x06 ASL ZP +constant ZPLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001100000"; -- 0x46 LSR ZP +constant ZPLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001100001"; -- 0x46 LSR ZP +constant ZPLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001100010"; -- 0x46 LSR ZP +constant ZPLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001100011"; -- 0x46 LSR ZP +constant ZPLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001100100"; -- 0x46 LSR ZP +constant ZPLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001100101"; -- 0x46 LSR ZP +constant ZPROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001100000"; -- 0x26 ROL ZP +constant ZPROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001100001"; -- 0x26 ROL ZP +constant ZPROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001100010"; -- 0x26 ROL ZP +constant ZPROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001100011"; -- 0x26 ROL ZP +constant ZPROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001100100"; -- 0x26 ROL ZP +constant ZPROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001100101"; -- 0x26 ROL ZP +constant ZPROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001100000"; -- 0x66 ROR ZP +constant ZPROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001100001"; -- 0x66 ROR ZP +constant ZPROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001100010"; -- 0x66 ROR ZP +constant ZPROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001100011"; -- 0x66 ROR ZP +constant ZPROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001100100"; -- 0x66 ROR ZP +constant ZPROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001100101"; -- 0x66 ROR ZP +constant ZPINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001100000"; -- 0xE6 INC ZP +constant ZPINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001100001"; -- 0xE6 INC ZP +constant ZPINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001100010"; -- 0xE6 INC ZP +constant ZPINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001100011"; -- 0xE6 INC ZP +constant ZPINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001100100"; -- 0xE6 INC ZP +constant ZPINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001100101"; -- 0xE6 INC ZP +constant ZPDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001100000"; -- 0xC6 DEC ZP +constant ZPDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001100001"; -- 0xC6 DEC ZP +constant ZPDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001100010"; -- 0xC6 DEC ZP +constant ZPDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001100011"; -- 0xC6 DEC ZP +constant ZPDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001100100"; -- 0xC6 DEC ZP +constant ZPDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001100101"; -- 0xC6 DEC ZP +constant ZPTSB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001000000"; -- 0x04 TSB ZP +constant ZPTSB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001000001"; -- 0x04 TSB ZP +constant ZPTSB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001000010"; -- 0x04 TSB ZP +constant ZPTSB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001000011"; -- 0x04 TSB ZP +constant ZPTSB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001000100"; -- 0x04 TSB ZP +constant ZPTSB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001000101"; -- 0x04 TSB ZP +constant ZPTSB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001000110"; -- 0x04 TSB ZP +constant ZPTRB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101000000"; -- 0x14 TRB ZP +constant ZPTRB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101000001"; -- 0x14 TRB ZP +constant ZPTRB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101000010"; -- 0x14 TRB ZP +constant ZPTRB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101000011"; -- 0x14 TRB ZP +constant ZPTRB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101000100"; -- 0x14 TRB ZP +constant ZPTRB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101000101"; -- 0x14 TRB ZP +constant ZPTRB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101000110"; -- 0x14 TRB ZP + +------------------------------------ +-- ZERO PAGE,X -- +------------------------------------ +constant ZXLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101010000"; -- 0xB5 LDA ZP,X +constant ZXLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101010001"; -- 0xB5 LDA ZP,X +constant ZXLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101010010"; -- 0xB5 LDA ZP,X +constant ZXLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101000000"; -- 0xB4 LDY ZP,X +constant ZXLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101000001"; -- 0xB4 LDY ZP,X +constant ZXLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101000010"; -- 0xB4 LDY ZP,X +constant ZXSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101010000"; -- 0x95 STA ZP,X +constant ZXSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101010001"; -- 0x95 STA ZP,X +constant ZXSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101010010"; -- 0x95 STA ZP,X +constant ZXSTY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101000000"; -- 0x94 STY ZP,X +constant ZXSTY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101000001"; -- 0x94 STY ZP,X +constant ZXSTY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101000010"; -- 0x94 STY ZP,X +constant ZXSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101000000"; -- 0x74 STZ ZP,X +constant ZXSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101000001"; -- 0x74 STZ ZP,X +constant ZXSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101000010"; -- 0x74 STZ ZP,X +constant ZXADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101010000"; -- 0x75 ADC ZP,X +constant ZXADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101010001"; -- 0x75 ADC ZP,X +constant ZXADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101010010"; -- 0x75 ADC ZP,X +constant ZXSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101010000"; -- 0xF5 SBC ZP,X +constant ZXSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101010001"; -- 0xF5 SBC ZP,X +constant ZXSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101010010"; -- 0xF5 SBC ZP,X +constant ZXCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101010000"; -- 0xD5 CMP ZP,X +constant ZXCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101010001"; -- 0xD5 CMP ZP,X +constant ZXCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101010010"; -- 0xD5 CMP ZP,X +constant ZXAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101010000"; -- 0x35 AND ZP,X +constant ZXAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101010001"; -- 0x35 AND ZP,X +constant ZXAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101010010"; -- 0x35 AND ZP,X +constant ZXORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101010000"; -- 0x15 ORA ZP,X +constant ZXORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101010001"; -- 0x15 ORA ZP,X +constant ZXORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101010010"; -- 0x15 ORA ZP,X +constant ZXEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101010000"; -- 0x55 EOR ZP,X +constant ZXEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101010001"; -- 0x55 EOR ZP,X +constant ZXEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101010010"; -- 0x55 EOR ZP,X +constant ZXASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101100000"; -- 0x16 ASL ZP,X +constant ZXASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101100001"; -- 0x16 ASL ZP,X +constant ZXASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101100010"; -- 0x16 ASL ZP,X +constant ZXASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101100011"; -- 0x16 ASL ZP,X +constant ZXASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101100100"; -- 0x16 ASL ZP,X +constant ZXASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101100101"; -- 0x16 ASL ZP,X +constant ZXLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101100000"; -- 0x56 LSR ZP,X +constant ZXLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101100001"; -- 0x56 LSR ZP,X +constant ZXLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101100010"; -- 0x56 LSR ZP,X +constant ZXLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101100011"; -- 0x56 LSR ZP,X +constant ZXLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101100100"; -- 0x56 LSR ZP,X +constant ZXLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101100101"; -- 0x56 LSR ZP,X +constant ZXROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101100000"; -- 0x36 ROL ZP,X +constant ZXROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101100001"; -- 0x36 ROL ZP,X +constant ZXROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101100010"; -- 0x36 ROL ZP,X +constant ZXROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101100011"; -- 0x36 ROL ZP,X +constant ZXROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101100100"; -- 0x36 ROL ZP,X +constant ZXROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101100101"; -- 0x36 ROL ZP,X +constant ZXROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101100000"; -- 0x76 ROR ZP,X +constant ZXROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101100001"; -- 0x76 ROR ZP,X +constant ZXROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101100010"; -- 0x76 ROR ZP,X +constant ZXROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101100011"; -- 0x76 ROR ZP,X +constant ZXROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101100100"; -- 0x76 ROR ZP,X +constant ZXROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101100101"; -- 0x76 ROR ZP,X +constant ZXDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101100000"; -- 0xD6 DEC ZP,X +constant ZXDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101100001"; -- 0xD6 DEC ZP,X +constant ZXDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101100010"; -- 0xD6 DEC ZP,X +constant ZXDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101100011"; -- 0xD6 DEC ZP,X +constant ZXDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101100100"; -- 0xD6 DEC ZP,X +constant ZXDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101100101"; -- 0xD6 DEC ZP,X +constant ZXINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101100000"; -- 0xF6 INC ZP,X +constant ZXINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101100001"; -- 0xF6 INC ZP,X +constant ZXINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101100010"; -- 0xF6 INC ZP,X +constant ZXINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101100011"; -- 0xF6 INC ZP,X +constant ZXINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101100100"; -- 0xF6 INC ZP,X +constant ZXINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101100101"; -- 0xF6 INC ZP,X +constant ZXBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101000000"; -- 0x34 BIT ZP,X +constant ZXBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101000001"; -- 0x34 BIT ZP,X +constant ZXBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101000010"; -- 0x34 BIT ZP,X + +------------------------------------ +-- ZERO PAGE,Y -- +------------------------------------ +constant ZYLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101100000"; -- 0xB6 LDX ZP,Y +constant ZYLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101100001"; -- 0xB6 LDX ZP,Y +constant ZYLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101100010"; -- 0xB6 LDX ZP,Y +constant ZYLDX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101100011"; -- 0xB6 LDX ZP,Y + +constant ZYSTX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101100000"; -- 0x96 STX ZP,Y +constant ZYSTX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101100001"; -- 0x96 STX ZP,Y +constant ZYSTX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101100010"; -- 0x96 STX ZP,Y + +------------------------------------ +-- INDIRECT -- +------------------------------------ +constant INJMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011000000"; -- 0x6C JMP (IND) +constant INJMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011000001"; -- 0x6C JMP (IND) +constant INJMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011000010"; -- 0x6C JMP (IND) +constant INJMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011000011"; -- 0x6C JMP (IND) +constant INJML_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111000000"; -- 0xDC JML (IND) +constant INJML_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111000001"; -- 0xDC JML (IND) +constant INJML_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111000010"; -- 0xDC JML (IND) +constant INJML_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111000011"; -- 0xDC JML (IND) +constant INJML_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111000100"; -- 0xDC JML (IND) + + +------------------------------------ +-- INDIRECT,Y -- +------------------------------------ +constant IYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100010000"; -- 0xB1 LDA [DIR],Y +constant IYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100010001"; -- 0xB1 LDA [DIR],Y +constant IYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100010010"; -- 0xB1 LDA [DIR],Y +constant IYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100010011"; -- 0xB1 LDA [DIR],Y +constant IYLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100010100"; -- 0xB1 LDA [DIR],Y +constant IYLDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100010101"; -- 0xB1 LDA [DIR],Y +constant IYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100010000"; -- 0x91 STA [DIR],Y +constant IYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100010001"; -- 0x91 STA [DIR],Y +constant IYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100010010"; -- 0x91 STA [DIR],Y +constant IYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100010011"; -- 0x91 STA [DIR],Y +constant IYSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100010100"; -- 0x91 STA [DIR],Y +constant IYSTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100010101"; -- 0x91 STA [DIR],Y +constant IYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100010000"; -- 0x71 ADC [DIR],Y +constant IYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100010001"; -- 0x71 ADC [DIR],Y +constant IYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100010010"; -- 0x71 ADC [DIR],Y +constant IYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100010011"; -- 0x71 ADC [DIR],Y +constant IYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100010100"; -- 0x71 ADC [DIR],Y +constant IYADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100010101"; -- 0x71 ADC [DIR],Y +constant IYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100010000"; -- 0xF1 SBC [DIR],Y +constant IYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100010001"; -- 0xF1 SBC [DIR],Y +constant IYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100010010"; -- 0xF1 SBC [DIR],Y +constant IYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100010011"; -- 0xF1 SBC [DIR],Y +constant IYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100010100"; -- 0xF1 SBC [DIR],Y +constant IYSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100010101"; -- 0xF1 SBC [DIR],Y +constant IYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100010000"; -- 0xD1 CMP [DIR],Y +constant IYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100010001"; -- 0xD1 CMP [DIR],Y +constant IYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100010010"; -- 0xD1 CMP [DIR],Y +constant IYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100010011"; -- 0xD1 CMP [DIR],Y +constant IYCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100010100"; -- 0xD1 CMP [DIR],Y +constant IYCMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100010101"; -- 0xD1 CMP [DIR],Y +constant IYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100010000"; -- 0x31 AND [DIR],Y +constant IYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100010001"; -- 0x31 AND [DIR],Y +constant IYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100010010"; -- 0x31 AND [DIR],Y +constant IYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100010011"; -- 0x31 AND [DIR],Y +constant IYAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100010100"; -- 0x31 AND [DIR],Y +constant IYAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100010101"; -- 0x31 AND [DIR],Y +constant IYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100010000"; -- 0x11 ORA [DIR],Y +constant IYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100010001"; -- 0x11 ORA [DIR],Y +constant IYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100010010"; -- 0x11 ORA [DIR],Y +constant IYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100010011"; -- 0x11 ORA [DIR],Y +constant IYORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100010100"; -- 0x11 ORA [DIR],Y +constant IYORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100010101"; -- 0x11 ORA [DIR],Y +constant IYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100010000"; -- 0x51 EOR [DIR],Y +constant IYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100010001"; -- 0x51 EOR [DIR],Y +constant IYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100010010"; -- 0x51 EOR [DIR],Y +constant IYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100010011"; -- 0x51 EOR [DIR],Y +constant IYEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100010100"; -- 0x51 EOR [DIR],Y +constant IYEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100010101"; -- 0x51 EOR [DIR],Y + +------------------------------------ +-- INDIRECT,X -- +------------------------------------ +constant IXLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000010000"; -- 0xA1 LDA (IND_ZP,X) +constant IXLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000010001"; -- 0xA1 LDA (IND_ZP,X) +constant IXLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000010010"; -- 0xA1 LDA (IND_ZP,X) +constant IXLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000010011"; -- 0xA1 LDA (IND_ZP,X) +constant IXLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000010100"; -- 0xA1 LDA (IND_ZP,X) +constant IXSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000010000"; -- 0x81 STA (IND_ZP,X) +constant IXSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000010001"; -- 0x81 STA (IND_ZP,X) +constant IXSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000010010"; -- 0x81 STA (IND_ZP,X) +constant IXSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000010011"; -- 0x81 STA (IND_ZP,X) +constant IXSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000010100"; -- 0x81 STA (IND_ZP,X) +constant IXAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000010000"; -- 0x21 AND (IND_ZP,X) +constant IXAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000010001"; -- 0x21 AND (IND_ZP,X) +constant IXAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000010010"; -- 0x21 AND (IND_ZP,X) +constant IXAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000010011"; -- 0x21 AND (IND_ZP,X) +constant IXAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000010100"; -- 0x21 AND (IND_ZP,X) +constant IXORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000010000"; -- 0x01 ORA (IND_ZP,X) +constant IXORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000010001"; -- 0x01 ORA (IND_ZP,X) +constant IXORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000010010"; -- 0x01 ORA (IND_ZP,X) +constant IXORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000010011"; -- 0x01 ORA (IND_ZP,X) +constant IXORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000010100"; -- 0x01 ORA (IND_ZP,X) +constant IXEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000010000"; -- 0x41 EOR (IND_ZP,X) +constant IXEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000010001"; -- 0x41 EOR (IND_ZP,X) +constant IXEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000010010"; -- 0x41 EOR (IND_ZP,X) +constant IXEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000010011"; -- 0x41 EOR (IND_ZP,X) +constant IXEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000010100"; -- 0x41 EOR (IND_ZP,X) +constant IXCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000010000"; -- 0xC1 CMP (IND_ZP,X) +constant IXCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000010001"; -- 0xC1 CMP (IND_ZP,X) +constant IXCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000010010"; -- 0xC1 CMP (IND_ZP,X) +constant IXCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000010011"; -- 0xC1 CMP (IND_ZP,X) +constant IXCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000010100"; -- 0xC1 CMP (IND_ZP,X) +constant IXADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000010000"; -- 0x61 ADC (IND_ZP,X) +constant IXADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000010001"; -- 0x61 ADC (IND_ZP,X) +constant IXADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000010010"; -- 0x61 ADC (IND_ZP,X) +constant IXADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000010011"; -- 0x61 ADC (IND_ZP,X) +constant IXADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000010100"; -- 0x61 ADC (IND_ZP,X) +constant IXSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000010000"; -- 0xE1 SBC (IND_ZP,X) +constant IXSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000010001"; -- 0xE1 SBC (IND_ZP,X) +constant IXSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000010010"; -- 0xE1 SBC (IND_ZP,X) +constant IXSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000010011"; -- 0xE1 SBC (IND_ZP,X) +constant IXSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000010100"; -- 0xE1 SBC (IND_ZP,X) +constant IXJMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111000000"; -- 0x7C JMP (IND,X) +constant IXJMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111000001"; -- 0x7C JMP (IND,X) +constant IXJMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111000010"; -- 0x7C JMP (IND,X) +constant IXJMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111000011"; -- 0x7C JMP (IND,X) +constant IXJMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111000100"; -- 0x7C JMP (IND,X) +constant IXJSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111000000"; -- 0xFC JSR (IND,X) +constant IXJSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111000001"; -- 0xFC JSR (IND,X) +constant IXJSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111000010"; -- 0xFC JSR (IND,X) +constant IXJSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111000011"; -- 0xFC JSR (IND,X) +constant IXJSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111000100"; -- 0xFC JSR (IND,X) +constant IXJSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111000101"; -- 0xFC JSR (IND,X) + +------------------------------------ +-- ABSOLUTE -- +------------------------------------ +constant ABLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011010000"; -- 0xAD LDA ABS +constant ABLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011010001"; -- 0xAD LDA ABS +constant ABLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011010010"; -- 0xAD LDA ABS +constant ABLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011010011"; -- 0xAD LDA ABS +constant ABLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011100000"; -- 0xAE LDX ABS +constant ABLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011100001"; -- 0xAE LDX ABS +constant ABLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011100010"; -- 0xAE LDX ABS +constant ABLDX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011100011"; -- 0xAE LDX ABS +constant ABLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011000000"; -- 0xAC LDY ABS +constant ABLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011000001"; -- 0xAC LDY ABS +constant ABLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011000010"; -- 0xAC LDY ABS +constant ABLDY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011000011"; -- 0xAC LDY ABS +constant ABSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011010000"; -- 0x8D STA ABS +constant ABSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011010001"; -- 0x8D STA ABS +constant ABSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011010010"; -- 0x8D STA ABS +constant ABSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011010011"; -- 0x8D STA ABS +constant ABSTX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011100000"; -- 0x8E STX ABS +constant ABSTX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011100001"; -- 0x8E STX ABS +constant ABSTX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011100010"; -- 0x8E STX ABS +constant ABSTX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011100011"; -- 0x8E STX ABS +constant ABSTY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011000000"; -- 0x8C STY ABS +constant ABSTY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011000001"; -- 0x8C STY ABS +constant ABSTY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011000010"; -- 0x8C STY ABS +constant ABSTY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011000011"; -- 0x8C STY ABS +constant ABSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111000000"; -- 0x9C STZ ABS +constant ABSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111000001"; -- 0x9C STZ ABS +constant ABSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111000010"; -- 0x9C STZ ABS +constant ABSTZ_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111000011"; -- 0x9C STZ ABS +constant ABADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011010000"; -- 0x6D ADC ABS +constant ABADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011010001"; -- 0x6D ADC ABS +constant ABADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011010010"; -- 0x6D ADC ABS +constant ABADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011010011"; -- 0x6D ADC ABS +constant ABADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011010100"; -- 0x6D ADC ABS +constant ABSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011010000"; -- 0xED SBC ABS +constant ABSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011010001"; -- 0xED SBC ABS +constant ABSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011010010"; -- 0xED SBC ABS +constant ABSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011010011"; -- 0xED SBC ABS +constant ABSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011010100"; -- 0xED SBC ABS +constant ABORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011010000"; -- 0x0D ORA ABS +constant ABORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011010001"; -- 0x0D ORA ABS +constant ABORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011010010"; -- 0x0D ORA ABS +constant ABORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011010011"; -- 0x0D ORA ABS +constant ABAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011010000"; -- 0x2D AND ABS +constant ABAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011010001"; -- 0x2D AND ABS +constant ABAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011010010"; -- 0x2D AND ABS +constant ABAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011010011"; -- 0x2D AND ABS +constant ABEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011010000"; -- 0x4D EOR ABS +constant ABEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011010001"; -- 0x4D EOR ABS +constant ABEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011010010"; -- 0x4D EOR ABS +constant ABEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011010011"; -- 0x4D EOR ABS +constant ABCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011010000"; -- 0xCD CMP ABS +constant ABCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011010001"; -- 0xCD CMP ABS +constant ABCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011010010"; -- 0xCD CMP ABS +constant ABCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011010011"; -- 0xCD CMP ABS +constant ABCPX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011000000"; -- 0xEC CPX ABS +constant ABCPX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011000001"; -- 0xEC CPX ABS +constant ABCPX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011000010"; -- 0xEC CPX ABS +constant ABCPX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011000011"; -- 0xEC CPX ABS +constant ABCPY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011000000"; -- 0xCC CPY ABS +constant ABCPY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011000001"; -- 0xCC CPY ABS +constant ABCPY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011000010"; -- 0xCC CPY ABS +constant ABCPY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011000011"; -- 0xCC CPY ABS +constant ABJMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011000000"; -- 0x4C JMP ABS +constant ABJMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011000001"; -- 0x4C JMP ABS +constant ABJSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000000000"; -- 0x20 JSR ABS +constant ABJSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000000001"; -- 0x20 JSR ABS +constant ABJSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000000010"; -- 0x20 JSR ABS +constant ABJSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000000011"; -- 0x20 JSR ABS +constant ABBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011000000"; -- 0x2C BIT ABS +constant ABBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011000001"; -- 0x2C BIT ABS +constant ABBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011000010"; -- 0x2C BIT ABS +constant ABBIT_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011000011"; -- 0x2C BIT ABS +constant ABASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011100000"; -- 0x0E ASL ABS +constant ABASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011100001"; -- 0x0E ASL ABS +constant ABASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011100010"; -- 0x0E ASL ABS +constant ABASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011100011"; -- 0x0E ASL ABS +constant ABASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011100100"; -- 0x0E ASL ABS +constant ABASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011100101"; -- 0x0E ASL ABS +constant ABASL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011100110"; -- 0x0E ASL ABS +constant ABLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011100000"; -- 0x4E LSR ABS +constant ABLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011100001"; -- 0x4E LSR ABS +constant ABLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011100010"; -- 0x4E LSR ABS +constant ABLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011100011"; -- 0x4E LSR ABS +constant ABLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011100100"; -- 0x4E LSR ABS +constant ABLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011100101"; -- 0x4E LSR ABS +constant ABLSR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011100110"; -- 0x4E LSR ABS +constant ABROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011100000"; -- 0x2E ROL ABS +constant ABROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011100001"; -- 0x2E ROL ABS +constant ABROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011100010"; -- 0x2E ROL ABS +constant ABROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011100011"; -- 0x2E ROL ABS +constant ABROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011100100"; -- 0x2E ROL ABS +constant ABROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011100101"; -- 0x2E ROL ABS +constant ABROL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011100110"; -- 0x2E ROL ABS +constant ABROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011100000"; -- 0x6E ROR ABS +constant ABROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011100001"; -- 0x6E ROR ABS +constant ABROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011100010"; -- 0x6E ROR ABS +constant ABROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011100011"; -- 0x6E ROR ABS +constant ABROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011100100"; -- 0x6E ROR ABS +constant ABROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011100101"; -- 0x6E ROR ABS +constant ABROR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011100110"; -- 0x6E ROR ABS +constant ABINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011100000"; -- 0xEE INC ABS +constant ABINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011100001"; -- 0xEE INC ABS +constant ABINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011100010"; -- 0xEE INC ABS +constant ABINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011100011"; -- 0xEE INC ABS +constant ABINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011100100"; -- 0xEE INC ABS +constant ABINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011100101"; -- 0xEE INC ABS +constant ABINC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011100110"; -- 0xEE INC ABS +constant ABDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011100000"; -- 0xCE DEC ABS +constant ABDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011100001"; -- 0xCE DEC ABS +constant ABDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011100010"; -- 0xCE DEC ABS +constant ABDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011100011"; -- 0xCE DEC ABS +constant ABDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011100100"; -- 0xCE DEC ABS +constant ABDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011100101"; -- 0xCE DEC ABS +constant ABDEC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011100110"; -- 0xCE DEC ABS +constant ABTSB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000000"; -- 0x0C TSB ABS +constant ABTSB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000001"; -- 0x0C TSB ABS +constant ABTSB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000010"; -- 0x0C TSB ABS +constant ABTSB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000011"; -- 0x0C TSB ABS +constant ABTSB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000100"; -- 0x0C TSB ABS +constant ABTSB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000101"; -- 0x0C TSB ABS +constant ABTSB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000110"; -- 0x0C TSB ABS +constant ABTSB_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011000111"; -- 0x0C TSB ABS +constant ABTRB_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000000"; -- 0x1C TRB ABS +constant ABTRB_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000001"; -- 0x1C TRB ABS +constant ABTRB_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000010"; -- 0x1C TRB ABS +constant ABTRB_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000011"; -- 0x1C TRB ABS +constant ABTRB_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000100"; -- 0x1C TRB ABS +constant ABTRB_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000101"; -- 0x1C TRB ABS +constant ABTRB_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000110"; -- 0x1C TRB ABS +constant ABTRB_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111000111"; -- 0x1C TRB ABS + +------------------------------------ +-- ABSOLUTE,X -- +------------------------------------ +constant AXLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111010000"; -- 0xBD LDA ABS,X +constant AXLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111010001"; -- 0xBD LDA ABS,X +constant AXLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111010010"; -- 0xBD LDA ABS,X +constant AXLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111010011"; -- 0xBD LDA ABS,X +constant AXLDY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111000000"; -- 0xBC LDY ABS,X +constant AXLDY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111000001"; -- 0xBC LDY ABS,X +constant AXLDY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111000010"; -- 0xBC LDY ABS,X +constant AXLDY_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111000011"; -- 0xBC LDY ABS,X +constant AXSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111010000"; -- 0x9D STA ABS,X +constant AXSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111010001"; -- 0x9D STA ABS,X +constant AXSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111010010"; -- 0x9D STA ABS,X +constant AXSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111010011"; -- 0x9D STA ABS,X +constant AXSTZ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111100000"; -- 0x9E STZ ABS,X +constant AXSTZ_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111100001"; -- 0x9E STZ ABS,X +constant AXSTZ_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111100010"; -- 0x9E STZ ABS,X +constant AXSTZ_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111100011"; -- 0x9E STZ ABS,X +constant AXADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111010000"; -- 0x7D ADC ABS,X +constant AXADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111010001"; -- 0x7D ADC ABS,X +constant AXADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111010010"; -- 0x7D ADC ABS,X +constant AXADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111010011"; -- 0x7D ADC ABS,X +constant AXSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111010000"; -- 0xFD SBC ABS,X +constant AXSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111010001"; -- 0xFD SBC ABS,X +constant AXSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111010010"; -- 0xFD SBC ABS,X +constant AXSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111010011"; -- 0xFD SBC ABS,X +constant AXCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111010000"; -- 0xDD CMP ABS,X +constant AXCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111010001"; -- 0xDD CMP ABS,X +constant AXCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111010010"; -- 0xDD CMP ABS,X +constant AXCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111010011"; -- 0xDD CMP ABS,X +constant AXINC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111100000"; -- 0xFE INC ABS,X +constant AXINC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111100001"; -- 0xFE INC ABS,X +constant AXINC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111100010"; -- 0xFE INC ABS,X +constant AXINC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111100011"; -- 0xFE INC ABS,X +constant AXINC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111100100"; -- 0xFE INC ABS,X +constant AXINC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111100101"; -- 0xFE INC ABS,X +constant AXINC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111100110"; -- 0xFE INC ABS,X +constant AXDEC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111100000"; -- 0xDE DEC ABS,X +constant AXDEC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111100001"; -- 0xDE DEC ABS,X +constant AXDEC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111100010"; -- 0xDE DEC ABS,X +constant AXDEC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111100011"; -- 0xDE DEC ABS,X +constant AXDEC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111100100"; -- 0xDE DEC ABS,X +constant AXDEC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111100101"; -- 0xDE DEC ABS,X +constant AXDEC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111100110"; -- 0xDE DEC ABS,X +constant AXASL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111100000"; -- 0x1E ASL ABS,X +constant AXASL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111100001"; -- 0x1E ASL ABS,X +constant AXASL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111100010"; -- 0x1E ASL ABS,X +constant AXASL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111100011"; -- 0x1E ASL ABS,X +constant AXASL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111100100"; -- 0x1E ASL ABS,X +constant AXASL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111100101"; -- 0x1E ASL ABS,X +constant AXASL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111100110"; -- 0x1E ASL ABS,X +constant AXLSR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111100000"; -- 0x5E LSR ABS,X +constant AXLSR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111100001"; -- 0x5E LSR ABS,X +constant AXLSR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111100010"; -- 0x5E LSR ABS,X +constant AXLSR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111100011"; -- 0x5E LSR ABS,X +constant AXLSR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111100100"; -- 0x5E LSR ABS,X +constant AXLSR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111100101"; -- 0x5E LSR ABS,X +constant AXLSR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111100110"; -- 0x5E LSR ABS,X +constant AXROL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111100000"; -- 0x3E ROL ABS,X +constant AXROL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111100001"; -- 0x3E ROL ABS,X +constant AXROL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111100010"; -- 0x3E ROL ABS,X +constant AXROL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111100011"; -- 0x3E ROL ABS,X +constant AXROL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111100100"; -- 0x3E ROL ABS,X +constant AXROL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111100101"; -- 0x3E ROL ABS,X +constant AXROL_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111100110"; -- 0x3E ROL ABS,X +constant AXROR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111100000"; -- 0x7E ROR ABS,X +constant AXROR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111100001"; -- 0x7E ROR ABS,X +constant AXROR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111100010"; -- 0x7E ROR ABS,X +constant AXROR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111100011"; -- 0x7E ROR ABS,X +constant AXROR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111100100"; -- 0x7E ROR ABS,X +constant AXROR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111100101"; -- 0x7E ROR ABS,X +constant AXROR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111100110"; -- 0x7E ROR ABS,X +constant AXAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111010000"; -- 0x3D AND ABS,X +constant AXAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111010001"; -- 0x3D AND ABS,X +constant AXAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111010010"; -- 0x3D AND ABS,X +constant AXAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111010011"; -- 0x3D AND ABS,X +constant AXORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111010000"; -- 0x1D ORA ABS,X +constant AXORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111010001"; -- 0x1D ORA ABS,X +constant AXORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111010010"; -- 0x1D ORA ABS,X +constant AXORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111010011"; -- 0x1D ORA ABS,X +constant AXEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111010000"; -- 0x5D EOR ABS,X +constant AXEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111010001"; -- 0x5D EOR ABS,X +constant AXEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111010010"; -- 0x5D EOR ABS,X +constant AXEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111010011"; -- 0x5D EOR ABS,X +constant AXBIT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111000000"; -- 0x3C BIT ABS,X +constant AXBIT_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111000001"; -- 0x3C BIT ABS,X +constant AXBIT_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111000010"; -- 0x3C BIT ABS,X +constant AXBIT_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111000011"; -- 0x3C BIT ABS,X + +------------------------------------ +-- ABSOLUTE,Y -- +------------------------------------ +constant AYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101110010000"; -- 0xB9 LDA ABS,Y +constant AYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101110010001"; -- 0xB9 LDA ABS,Y +constant AYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101110010010"; -- 0xB9 LDA ABS,Y +constant AYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101110010011"; -- 0xB9 LDA ABS,Y +constant AYLDX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111100000"; -- 0xBE LDX ABS,Y +constant AYLDX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111100001"; -- 0xBE LDX ABS,Y +constant AYLDX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111100010"; -- 0xBE LDX ABS,Y +constant AYLDX_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111100011"; -- 0xBE LDX ABS,Y +constant AYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100110010000"; -- 0x99 STA ABS,Y +constant AYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100110010001"; -- 0x99 STA ABS,Y +constant AYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100110010010"; -- 0x99 STA ABS,Y +constant AYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100110010011"; -- 0x99 STA ABS,Y +constant AYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110010000"; -- 0x79 ADC ABS,Y +constant AYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110010001"; -- 0x79 ADC ABS,Y +constant AYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110010010"; -- 0x79 ADC ABS,Y +constant AYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110010011"; -- 0x79 ADC ABS,Y +constant AYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011110010100"; -- 0x79 ADC ABS,Y +constant AYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110010000"; -- 0xF9 SBC ABS,Y +constant AYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110010001"; -- 0xF9 SBC ABS,Y +constant AYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110010010"; -- 0xF9 SBC ABS,Y +constant AYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110010011"; -- 0xF9 SBC ABS,Y +constant AYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111110010100"; -- 0xF9 SBC ABS,Y +constant AYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110010000"; -- 0xD9 CMP ABS,Y +constant AYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110010001"; -- 0xD9 CMP ABS,Y +constant AYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110010010"; -- 0xD9 CMP ABS,Y +constant AYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110110010011"; -- 0xD9 CMP ABS,Y +constant AYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000110010000"; -- 0x19 ORA ABS,Y +constant AYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000110010001"; -- 0x19 ORA ABS,Y +constant AYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000110010010"; -- 0x19 ORA ABS,Y +constant AYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000110010011"; -- 0x19 ORA ABS,Y +constant AYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001110010000"; -- 0x39 AND ABS,Y +constant AYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001110010001"; -- 0x39 AND ABS,Y +constant AYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001110010010"; -- 0x39 AND ABS,Y +constant AYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001110010011"; -- 0x39 AND ABS,Y +constant AYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110010000"; -- 0x59 EOR ABS,Y +constant AYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110010001"; -- 0x59 EOR ABS,Y +constant AYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110010010"; -- 0x59 EOR ABS,Y +constant AYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010110010011"; -- 0x59 EOR ABS,Y + +------------------------------------------------ +-- ABSOLUTE LONG (JUMP...) -- +------------------------------------------------ +constant ABJML_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111000000"; -- 0x5C JML ABS +constant ABJML_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111000001"; -- 0x5C JML ABS +constant ABJML_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111000010"; -- 0x5C JML ABS +constant ABJSL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000100000"; -- 0x22 JSL ABS +constant ABJSL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000100001"; -- 0x22 JSL ABS +constant ABJSL_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000100010"; -- 0x22 JSL ABS +constant ABJSL_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000100011"; -- 0x22 JSL ABS +constant ABJSL_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000100100"; -- 0x22 JSL ABS +constant ABJSL_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000100101"; -- 0x22 JSL ABS + +------------------------------------ +-- RELATIVE -- +------------------------------------ +constant BRA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000000000"; -- 0x80 BRA +constant BCC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100000000"; -- 0x90 BCC +constant BCS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100000000"; -- 0xB0 BCS +constant BEQ_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100000000"; -- 0xF0 BEQ +constant BNE_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100000000"; -- 0xD0 BNE +constant BPL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100000000"; -- 0x10 BPL +constant BMI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100000000"; -- 0x30 BMI +constant BVC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100000000"; -- 0x50 BVC +constant BVS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100000000"; -- 0x70 BVS + +--------------------------------------- +-- RELATIVE LONG -- +--------------------------------------- +constant BRL_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000100000"; -- 0x82 BRL +constant BRL_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000100001"; -- 0x82 BRL + +------------------------------- +-- STACK -- +------------------------------- +constant PEA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101000000"; -- 0xF4 PEA +constant PEA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101000001"; -- 0xF4 PEA +constant PEA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101000010"; -- 0xF4 PEA +constant PEA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101000011"; -- 0xF4 PEA +constant PEI_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101000000"; -- 0xD4 PEI +constant PEI_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101000001"; -- 0xD4 PEI +constant PEI_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101000010"; -- 0xD4 PEI +constant PEI_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101000011"; -- 0xD4 PEI +constant PEI_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101000100"; -- 0xD4 PEI +constant PER_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000100000"; -- 0x62 PER +constant PER_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000100001"; -- 0x62 PER +constant PER_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000100010"; -- 0x62 PER +constant PER_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000100011"; -- 0x62 PER +constant PER_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000100100"; -- 0x62 PER + +---------------------------------- +-- DIRECT,Y -- +---------------------------------- +constant DYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101110000"; -- 0xB7 LDA [DIR],Y +constant DYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101110001"; -- 0xB7 LDA [DIR],Y +constant DYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101110010"; -- 0xB7 LDA [IND],Y +constant DYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101110011"; -- 0xB7 LDA [DIR],Y +constant DYLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101110100"; -- 0xB7 LDA [DIR],Y +constant DYLDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101110101"; -- 0xB7 LDA [DIR],Y +constant DYLDA_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101101110110"; -- 0xB7 LDA [DIR],Y +constant DYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101110000"; -- 0x97 STA [DIR],Y +constant DYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101110001"; -- 0x97 STA [DIR],Y +constant DYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101110010"; -- 0x97 STA [DIR],Y +constant DYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101110011"; -- 0x97 STA [DIR],Y +constant DYSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101110100"; -- 0x97 STA [DIR],Y +constant DYSTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101110101"; -- 0x97 STA [DIR],Y +constant DYSTA_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100101110110"; -- 0x97 STA [DIR],Y +constant DYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101110000"; -- 0x77 ADC [DIR],Y +constant DYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101110001"; -- 0x77 ADC [DIR],Y +constant DYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101110010"; -- 0x77 ADC [DIR],Y +constant DYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101110011"; -- 0x77 ADC [DIR],Y +constant DYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101110100"; -- 0x77 ADC [DIR],Y +constant DYADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101110101"; -- 0x77 ADC [DIR],Y +constant DYADC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011101110110"; -- 0x77 ADC [DIR],Y +constant DYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101110000"; -- 0xF7 SBC [DIR],Y +constant DYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101110001"; -- 0xF7 SBC [DIR],Y +constant DYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101110010"; -- 0xF7 SBC [DIR],Y +constant DYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101110011"; -- 0xF7 SBC [DIR],Y +constant DYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101110100"; -- 0xF7 SBC [DIR],Y +constant DYSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101110101"; -- 0xF7 SBC [DIR],Y +constant DYSBC_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111101110110"; -- 0xF7 SBC [DIR],Y +constant DYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101110000"; -- 0xD7 CMP [DIR],Y +constant DYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101110001"; -- 0xD7 CMP [DIR],Y +constant DYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101110010"; -- 0xD7 CMP [DIR],Y +constant DYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101110011"; -- 0xD7 CMP [DIR],Y +constant DYCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101110100"; -- 0xD7 CMP [DIR],Y +constant DYCMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101110101"; -- 0xD7 CMP [DIR],Y +constant DYCMP_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110101110110"; -- 0xD7 CMP [DIR],Y +constant DYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101110000"; -- 0x37 AND [DIR],Y +constant DYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101110001"; -- 0x37 AND [DIR],Y +constant DYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101110010"; -- 0x37 AND [DIR],Y +constant DYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101110011"; -- 0x37 AND [DIR],Y +constant DYAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101110100"; -- 0x37 AND [DIR],Y +constant DYAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101110101"; -- 0x37 AND [DIR],Y +constant DYAND_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001101110110"; -- 0x37 AND [DIR],Y +constant DYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101110000"; -- 0x17 ORA [DIR],Y +constant DYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101110001"; -- 0x17 ORA [DIR],Y +constant DYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101110010"; -- 0x17 ORA [DIR],Y +constant DYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101110011"; -- 0x17 ORA [DIR],Y +constant DYORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101110100"; -- 0x17 ORA [DIR],Y +constant DYORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101110101"; -- 0x17 ORA [DIR],Y +constant DYORA_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000101110110"; -- 0x17 ORA [DIR],Y +constant DYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101110000"; -- 0x57 EOR [DIR],Y +constant DYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101110001"; -- 0x57 EOR [DIR],Y +constant DYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101110010"; -- 0x57 EOR [DIR],Y +constant DYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101110011"; -- 0x57 EOR [DIR],Y +constant DYEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101110100"; -- 0x57 EOR [DIR],Y +constant DYEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101110101"; -- 0x57 EOR [DIR],Y +constant DYEOR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101110110"; -- 0x57 EOR [DIR],Y + +-------------------------------- +-- DIRECT -- +-------------------------------- +constant DILDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001110000"; -- 0xA7 LDA [DIR] +constant DILDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001110001"; -- 0xA7 LDA [DIR] +constant DILDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001110010"; -- 0xA7 LDA [IND] +constant DILDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001110011"; -- 0xA7 LDA [DIR] +constant DILDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001110100"; -- 0xA7 LDA [DIR] +constant DILDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101001110101"; -- 0xA7 LDA [DIR] +constant DISTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001110000"; -- 0x87 STA [DIR] +constant DISTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001110001"; -- 0x87 STA [DIR] +constant DISTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001110010"; -- 0x87 STA [DIR] +constant DISTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001110011"; -- 0x87 STA [DIR] +constant DISTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001110100"; -- 0x87 STA [DIR] +constant DISTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100001110101"; -- 0x87 STA [DIR] +constant DIADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001110000"; -- 0x67 ADC [DIR] +constant DIADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001110001"; -- 0x67 ADC [DIR] +constant DIADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001110010"; -- 0x67 ADC [DIR] +constant DIADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001110011"; -- 0x67 ADC [DIR] +constant DIADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001110100"; -- 0x67 ADC [DIR] +constant DIADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011001110101"; -- 0x67 ADC [DIR] +constant DISBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001110000"; -- 0xE7 SBC [DIR] +constant DISBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001110001"; -- 0xE7 SBC [DIR] +constant DISBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001110010"; -- 0xE7 SBC [DIR] +constant DISBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001110011"; -- 0xE7 SBC [DIR] +constant DISBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001110100"; -- 0xE7 SBC [DIR] +constant DISBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111001110101"; -- 0xE7 SBC [DIR] +constant DICMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001110000"; -- 0xC7 CMP [DIR] +constant DICMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001110001"; -- 0xC7 CMP [DIR] +constant DICMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001110010"; -- 0xC7 CMP [DIR] +constant DICMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001110011"; -- 0xC7 CMP [DIR] +constant DICMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001110100"; -- 0xC7 CMP [DIR] +constant DICMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110001110101"; -- 0xC7 CMP [DIR] +constant DIAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001110000"; -- 0x27 AND [DIR] +constant DIAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001110001"; -- 0x27 AND [DIR] +constant DIAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001110010"; -- 0x27 AND [DIR] +constant DIAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001110011"; -- 0x27 AND [DIR] +constant DIAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001110100"; -- 0x27 AND [DIR] +constant DIAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001001110101"; -- 0x27 AND [DIR] +constant DIORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001110000"; -- 0x07 ORA [DIR] +constant DIORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001110001"; -- 0x07 ORA [DIR] +constant DIORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001110010"; -- 0x07 ORA [DIR] +constant DIORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001110011"; -- 0x07 ORA [DIR] +constant DIORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001110100"; -- 0x07 ORA [DIR] +constant DIORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000001110101"; -- 0x07 ORA [DIR] +constant DIEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001110000"; -- 0x47 EOR [DIR] +constant DIEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001110001"; -- 0x47 EOR [DIR] +constant DIEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001110010"; -- 0x47 EOR [DIR] +constant DIEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001110011"; -- 0x47 EOR [DIR] +constant DIEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001110100"; -- 0x47 EOR [DIR] +constant DIEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001110101"; -- 0x47 EOR [DIR] + +---------------------------------------- +-- ABSOLUTE LONG -- +---------------------------------------- +constant ALLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011110000"; -- 0xAF LDA ABS_LONG +constant ALLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011110001"; -- 0xAF LDA ABS_LONG +constant ALLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011110010"; -- 0xAF LDA ABS_LONG +constant ALLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011110011"; -- 0xAF LDA ABS_LONG +constant ALLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101011110100"; -- 0xAF LDA ABS_LONG +constant ALSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011110000"; -- 0x8F STA ABS_LONG +constant ALSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011110001"; -- 0x8F STA ABS_LONG +constant ALSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011110010"; -- 0x8F STA ABS_LONG +constant ALSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011110011"; -- 0x8F STA ABS_LONG +constant ALSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100011110100"; -- 0x8F STA ABS_LONG +constant ALADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011110000"; -- 0x6F ADC ABS_LONG +constant ALADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011110001"; -- 0x6F ADC ABS_LONG +constant ALADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011110010"; -- 0x6F ADC ABS_LONG +constant ALADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011110011"; -- 0x6F ADC ABS_LONG +constant ALADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011110100"; -- 0x6F ADC ABS_LONG +constant ALADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011011110101"; -- 0x6F ADC ABS_LONG +constant ALSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011110000"; -- 0xEF SBC ABS_LONG +constant ALSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011110001"; -- 0xEF SBC ABS_LONG +constant ALSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011110010"; -- 0xEF SBC ABS_LONG +constant ALSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011110011"; -- 0xEF SBC ABS_LONG +constant ALSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011110100"; -- 0xEF SBC ABS_LONG +constant ALSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111011110101"; -- 0xEF SBC ABS_LONG +constant ALORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011110000"; -- 0x0F ORA ABS_LONG +constant ALORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011110001"; -- 0x0F ORA ABS_LONG +constant ALORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011110010"; -- 0x0F ORA ABS_LONG +constant ALORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011110011"; -- 0x0F ORA ABS_LONG +constant ALORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000011110100"; -- 0x0F ORA ABS_LONG +constant ALAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011110000"; -- 0x2F AND ABS_LONG +constant ALAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011110001"; -- 0x2F AND ABS_LONG +constant ALAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011110010"; -- 0x2F AND ABS_LONG +constant ALAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011110011"; -- 0x2F AND ABS_LONG +constant ALAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001011110100"; -- 0x2F AND ABS_LONG +constant ALEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011110000"; -- 0x4F EOR ABS_LONG +constant ALEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011110001"; -- 0x4F EOR ABS_LONG +constant ALEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011110010"; -- 0x4F EOR ABS_LONG +constant ALEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011110011"; -- 0x4F EOR ABS_LONG +constant ALEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010011110100"; -- 0x4F EOR ABS_LONG +constant ALCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011110000"; -- 0xCF CMP ABS_LONG +constant ALCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011110001"; -- 0xCF CMP ABS_LONG +constant ALCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011110010"; -- 0xCF CMP ABS_LONG +constant ALCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011110011"; -- 0xCF CMP ABS_LONG +constant ALCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110011110100"; -- 0xCF CMP ABS_LONG + +----------------------------------------- +-- ABSOLUTE LONG,X -- +----------------------------------------- +constant AILDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111110000"; -- 0xBF LDA ABS_LONG,X +constant AILDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111110001"; -- 0xBF LDA ABS_LONG,X +constant AILDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111110010"; -- 0xBF LDA ABS_LONG,X +constant AILDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111110011"; -- 0xBF LDA ABS_LONG,X +constant AILDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111110100"; -- 0xBF LDA ABS_LONG,X +constant AILDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101111110101"; -- 0xBF LDA ABS_LONG,X +constant AISTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111110000"; -- 0x9F STA ABS_LONG,X +constant AISTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111110001"; -- 0x9F STA ABS_LONG,X +constant AISTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111110010"; -- 0x9F STA ABS_LONG,X +constant AISTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111110011"; -- 0x9F STA ABS_LONG,X +constant AISTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111110100"; -- 0x9F STA ABS_LONG,X +constant AISTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100111110101"; -- 0x9F STA ABS_LONG,X +constant AIADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111110000"; -- 0x7F ADC ABS_LONG,X +constant AIADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111110001"; -- 0x7F ADC ABS_LONG,X +constant AIADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111110010"; -- 0x7F ADC ABS_LONG,X +constant AIADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111110011"; -- 0x7F ADC ABS_LONG,X +constant AIADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111110100"; -- 0x7F ADC ABS_LONG,X +constant AIADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011111110101"; -- 0x7F ADC ABS_LONG,X +constant AISBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111110000"; -- 0xFF SBC ABS_LONG,X +constant AISBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111110001"; -- 0xFF SBC ABS_LONG,X +constant AISBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111110010"; -- 0xFF SBC ABS_LONG,X +constant AISBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111110011"; -- 0xFF SBC ABS_LONG,X +constant AISBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111110100"; -- 0xFF SBC ABS_LONG,X +constant AISBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111111110101"; -- 0xFF SBC ABS_LONG,X +constant AICMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111110000"; -- 0xDF CMP ABS_LONG,X +constant AICMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111110001"; -- 0xDF CMP ABS_LONG,X +constant AICMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111110010"; -- 0xDF CMP ABS_LONG,X +constant AICMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111110011"; -- 0xDF CMP ABS_LONG,X +constant AICMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111110100"; -- 0xDF CMP ABS_LONG,X +constant AICMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110111110101"; -- 0xDF CMP ABS_LONG,X +constant AIAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111110000"; -- 0x3F AND ABS_LONG,X +constant AIAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111110001"; -- 0x3F AND ABS_LONG,X +constant AIAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111110010"; -- 0x3F AND ABS_LONG,X +constant AIAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111110011"; -- 0x3F AND ABS_LONG,X +constant AIAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111110100"; -- 0x3F AND ABS_LONG,X +constant AIAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001111110101"; -- 0x3F AND ABS_LONG,X +constant AIORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111110000"; -- 0x1F ORA ABS_LONG,X +constant AIORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111110001"; -- 0x1F ORA ABS_LONG,X +constant AIORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111110010"; -- 0x1F ORA ABS_LONG,X +constant AIORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111110011"; -- 0x1F ORA ABS_LONG,X +constant AIORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111110100"; -- 0x1F ORA ABS_LONG,X +constant AIORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000111110101"; -- 0x1F ORA ABS_LONG,X +constant AIEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111110000"; -- 0x5F EOR ABS_LONG,X +constant AIEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111110001"; -- 0x5F EOR ABS_LONG,X +constant AIEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111110010"; -- 0x5F EOR ABS_LONG,X +constant AIEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111110011"; -- 0x5F EOR ABS_LONG,X +constant AIEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111110100"; -- 0x5F EOR ABS_LONG,X +constant AIEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010111110101"; -- 0x5F EOR ABS_LONG,X + +----------------------------------------- +-- STACK RELATIVE -- +----------------------------------------- +constant SRLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000110000"; -- 0xA3 LDA $XX,S +constant SRLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000110001"; -- 0xA3 LDA $XX,S +constant SRLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101000110010"; -- 0xA3 LDA $XX,S +constant SRSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000110000"; -- 0x83 STA $XX,S +constant SRSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000110001"; -- 0x83 STA $XX,S +constant SRSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100000110010"; -- 0x83 STA $XX,S +constant SRADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000110000"; -- 0x63 ADC $XX,S +constant SRADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000110001"; -- 0x63 ADC $XX,S +constant SRADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011000110010"; -- 0x63 ADC $XX,S +constant SRSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000110000"; -- 0xE3 SBC $XX,S +constant SRSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000110001"; -- 0xE3 SBC $XX,S +constant SRSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111000110010"; -- 0xE3 SBC $XX,S +constant SRCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000110000"; -- 0xC3 CMP $XX,S +constant SRCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000110001"; -- 0xC3 CMP $XX,S +constant SRCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110000110010"; -- 0xC3 CMP $XX,S +constant SRAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000110000"; -- 0x23 AND $XX,S +constant SRAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000110001"; -- 0x23 AND $XX,S +constant SRAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001000110010"; -- 0x23 AND $XX,S +constant SRORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000110000"; -- 0x03 ORA $XX,S +constant SRORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000110001"; -- 0x03 ORA $XX,S +constant SRORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000000110010"; -- 0x03 ORA $XX,S +constant SREOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000110000"; -- 0x43 EOR $XX,S +constant SREOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000110001"; -- 0x43 EOR $XX,S +constant SREOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010000110010"; -- 0x43 EOR $XX,S + +-------------------------------------------------- +-- STACK RELATIVE INDEXED Y -- +-------------------------------------------------- +constant SYLDA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100110000"; -- 0xB3 LDA ($XX,S),Y +constant SYLDA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100110001"; -- 0xB3 LDA ($XX,S),Y +constant SYLDA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100110010"; -- 0xB3 LDA ($XX,S),Y +constant SYLDA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100110011"; -- 0xB3 LDA ($XX,S),Y +constant SYLDA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100110100"; -- 0xB3 LDA ($XX,S),Y +constant SYLDA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0101100110101"; -- 0xB3 LDA ($XX,S),Y +constant SYSTA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100110000"; -- 0x93 STA ($XX,S),Y +constant SYSTA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100110001"; -- 0x93 STA ($XX,S),Y +constant SYSTA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100110010"; -- 0x93 STA ($XX,S),Y +constant SYSTA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100110011"; -- 0x93 STA ($XX,S),Y +constant SYSTA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100110100"; -- 0x93 STA ($XX,S),Y +constant SYSTA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0100100110101"; -- 0x93 STA ($XX,S),Y +constant SYADC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100110000"; -- 0x73 ADC ($XX,S),Y +constant SYADC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100110001"; -- 0x73 ADC ($XX,S),Y +constant SYADC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100110010"; -- 0x73 ADC ($XX,S),Y +constant SYADC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100110011"; -- 0x73 ADC ($XX,S),Y +constant SYADC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100110100"; -- 0x73 ADC ($XX,S),Y +constant SYADC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0011100110101"; -- 0x73 ADC ($XX,S),Y +constant SYSBC_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100110000"; -- 0xF3 SBC ($XX,S),Y +constant SYSBC_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100110001"; -- 0xF3 SBC ($XX,S),Y +constant SYSBC_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100110010"; -- 0xF3 SBC ($XX,S),Y +constant SYSBC_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100110011"; -- 0xF3 SBC ($XX,S),Y +constant SYSBC_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100110100"; -- 0xF3 SBC ($XX,S),Y +constant SYSBC_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0111100110101"; -- 0xF3 SBC ($XX,S),Y +constant SYCMP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100110000"; -- 0xD3 CMP ($XX,S),Y +constant SYCMP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100110001"; -- 0xD3 CMP ($XX,S),Y +constant SYCMP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100110010"; -- 0xD3 CMP ($XX,S),Y +constant SYCMP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100110011"; -- 0xD3 CMP ($XX,S),Y +constant SYCMP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100110100"; -- 0xD3 CMP ($XX,S),Y +constant SYCMP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0110100110101"; -- 0xD3 CMP ($XX,S),Y +constant SYAND_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100110000"; -- 0x33 AND ($XX,S),Y +constant SYAND_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100110001"; -- 0x33 AND ($XX,S),Y +constant SYAND_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100110010"; -- 0x33 AND ($XX,S),Y +constant SYAND_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100110011"; -- 0x33 AND ($XX,S),Y +constant SYAND_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100110100"; -- 0x33 AND ($XX,S),Y +constant SYAND_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0001100110101"; -- 0x33 AND ($XX,S),Y +constant SYORA_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100110000"; -- 0x13 ORA ($XX,S),Y +constant SYORA_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100110001"; -- 0x13 ORA ($XX,S),Y +constant SYORA_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100110010"; -- 0x13 ORA ($XX,S),Y +constant SYORA_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100110011"; -- 0x13 ORA ($XX,S),Y +constant SYORA_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100110100"; -- 0x13 ORA ($XX,S),Y +constant SYORA_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0000100110101"; -- 0x13 ORA ($XX,S),Y +constant SYEOR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100110000"; -- 0x53 EOR ($XX,S),Y +constant SYEOR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100110001"; -- 0x53 EOR ($XX,S),Y +constant SYEOR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100110010"; -- 0x53 EOR ($XX,S),Y +constant SYEOR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100110011"; -- 0x53 EOR ($XX,S),Y +constant SYEOR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100110100"; -- 0x53 EOR ($XX,S),Y +constant SYEOR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010100110101"; -- 0x53 EOR ($XX,S),Y + +------------------------------------ +-- MOVE BLOCK -- +------------------------------------ +constant MBMVN_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000000"; -- 0x54 MVN $xx,$xx +constant MBMVN_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000001"; -- 0x54 MVN $xx,$xx +constant MBMVN_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000010"; -- 0x54 MVN $xx,$xx +constant MBMVN_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000011"; -- 0x54 MVN $xx,$xx +constant MBMVN_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000100"; -- 0x54 MVN $xx,$xx +constant MBMVN_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000101"; -- 0x54 MVN $xx,$xx +constant MBMVN_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000110"; -- 0x54 MVN $xx,$xx +constant MBMVN_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010101000111"; -- 0x54 MVN $xx,$xx + +constant MBMVP_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000000"; -- 0x44 MVP $xx,$xx +constant MBMVP_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000001"; -- 0x44 MVP $xx,$xx +constant MBMVP_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000010"; -- 0x44 MVP $xx,$xx +constant MBMVP_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000011"; -- 0x44 MVP $xx,$xx +constant MBMVP_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000100"; -- 0x44 MVP $xx,$xx +constant MBMVP_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000101"; -- 0x44 MVP $xx,$xx +constant MBMVP_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000110"; -- 0x44 MVP $xx,$xx +constant MBMVP_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "0010001000111"; -- 0x44 MVP $xx,$xx + +------------------------------------------------- +-- NEW OPCODES (WDM OPCODE) -- +------------------------------------------------- +-- IMPLIED +constant PHR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100010110000"; -- 0x8B PHR AXY->S (two byte instruction) +constant PHR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100010110001"; -- 0x8B PHR AXY->S (two byte instruction) +constant PHR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100010110010"; -- 0x8B PHR AXY->S (two byte instruction) +constant PHR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100010110011"; -- 0x8B PHR AXY->S (two byte instruction) +constant PHR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100010110100"; -- 0x8B PHR AXY->S (two byte instruction) +constant PHR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100010110101"; -- 0x8B PHR AXY->S (two byte instruction) + +constant PLR_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1101010110000"; -- 0xAB PLR S->YXA (two byte instruction) +constant PLR_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1101010110001"; -- 0xAB PLR S->YXA (two byte instruction) +constant PLR_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1101010110010"; -- 0xAB PLR S->YXA (two byte instruction) +constant PLR_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1101010110011"; -- 0xAB PLR S->YXA (two byte instruction) +constant PLR_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1101010110100"; -- 0xAB PLR S->YXA (two byte instruction) +constant PLR_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1101010110101"; -- 0xAB PLR S->YXA (two byte instruction) +constant PLR_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1101010110110"; -- 0xAB PLR S->YXA (two byte instruction) + +constant SAV_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000000"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000001"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000010"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000011"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000100"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000101"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000110"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100000111"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP8: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100001000"; -- 0x90 SAV AXYBDP->S (two byte instruction) +constant SAV_OP9: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100001001"; -- 0x90 SAV AXYBDP->S (two byte instruction) + +constant RST_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010000"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010001"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010010"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010011"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP4: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010100"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP5: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010101"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP6: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010110"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP7: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100010111"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP8: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100011000"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP9: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100011001"; -- 0x91 RST S->PDBYXA (two byte instruction) +constant RST_OP10: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100100011010"; -- 0x91 RST S->PDBYXA (two byte instruction) + +-- MULTIPLY UNSIGNED 16X16->32 BIT +constant MPU_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011100000"; -- 0x8E MPU multiply A*X (two byte instruction) +constant MPU_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011100001"; -- 0x8E MPU multiply A*X (two byte instruction) +constant MPU_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011100010"; -- 0x8E MPU multiply A*X (two byte instruction) +constant MPU_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011100011"; -- 0x8E MPU multiply A*X (two byte instruction) + +-- MULTIPLY SIGNED 16X16->32 BIT +constant MPS_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011110000"; -- 0x8F MPS multiply A*X (two byte instruction) +constant MPS_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011110001"; -- 0x8F MPS multiply A*X (two byte instruction) +constant MPS_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011110010"; -- 0x8F MPS multiply A*X (two byte instruction) +constant MPS_OP3: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1100011110011"; -- 0x8F MPS multiply A*X (two byte instruction) + +-- REGISTERS EXCHANGE +constant XYX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1111010110000"; -- 0xEB EXCHANGE X <-> Y (two byte instruction) +constant XYX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1111010110001"; -- 0xEB EXCHANGE X <-> Y (two byte instruction) +constant XYX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1111010110010"; -- 0xEB EXCHANGE X <-> Y (two byte instruction) +constant XAX_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1000010110000"; -- 0x0B EXCHANGE A <-> X (two byte instruction) +constant XAX_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1000010110001"; -- 0x0B EXCHANGE A <-> X (two byte instruction) +constant XAX_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1000010110010"; -- 0x0B EXCHANGE A <-> X (two byte instruction) +constant XAY_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1001010110000"; -- 0x2B EXCHANGE A <-> Y (two byte instruction) +constant XAY_OP1: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1001010110001"; -- 0x2B EXCHANGE A <-> Y (two byte instruction) +constant XAY_OP2: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1001010110010"; -- 0x2B EXCHANGE A <-> Y (two byte instruction) + +-- MISC +constant EXT_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1111011000000"; -- 0xEC EXTEND SIGN OF A TO B (two byte instruction) +constant NEG_OP0: STD_LOGIC_VECTOR(MC_ADDR_LENGTH downto 0) := "1111011010000"; -- 0xED NEGATE A (two byte instruction) + + +-- ALU microcode +constant NOP_A: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- no operation +constant SUM_A: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- sum with carry +constant SUB_A: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- subtract with borrow +constant AND_A: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- and +constant OR_A: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- or +constant XOR_A: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- xor +constant INC_A: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- increment by 1 +constant DEC_A: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- decrement by 1 +constant SHL_A: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- shift left +constant SHR_A: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- shift right +constant ROL_A: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- rotation left +constant ROR_A: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- rotation right +constant SWC_A: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- sum without carry (used for indexing and branches) +constant SWC_N: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- subtract without borrow (used only by branches with negative offset) +constant BIT_A: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- bit test (used by BIT opcode) +constant DAA_A: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- decimal adjustement for BCD sum +constant DAS_A: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- decimal adjustement for BCD subtract +constant CMP_A: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- compare +constant TSB_A: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- test and set bit +constant TRB_A: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- test and reset bit +constant EXT_A: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- extend sign +constant NEG_A: STD_LOGIC_VECTOR(4 downto 0) := "10100"; -- negate + +-- PCR microcode +constant NOP_PC: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PC no operation +constant LSB_PC: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PC load lsb +constant MSB_PC: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- PC load msb +constant INC_PC: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- PC increment by 1 +constant LOD_PC: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- PC load lsb\msb (used by JMP\JSR instructions) +constant LML_PC: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- PC load lsb\msb from oper register (used for JML\JSL instructions) +constant IN2_PC: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- PC = PC +2 (BRK opcode) +constant DE3_PC: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- PC = PC -3 (MVN/MVP opcodes) +constant BRA_PC: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- PC branch +constant BRL_PC: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- PC branch long + +-- MPR (memory data pointer) microcode +constant NOP_M: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- no operation +constant LSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- load lsb +constant MSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- load msb +constant INC_M: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- increment +constant DEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- decrement +constant VEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- load vector +constant ZPL_M: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- load ZEROPAGE +constant ALL_M: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- load all 16 bit register +constant ICC_M: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- increment MSB with carry +constant DOX_M: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- add D + offset + X +constant DOY_M: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- add D + offset + Y +constant AOS_M: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- add S + offset +constant ABX_M: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- add opr+X +constant ABY_M: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- add opr+Y +constant ADX_M: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- add X +constant ADY_M: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- add Y +constant MHB_M: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- load high byte +constant AOY_M: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- add opr+Y and concatenates SBR + +-- address multiplexer microcode +constant ADPC: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- select PC +constant ADMP: STD_LOGIC_VECTOR(2 downto 0) := "001"; -- select MP +constant ADSP: STD_LOGIC_VECTOR(2 downto 0) := "010"; -- select SP +constant ADDI: STD_LOGIC_VECTOR(2 downto 0) := "011"; -- select Direct +constant ADXR: STD_LOGIC_VECTOR(2 downto 0) := "100"; -- select X register +constant ADYR: STD_LOGIC_VECTOR(2 downto 0) := "101"; -- select Y register +constant ADNP: STD_LOGIC_VECTOR(2 downto 0) := "000"; -- no operation (PC) + +-- PR microcode +constant NOP_P: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- PR no operation +constant PLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- PR load +constant FLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- NV load +constant FLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- NZC load +constant FLV_P: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- NVZC load +constant SEC_P: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- 1 => C +constant CLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- 0 => C +constant SEI_P: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- 1 => I +constant CLI_P: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- 0 => I +constant SED_P: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- 1 => D +constant CLD_P: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- 0 => D +constant CLV_P: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- 0 => V +constant AUC_P: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- auc => ACR +constant HAC_P: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- hold ACR +constant SID_P: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- 1 => I/D +constant LDZ_P: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- Z load +constant XCE_P: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- E => C; C => E +constant SEP_P: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- P = P OR din +constant REP_P: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- P = P AND not din +constant WDM_P: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- 1 => op_exp; +constant WDC_P: STD_LOGIC_VECTOR(4 downto 0) := "10100"; -- 0 => op_exp; +constant FLW_P: STD_LOGIC_VECTOR(4 downto 0) := "10101"; -- NZ load, 0 -> op_exp +constant MUF_P: STD_LOGIC_VECTOR(4 downto 0) := "10110"; -- Z load from unsigned multplier +constant MSF_P: STD_LOGIC_VECTOR(4 downto 0) := "10111"; -- NZ load from unsigned multplier + +-- register operation microcode REGOP (decreg) +constant NOP_R: STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- no operation +constant ALL_R: STD_LOGIC_VECTOR(5 downto 0) := "000001"; -- register A load lsb +constant ALM_R: STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- register A load msb +constant A16_R: STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- register A load msb & lsb +constant XLL_R: STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- register X load lsb +constant XLM_R: STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- register X load msb +constant X16_R: STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- register X load msb & lsb +constant YLL_R: STD_LOGIC_VECTOR(5 downto 0) := "000111"; -- register Y load lsb +constant YLM_R: STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- register Y load msb +constant Y16_R: STD_LOGIC_VECTOR(5 downto 0) := "001001"; -- register Y load msb & lsb +constant DLL_R: STD_LOGIC_VECTOR(5 downto 0) := "001010"; -- register D load lsb +constant DLM_R: STD_LOGIC_VECTOR(5 downto 0) := "001011"; -- register D load msb +constant D16_R: STD_LOGIC_VECTOR(5 downto 0) := "001100"; -- register D load msb & lsb +constant OLD_R: STD_LOGIC_VECTOR(5 downto 0) := "001101"; -- register O load lsb +constant OMD_R: STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- register O load msb +constant SLD_R: STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- register S load lsb +constant SLM_R: STD_LOGIC_VECTOR(5 downto 0) := "010000"; -- register S load msb +constant S16_R: STD_LOGIC_VECTOR(5 downto 0) := "010001"; -- register S load msb & lsb +constant SUP_R: STD_LOGIC_VECTOR(5 downto 0) := "010010"; -- register S increment by 1 +constant SDW_R: STD_LOGIC_VECTOR(5 downto 0) := "010011"; -- register S decrement by 1 +constant SAU_R: STD_LOGIC_VECTOR(5 downto 0) := "010100"; -- register A (lsb) load/register S increment by 1 +constant SXU_R: STD_LOGIC_VECTOR(5 downto 0) := "010101"; -- register X (lsb) load/register S increment by 1 +constant SXM_R: STD_LOGIC_VECTOR(5 downto 0) := "010110"; -- register X (msb) load/register S increment by 1 +constant SYU_R: STD_LOGIC_VECTOR(5 downto 0) := "010111"; -- register Y (lsb) load/register S increment by 1 +constant SYM_R: STD_LOGIC_VECTOR(5 downto 0) := "011000"; -- register Y (msb) load/register S increment by 1 +constant KLD_R: STD_LOGIC_VECTOR(5 downto 0) := "011001"; -- register K (PBR) load +constant BLD_R: STD_LOGIC_VECTOR(5 downto 0) := "011010"; -- register B (DBR) load +constant KCL_R: STD_LOGIC_VECTOR(5 downto 0) := "011011"; -- register K (PBR) clear and register S decrement by 1 +constant BCL_R: STD_LOGIC_VECTOR(5 downto 0) := "011100"; -- register B (DBR) clear +constant SKC_R: STD_LOGIC_VECTOR(5 downto 0) := "011101"; -- register B (DBR) clear and register S decrement by 1 +constant DEA_R: STD_LOGIC_VECTOR(5 downto 0) := "011110"; -- register A decrement (MVN/MVP) +constant O16_R: STD_LOGIC_VECTOR(5 downto 0) := "011111"; -- register O load msb & lsb +constant OSU_R: STD_LOGIC_VECTOR(5 downto 0) := "100000"; -- register O load lsb/register S increment by 1 +constant MVN_R: STD_LOGIC_VECTOR(5 downto 0) := "100001"; -- register XY increment by 1, A decremented by 1 +constant MVP_R: STD_LOGIC_VECTOR(5 downto 0) := "100010"; -- register XY decrement by 1, A decremented by 1 +constant MUL_R: STD_LOGIC_VECTOR(5 downto 0) := "100011"; -- register A/B load multiplication lsb result, register X load multiplication msb result +constant MUI_R: STD_LOGIC_VECTOR(5 downto 0) := "100100"; -- multiplication init +constant MUS_R: STD_LOGIC_VECTOR(5 downto 0) := "100101"; -- multiplication (unsigned) start +constant MSS_R: STD_LOGIC_VECTOR(5 downto 0) := "100110"; -- multiplication (signed) start +constant WAI_R: STD_LOGIC_VECTOR(5 downto 0) := "100111"; -- WAI set flipflop +constant STP_R: STD_LOGIC_VECTOR(5 downto 0) := "101000"; -- STP set flipflop +constant BLS_R: STD_LOGIC_VECTOR(5 downto 0) := "101001"; -- register B (DBR) load/register S incremented by 1 +constant DLS_R: STD_LOGIC_VECTOR(5 downto 0) := "101010"; -- register D load msb & lsb/register S incremented by 1 + +-- register multiplexer microcode RSEL (ALU operand #1) +constant EXT_O: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- external data bus +constant ARD_O: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- register A msb & lsb select +constant ARM_O: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- register A msb select (also returns A swapped) +constant XRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- register X msb & lsb select +constant XRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- register X msb select +constant YRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- register Y msb & lsb select +constant YRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- register Y msb select +constant SRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- register S lsb select +constant PRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- register P select +constant PLR_O: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- register PCL select +constant PHR_O: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- register PCH select +constant ORD_O: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- register O msb & lsb select +constant Z00_O: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- select (all zero output) +constant DRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- register D msb & lsb select +constant DRM_O: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- register D msb select +constant KRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- register K PBR +constant BRD_O: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- register B PBR +constant EXM_O: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- external data bus on MSB, O on lsb +constant OMD_O: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- register O msb select +constant PCR_O: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- register PC (16 bit) select + +-- data multiplexer microcode DMUX (ALU operand #2) +constant NOP_D: STD_LOGIC_VECTOR(2 downto 0) := "000"; +constant ORD_D: STD_LOGIC_VECTOR(2 downto 0) := "001"; +constant EXT_D: STD_LOGIC_VECTOR(2 downto 0) := "010"; +constant EXM_D: STD_LOGIC_VECTOR(2 downto 0) := "011"; +constant BCD_D: STD_LOGIC_VECTOR(2 downto 0) := "100"; + +-- read/write control +constant RDE: STD_LOGIC_VECTOR(1 downto 0) := "11"; -- data bus read +constant WRE: STD_LOGIC_VECTOR(1 downto 0) := "10"; -- data bus write (combinatorial mode) +constant WRL: STD_LOGIC_VECTOR(1 downto 0) := "01"; -- data bus write (registered mode) + +begin + process(em,m,x,a) + begin + ----------------------------------- + -- NATIVE MODE -- + ----------------------------------- + if em = '0' then + -- The PLA is arranged like an ROM, there are an address input "a" and an data output "q". The address of PLA is 13 bit wide + -- and composed in this way: + -- + -- W ---- CPU OPCODE ---- --- MPC -- + -- | | | | | + -- | | | | | + -- W X--X--X--X--X--X--X--X--Y--Y--Y--Y + -- 12-11-10-09-08-07-06-05-04-03-02-01-00 + -- + -- the bit (12) W is the two byte instruction bit + -- the bits (11-4) (X field) is formed by CPU instruction opcode + -- the bits (3-0) (Y field) is formed by the three bit wide microinstruction program counter (MPC) + -- The MPC field is cleared at each opcode fetch by FSM and since it's three bit wide there are + -- an maximum of eight microinstructions available per opcode + -- + -- The bits 10-3 of PLA address serves to select the microcode group of a related CPU opcode + -- and they are stable for all instruction execution time, instead the remaining three bit 2-0 (MPC field) of PLA address + -- increment at each clock in order to address the next microcode instructions. + -- microcode assembly: + -- Due the particulary pipeline structure of this CPU, all microinstructions have an extra cycle hidden on fetch + -- of the next opcode instruction and normally this extra cycle is coded as "NOP" (see the last line "when others =>..."). + -- However there are some instructions where this extra cycle is used for some functions like decimal adjustments etc of + -- ADC and SBC instructions (see DAA and DAS). + -- + -- Microcode fields: + -- + -- DMUX: ALU operand #2 multiplexer + -- | AI: effective address is indexed (X or Y) + -- | | VP: vector pull + -- | | | ML: memory lock + -- | | | | VPA: valid program address + -- | | | | | VDA: valid data address + -- | | | | | | EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction) + -- | | | | | | | W: read/write control + -- | | | | | | | | CLI: clear interrupt request + -- | | | | | | | | | PD: PC/MP address output multiplexer select + -- | | | | | | | | | | PCR: register PC (program counter) + -- | | | | | | | | | | | MPR: register MP (memory pointer) + -- | | | | | | | | | | | | P_OP: register P set/reset bit + -- | | | | | | | | | | | | | ALUOP: ALU operation + -- | | | | | | | | | | | | | | REGOP: registers load/increment/decrement etc. + -- | | | | | | | | | | | | | | | RSEL: registers output multiplexer select + -- | | | | | | | | | | | | | | | | + -- | | | | | | | | | | | | | | | | + case a is -- DMUX AI VP ML VPA VDA EI W CLI PD PCR MPR P_OP ALUOP REGOP RSEL + ------------------------------------ + -- IMPLIED -- + ------------------------------------ + -- BRK + when BRK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & IN2_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- if no interrupt request then PC=PC+2 + when BRK_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- PBR->S; SP-1 + when BRK_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1 + when BRK_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1 + when BRK_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & KCL_R & PRD_O; -- P->S; VEC->MP; CLI; SEI; CLD + when BRK_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; 1->B; VP + when BRK_OP6 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP + + -- COP + when COP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & IN2_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- if no interrupt request then PC=PC+2 + when COP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- PBR->S; SP-1 + when COP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1 + when COP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1 + when COP_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & KCL_R & PRD_O; -- P->S; VEC->MP; CLI; SEI; CLD + when COP_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; 1->B; VP + when COP_OP6 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP + + -- NOP + when NOP_OP0 => q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- EI + + -- CLC + when CLC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLC_P & NOP_A & NOP_R & EXT_O; -- 0->C; EI + + -- SEC + when SEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEC_P & NOP_A & NOP_R & EXT_O; -- 1->C; EI + + -- CLI + when CLI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLI_P & NOP_A & NOP_R & EXT_O; -- 0->I; EI + + -- SEI + when SEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEI_P & NOP_A & NOP_R & EXT_O; -- 1->I; EI + + -- CLV + when CLV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLV_P & NOP_A & NOP_R & EXT_O; -- 0->V; EI + + -- CLD + when CLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLD_P & NOP_A & NOP_R & EXT_O; -- 0->D; EI + + -- SED + when SED_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SED_P & NOP_A & NOP_R & EXT_O; -- 1->D; EI + + -- TAX + when TAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & ARD_O; -- A->X; EI + + -- TXA + when TXA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & XRD_O; -- X->A; EI + + -- TAY + when TAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & Y16_R & ARD_O; -- A->Y; EI + + -- TYA + when TYA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & YRD_O; -- Y->A; EI + + -- TXY + when TXY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & Y16_R & XRD_O; -- X->Y; EI + + -- TYX + when TYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & YRD_O; -- Y->X; EI + + -- TCD + when TCD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & D16_R & ARD_O; -- C->D; EI + + -- TDC + when TDC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & DRD_O; -- D->C; EI + + -- TXS + when TXS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & S16_R & XRD_O; -- X->S; EI + + -- TSX + when TSX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & SRD_O; -- S->X; EI + + -- INC A + when INC_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & ALL_R & ARD_O; -- A+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & A16_R & ARD_O; -- A+1; EI + end if; + + -- DEC A + when DEC_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & ALL_R & ARD_O; -- A-1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & A16_R & ARD_O; -- A-1; EI + end if; + + -- INX + when INX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & X16_R & XRD_O; -- X+1; EI + + -- DEX + when DEX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & X16_R & XRD_O; -- X-1; EI + + -- INY + when INY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & Y16_R & YRD_O; -- Y+1; EI + + -- DEY + when DEY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & Y16_R & YRD_O; -- Y-1; EI + + -- PHP + when PHP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PRD_O; -- P->S; SP-1; EI + + -- PHD + when PHD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & DRM_O; -- D (msb) ->S; SP-1; + when PHD_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & DRD_O; -- D (lsb) ->S; SP-1; EI + + -- PHA + when PHA_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A (lsb) ->S; SP-1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARM_O; -- A (msb) ->S; SP-1; + end if; + when PHA_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A (lsb) ->S; SP-1; EI + end if; + + -- PHX + when PHX_OP0 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X (lsb) ->S; SP-1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRM_O; -- X (msb) ->S; SP-1; + end if; + when PHX_OP1 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X (lsb) ->S; SP-1; EI + end if; + + -- PHY + when PHY_OP0 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- Y (lsb) ->S; SP-1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRM_O; -- Y (msb) ->S; SP-1; + end if; + when PHY_OP1 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- Y (lsb) ->S; SP-1; EI + end if; + + -- PHR (in native mode PHR pushes ALWAYS 16 bit registers) + when PHR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARM_O; -- A(msb)->S; SP-1; (two byte instruction) + when PHR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A(lsb)->S; SP-1; (two byte instruction) + when PHR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRM_O; -- X(msb)->S; SP-1; (two byte instruction) + when PHR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X(lsb)->S; SP-1; (two byte instruction) + when PHR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRM_O; -- Y(msb)->S; SP-1; (two byte instruction) + when PHR_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & SDW_R & YRD_O; -- Y(lsb)->S; SP-1; EI (two byte instruction) + + -- SAV (in native mode STO pushes ALWAYS AXY 16 bit registers) + when SAV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARM_O; -- A(msb)->S; SP-1; (two byte instruction) + when SAV_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A(lsb)->S; SP-1; (two byte instruction) + when SAV_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRM_O; -- X(msb)->S; SP-1; (two byte instruction) + when SAV_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X(lsb)->S; SP-1; (two byte instruction) + when SAV_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRM_O; -- Y(msb)->S; SP-1; (two byte instruction) + when SAV_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- Y(lsb)->S; SP-1; (two byte instruction) + when SAV_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PRD_O; -- P->S; SP-1; (two byte instruction) + when SAV_OP7 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & BRD_O; -- B->S; SP-1; (two byte instruction) + when SAV_OP8 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & DRM_O; -- D (msb) ->S; SP-1; (two byte instruction) + when SAV_OP9 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & SDW_R & DRD_O; -- D (lsb) ->S; SP-1; (two byte instruction) + + -- RST (in native mode RST pulls ALWAYS AXY 16 bit registers) + when RST_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 (two byte instruction) + when RST_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OSU_R & EXT_O; -- S->O (lsb); SP+1 + when RST_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & DLS_R & EXM_O; -- S msb) & O (lsb) -> D;/SP+1 + when RST_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & BLS_R & EXT_O; -- S->B; SP +1 + when RST_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & SUP_R & EXT_O; -- S->P; SP+1 + when RST_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYU_R & EXT_O; -- S->Y (lsb); SP+1 (two byte instruction) + when RST_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYM_R & EXT_O; -- S->Y (msb); SP+1 (two byte instruction) + when RST_OP7 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXU_R & EXT_O; -- S->X (lsb); SP+1 (two byte instruction) + when RST_OP8 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXM_R & EXT_O; -- S->X (msb); SP+1 (two byte instruction) + when RST_OP9 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SAU_R & EXT_O; -- S->A (lsb); SP+1 (two byte instruction) + when RST_OP10 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & ALM_R & EXT_O; -- S->A (msb); EI (two byte instruction) + + -- PLP + when PLP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & NOP_R & EXT_O; -- S->P; EI + + -- PLD + when PLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLD_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OSU_R & EXT_O; -- S->O (lsb); SP+1 + when PLD_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & D16_R & EXM_O; -- S msb) & O (lsb) -> D; + + -- PLA + when PLA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLA_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- S->A (lsb); EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OSU_R & EXT_O; -- SP->MP; SP+1 + end if; + when PLA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- S->O (msb) + end if; + when PLA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & ORD_O; -- O->A (msb/lsb) + end if; + + -- PLX + when PLX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLX_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- S->X (lsb); EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OSU_R & EXT_O; -- SP->MP; SP+1 + end if; + when PLX_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- S->O (msb) + end if; + when PLX_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & ORD_O; -- O->X (msb/lsb) + end if; + + -- PLY + when PLY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLY_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- S->Y (lsb); EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OSU_R & EXT_O; -- SP->MP; SP+1 + end if; + when PLY_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- S->O (msb) + end if; + when PLY_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & Y16_R & ORD_O; -- O->X (msb/lsb) + end if; + + -- PLR (in native mode PLR pulls ALWAYS 16 bit registers) + when PLR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 (two byte instruction) + when PLR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYU_R & EXT_O; -- S->Y (lsb); SP+1 (two byte instruction) + when PLR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYM_R & EXT_O; -- S->Y (msb); SP+1 (two byte instruction) + when PLR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXU_R & EXT_O; -- S->X (lsb); SP+1 (two byte instruction) + when PLR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXM_R & EXT_O; -- S->X (msb); SP+1 (two byte instruction) + when PLR_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SAU_R & EXT_O; -- S->A (lsb); SP+1 (two byte instruction) + when PLR_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & ALM_R & EXT_O; -- S->A (msb); EI (two byte instruction) + + -- RTI + when RTI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; MP=01XX (STACK) + when RTI_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; MEM->P; SP +1 + when RTI_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O; + when RTI_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1 + when RTI_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MSB->O; + when RTI_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1; + when RTI_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADSP & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; MEM->PBR; + + -- RTS + when RTS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1 + when RTS_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O; + when RTS_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1; + when RTS_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC + when RTS_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI + + -- ASL (A) + when ASL_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHL_A & ALL_R & ARD_O; -- A (lsb) SHIFT LEFT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHL_A & A16_R & ARD_O; -- A (msb/lsb) SHIFT LEFT; EI + end if; + + -- LSR (A) + when LSR_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHR_A & ALL_R & ARD_O; -- A (lsb) SHIFT RIGHT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHR_A & A16_R & ARD_O; -- A (msb/lsb) SHIFT RIGHT; EI + end if; + + -- ROL (A) + when ROL_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROL_A & ALL_R & ARD_O; -- A (lsb) ROTATE LEFT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROL_A & A16_R & ARD_O; -- A (msb\lsb) ROTATE LEFT; EI + end if; + + -- ROR (A) + when ROR_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROR_A & ALL_R & ARD_O; -- A (lsb) ROTATE RIGHT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROR_A & A16_R & ARD_O; -- A (msb\lsb) ROTATE RIGHT; EI + end if; + + -- EXT (A) + when EXT_OP0 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- NOP; EI (two byte instruction) + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & EXT_A & A16_R & ARD_O; -- A (msb/lsb) SHIFT LEFT; EI (two byte instruction) + end if; + + -- NEG (A) + when NEG_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NEG_A & ALL_R & ARD_O; -- negates A (lsb); EI (two byte instruction) + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NEG_A & A16_R & ARD_O; -- negates A (msb\lsb); EI (two byte instruction) + end if; + + -- XYX + when XYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O; (two byte instruction) + when XYX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & X16_R & YRD_O; -- Y->X; + when XYX_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NOP_A & Y16_R & ORD_O; -- O->Y; EI + + -- XAX + when XAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O; (two byte instruction) + when XAX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & X16_R & ARD_O; -- A->X; + when XAX_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NOP_A & A16_R & ORD_O; -- O->A; EI + + -- XAY + when XAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & YRD_O; -- Y->O; (two byte instruction) + when XAY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & Y16_R & ARD_O; -- A->Y; + when XAY_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NOP_A & A16_R & ORD_O; -- O->A; EI + + -- TCS + when TCS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & S16_R & ARD_O; -- C->S; + + -- TSC + when TSC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & SRD_O; -- S->C; + + -- XCE + when XCE_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & XCE_P & NOP_A & NOP_R & EXT_O; -- E<>C; EI + + -- WDM + when WDM_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDM_P & NOP_A & NOP_R & EXT_O; -- set two byte instruction bit + + -- PHK + when PHK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- K->S; SP-1; EI + + -- PHB + when PHB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & BRD_O; -- B->S; SP-1; EI + + -- PLB + when PLB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & BLD_R & EXT_O; -- S->B; EI + + -- RTL + when RTL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1 + when RTL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O; + when RTL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1 + when RTL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MSB->O; + when RTL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1; + when RTL_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; MEM->PBR; + when RTL_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI + + -- XBA + when XBA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & ARM_O; -- swap A<->B; EI + + -- WAI + when WAI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & WAI_R & EXT_O; -- set WAI flipflop + when WAI_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + + -- STP + when STP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & STP_R & EXT_O; -- set STP flipflop + when STP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + + ------------------------------------ + -- IMMEDIATE -- + ------------------------------------ + -- LDA #xx/#xxxx + when IMLDA_OP0 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MEM->A (lsb); PC +1; EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O (lsb); PC +1; EI + end if; + when IMLDA_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MEM->A (msb\lsb); PC +1; EI + end if; + + -- LDX #xx/#xxxx + when IMLDX_OP0 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MEM->X (lsb); PC +1; EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O (lsb); PC +1; EI + end if; + when IMLDX_OP1 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & X16_R & EXM_O; -- MEM->X (msb\lsb); PC +1; EI + end if; + + + -- LDY #yy/#xxxx + when IMLDY_OP0 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MEM->Y (lsb); PC +1; EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O (lsb); PC +1; EI + end if; + when IMLDY_OP1 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & Y16_R & EXM_O; -- MEM->Y (msb\lsb); PC +1; EI + end if; + + -- ADC #xx/#xxxx (immediate) + when IMADC_OP0 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; PC +1; EI (emulation mode) + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); PC +1; + end if; + when IMADC_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + + -- SBC #xx/#xxxx (immediate) + when IMSBC_OP0 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A-EXT; PC +1; EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- A=A+EXT; PC +1; + end if; + when IMSBC_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- MEM->A (msb\lsb); PC +1; EI + end if; + + -- CMP #xx/#xxxx (immediate) + when IMCMP_OP0 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; PC +1; EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM (lsb)->O; PC +1;; + end if; + when IMCMP_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-(msb\lsb); PC +1; EI + end if; + + -- CPX #xx/#xxxx (immediate) + when IMCPX_OP0 => + if x = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; PC +1; EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM (lsb)->O; PC +1; + end if; + when IMCPX_OP1 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-(msb\lsb); PC +1; EI + end if; + + + -- CPY #xx/#xxxx (immediate) + when IMCPY_OP0 => + if x = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; PC +1; EI + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM (lsb)->O; PC +1; + end if; + when IMCPY_OP1 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- X-(msb\lsb); PC +1; EI + end if; + + -- AND #xx/#xxxx (immediate) + when IMAND_OP0 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A AND MEM -> A; PC +1; + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM (lsb)->O; PC +1; + end if; + when IMAND_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A AND MEM ->A (msb\lsb) -> A; PC +1; EI + end if; + + -- ORA #xx/#xxxx (immediate) + when IMORA_OP0 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A AND MEM -> A; PC +1; + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM (lsb)->O; PC +1; + end if; + when IMORA_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A OR MEM ->A (msb\lsb) -> A; PC +1; EI + end if; + + -- EOR #xx (immediate) + when IMEOR_OP0 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A XOR MEM -> A; PC +1; + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM (lsb)->O; PC +1; + end if; + when IMEOR_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A XOR MEM ->A (msb\lsb) -> A; PC +1; EI + end if; + + -- BIT #xx/#xxxx (immediate) + when IMBIT_OP0 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & LDZ_P & BIT_A & NOP_R & ARD_O; -- A AND MEM -> A; PC +1; + else + q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM (lsb)->O; PC +1; + end if; + when IMBIT_OP1 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A AND MEM ->A (msb\lsb) -> A; PC +1; EI + end if; + + -- SEP #xx (immediate) + when IMSEP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & SEP_P & NOP_A & NOP_R & EXT_O; -- P = P OR MEM; PC +1; + + -- REP #xx (immediate) + when IMREP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & REP_P & NOP_A & NOP_R & EXT_O; -- P = P AND NOT MEM; PC +1; + + ------------------------------------ + -- ZERO PAGE -- + ------------------------------------ + -- LDA $xx (zero page) + when ZPLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLDA_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & INC_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPLDA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1; EI + end if; + + -- LDX $xx (zero page) + when ZPLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLDX_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & INC_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPLDX_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & EXM_O; -- MP->MEM; MEM->X; PC+1; EI + end if; + + -- LDY $xx (zero page) + when ZPLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLDY_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & INC_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->Y; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPLDY_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & Y16_R & EXM_O; -- MP->MEM; MEM->Y; PC+1; EI + end if; + + -- STA $xx (zero page) + when ZPSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTA_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A (lsb) ->MEM; PC+1; MP+1; + end if; + when ZPSTA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A (msb) ->MEM; EI + end if; + + -- STX $xx (zero page) + when ZPSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTX_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X (lsb) ->MEM; PC+1; MP+1 + end if; + when ZPSTX_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRM_O; -- MP->MEM; X (msb) ->MEM; EI + end if; + + + -- STY $xx (zero page) + when ZPSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTY_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y (lsb) ->MEM; PC+1; MP+1 + end if; + when ZPSTY_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRM_O; -- MP->MEM; X (msb) ->MEM; EI; + end if; + + + -- STZ $xx (zero page) + when ZPSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTZ_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0 (lsb) ->MEM; PC+1; MP+1 + end if; + when ZPSTZ_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0 (msb) ->MEM; EI; + end if; + + -- ADC $xx (zero page) + when ZPADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPADC_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPADC_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xx (zero page) + when ZPSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSBC_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ZPSBC_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A - MEM(msb)\O(lsb) => A (msb\lsb); EI + end if; + + -- CMP $xx (zeropage) + when ZPCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPCMP_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPCMP_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- CPX $xx (zeropage) + when ZPCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPCPX_OP1 => + if x = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPCPX_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X - MEM(msb)\O(lsb); EI + end if; + + -- CPY $xx (zeropage) + when ZPCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPCPY_OP1 => + if x = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPCPY_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y - MEM(msb)\O(lsb); EI + end if; + + -- AND $xx (zeropage) + when ZPAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPAND_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPAND_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A = A AND MEM(msb)\O(lsb); EI + end if; + + -- ORA $xx (zeropage) + when ZPORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPORA_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPORA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A = A OR MEM(msb)\O(lsb); EI + end if; + + -- EOR $xx (zeropage) + when ZPEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPEOR_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPEOR_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A = A XOR MEM(msb)\O(lsb); EI + end if; + + -- BIT $xx (zero page) + when ZPBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPBIT_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A BIT MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZPBIT_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A BIT MEM(msb)\O(lsb); EI + end if; + + -- ASL $xx (zero page) + when ZPASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPASL_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPASL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZPASL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & SHL_A & O16_R & ORD_O; -- O SHIFT LEFT; MP-1 + end if; + when ZPASL_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZPASL_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- LSR $xx (zero page) + when ZPLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLSR_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPLSR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZPLSR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & SHR_A & O16_R & ORD_O; -- O SHIFT LEFT; MP-1 + end if; + when ZPLSR_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZPLSR_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- ROL $xx (zero page) + when ZPROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPROL_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPROL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZPROL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & ROL_A & O16_R & ORD_O; -- O ROTATE LEFT; MP-1 + end if; + when ZPROL_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZPROL_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- ROR $xx (zero page) + when ZPROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPROR_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPROR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZPROR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & ROR_A & O16_R & ORD_O; -- O ROTATE RIGHT; MP-1 + end if; + when ZPROR_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZPROR_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- INC $xx (zero page) + when ZPINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPINC_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPINC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZPINC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLD_P & INC_A & O16_R & ORD_O; -- O = O +1; MP-1 + end if; + when ZPINC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZPINC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- DEC $xx (zero page) + when ZPDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPDEC_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPDEC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (msb); + end if; + when ZPDEC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLD_P & DEC_A & O16_R & ORD_O; -- O = O -1; MP-1 + end if; + when ZPDEC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZPDEC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- TSB $xx (zero page) + when ZPTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPTSB_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPTSB_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (msb); + end if; + when ZPTSB_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O -> O; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & LDZ_P & AND_A & O16_R & ARD_O; -- A AND O -> Z; + end if; + when ZPTSB_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & NOP_P & TSB_A & O16_R & ARD_O; -- A OR O -> O; MP -1 + end if; + when ZPTSB_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; + end if; + when ZPTSB_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- TRB $xx (zero page) + when ZPTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPTRB_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZPTRB_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (msb); + end if; + when ZPTRB_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O -> O; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & LDZ_P & AND_A & O16_R & ARD_O; -- A AND O -> Z; + end if; + when ZPTRB_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & NOP_P & TRB_A & O16_R & ARD_O; -- A NAND O -> O; MP -1 + end if; + when ZPTRB_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; + end if; + when ZPTRB_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + ------------------------------------ + -- ZERO PAGE,X -- + ------------------------------------ + -- LDA $xx,X (zero page indexed) + when ZXLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXLDA_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; MP+1 + end if; + when ZXLDA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; EI + end if; + + -- LDY $xx,X (zero page indexed) + when ZXLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXLDY_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->Y; PC+1; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXLDY_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & Y16_R & EXM_O; -- MP->MEM; MEM->Y; PC+1; EI + end if; + + -- STA $xx,X (zero page indexed) + when ZXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSTA_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; MP+1 + end if; + when ZXSTA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A->MEM; EI + end if; + + -- STY $xx,X (zero page indexed) + when ZXSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSTY_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; MP +1 + end if; + when ZXSTY_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRM_O; -- MP->MEM; Y->MEM; EI + end if; + + -- STZ $xx,X (zero page indexed) + when ZXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSTZ_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; MP+1 + end if; + when ZXSTZ_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI + end if; + + -- ADC $xx,X (zero page indexed) + when ZXADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXADC_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXADC_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xx,X (zero page indexed) + when ZXSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSBC_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXSBC_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- CMP $xx,X (zero page indexed) + when ZXCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXCMP_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXCMP_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- AND $xx,X (zero page indexed) + when ZXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXAND_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXAND_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A - AND O -> A (msb/lsb); EI + end if; + + -- ORA $xx,X (zero page indexed) + when ZXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXORA_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXORA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A - OR O -> A (msb/lsb); EI + end if; + + -- EOR $xx,X (zero page indexed) + when ZXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXEOR_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXEOR_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A - XOR O -> A (msb/lsb); EI + end if; + + -- ASL $xx,X (zero page indexed) + when ZXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXASL_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZXASL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZXASL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & SHL_A & O16_R & ORD_O; -- O SHIFT LEFT; MP-1 + end if; + when ZXASL_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZXASL_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- LSR $xx,X (zero page indexed) + when ZXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXLSR_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZXLSR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZXLSR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & SHR_A & O16_R & ORD_O; -- O SHIFT LEFT; MP-1 + end if; + when ZXLSR_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZXLSR_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- ROL $xx,X (zero page indexed) + when ZXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXROL_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZXROL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZXROL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & ROL_A & O16_R & ORD_O; -- O ROTATE LEFT; MP-1 + end if; + when ZXROL_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZXROL_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- ROR $xx,X (zero page indexed) + when ZXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXROR_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZXROR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZXROR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLC_P & ROR_A & O16_R & ORD_O; -- O ROTATE RIGHT; MP-1 + end if; + when ZXROR_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZXROR_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- INC $xx,X (zero page indexed) + when ZXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXINC_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZXINC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + end if; + when ZXINC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLD_P & INC_A & O16_R & ORD_O; -- O = O +1; MP-1 + end if; + when ZXINC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZXINC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- DEC $xx,X (zero page indexed) + when ZXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXDEC_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; MP +1 + end if; + when ZXDEC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O (msb); + end if; + when ZXDEC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & DEC_M & FLD_P & DEC_A & O16_R & ORD_O; -- O = O -1; MP-1 + end if; + when ZXDEC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O(lsb)->MEM; MP +1 + end if; + when ZXDEC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O(msb)->MEM; EI + end if; + + -- BIT $xx,X (zero page indexed) + when ZXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXBIT_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A BIT MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1; EI + end if; + when ZXBIT_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A BIT MEM(msb)\O(lsb); EI + end if; + + + ------------------------------------ + -- ZERO PAGE,Y -- + ------------------------------------ + -- LDX $xx,Y (zero page indexed) + when ZYLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZYLDX_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP +1 + end if; + when ZYLDX_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O + end if; + when ZYLDX_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & ORD_O; -- O->X + end if; + + -- STX $xx,Y (zero page indexed) + when ZYSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZYSTX_OP1 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADDI & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; MP +1 + end if; + when ZYSTX_OP2 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRM_O; -- MP->MEM; X->MEM; EI + end if; + + + ------------------------------------ + -- INDIRECT -- + ------------------------------------ + -- JMP ($xxxx) (indirect) + when INJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when INJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when INJMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + when INJMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC; O->PC; EI + + -- JML ($xxxx) (indirect) + when INJML_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when INJML_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when INJML_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + when INJML_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + when INJML_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; EXT->PBR; EI + + ------------------------------------ + -- INDIRECT,Y -- + ------------------------------------ + -- LDA ($xx),Y (zeropage - indirect - indexed) + when IYLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYLDA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYLDA_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IYLDA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA ($xx),Y (zeropage - indirect - indexed) + when IYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYSTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYSTA_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; MP +1 + end if; + when IYSTA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A->MEM; EI + end if; + + -- ADC ($xx),Y (zeropage - indirect - indexed) + when IYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYADC_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IYADC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- A=A+MEM (msb)/O (lsb); EI + end if; + + -- SBC ($xx),Y (zeropage - indirect - indexed) + when IYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYSBC_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IYSBC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A=A-MEM (msb)/O (lsb); EI + end if; + + -- CMP ($xx),Y (zeropage - indirect - indexed) + when IYCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYCMP_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IYCMP_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A=A-MEM (msb)/O (lsb); EI + end if; + + -- AND ($xx),Y (zeropage - indirect - indexed) + when IYAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYAND_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IYAND_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM (msb)/O (lsb); EI + end if; + + -- ORA ($xx),Y (zeropage - indirect - indexed) + when IYORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYORA_OP3 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IYORA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM (msb)/O (lsb); EI + end if; + + -- EOR ($xx),Y (zeropage - indirect - indexed) + when IYEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYEOR_OP3 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IYEOR_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM (msb)/O (lsb); EI + end if; + + + ------------------------------------ + -- INDIRECT,X -- + ------------------------------------ + -- LDA ($xx,X) (zero page - indexed - indirect) + when IXLDA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXLDA_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IXLDA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA ($xx,X) (zero page - indexed - indirect) + when IXSTA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXSTA_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- A->MEM; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; MP +1 + end if; + when IXSTA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A->MEM; EI + end if; + + -- AND ($xx,X) (zero page - indexed - indirect) + when IXAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXAND_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- MP->MEM; A=A AND MEM; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IXAND_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM (msb)/O (lsb); EI + end if; + + -- ORA ($xx,X) (zero page - indexed - indirect) + when IXORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXORA_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- MP->MEM; A=A OR MEM; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IXORA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM (msb)/O (lsb); EI + end if; + + -- EOR ($xx,X) (zero page - indexed - indirect) + when IXEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXEOR_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IXEOR_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM (msb)/O (lsb); EI + end if; + + -- ADC ($xx,X) (zero page - indexed - indirect) + when IXADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXADC_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A + MEM; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IXADC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- A=A+MEM (msb)/O (lsb); EI + end if; + + -- SBC ($xx,X) (zero page - indexed - indirect) + when IXSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXSBC_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IXSBC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A=A-MEM (msb)/O (lsb); EI + end if; + + -- CMP ($xx,X) (zero page - indexed - indirect) + when IXCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXCMP_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI=1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when IXCMP_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM (msb)/O (lsb); EI + end if; + + -- JMP ($xxxx,X) (absolute indexed - indirect) + when IXJMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when IXJMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when IXJMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI + when IXJMP_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + when IXJMP_OP4 => q <= ORD_D &'1'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + -- JSR ($xxxx,X) (absolute indexed - indirect) + when IXJSR_OP0 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when IXJSR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1; + when IXJSR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1; + when IXJSR_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when IXJSR_OP4 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when IXJSR_OP5 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + ------------------------------------ + -- ABSOLUTE -- + ------------------------------------ + -- LDA $xxxx (absolute) + when ABLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLDA_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A (lsb); + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABLDA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- LDX $xxxx (absolute) + when ABLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLDX_OP2 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->A (lsb); + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABLDX_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- LDY $xxxx (absolute) + when ABLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLDY_OP2 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->Y (lsb); + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABLDY_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & Y16_R & EXM_O; -- MP->MEM; MEM->Y; PC+1 + end if; + + -- STA $xxxx (absolute) + when ABSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTA_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A (lsb) ->MEM; + end if; + when ABSTA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A (msb) ->MEM; + end if; + + -- STX $xxxx (absolute) + when ABSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTX_OP2 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X (lsb) ->MEM; + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X (lsb) ->MEM; + end if; + when ABSTX_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRM_O; -- MP->MEM; X (msb) ->MEM; + end if; + + -- STY $xxxx (absolute) + when ABSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTY_OP2 => + if x = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y (lsb) ->MEM; + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y (lsb) ->MEM; + end if; + when ABSTY_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRM_O; -- MP->MEM; Y (msb) ->MEM; + end if; + + -- STZ $xxxx (absolute) + when ABSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTZ_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0 (lsb) ->MEM; + end if; + when ABSTZ_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0 (msb) ->MEM; + end if; + + -- JMP $xxxx (absolute) + when ABJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + -- JSR $xxxx (absolute) + when ABJSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1; + when ABJSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1; + when ABJSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + -- BIT $xxxx (absolute) + when ABBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABBIT_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABBIT_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; BIT + end if; + + -- ADC $xxxx (absolute) + when ABADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABADC_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABADC_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xxxx (absolute) + when ABSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSBC_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABSBC_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A = A - MEM(msb)\O(lsb); EI + end if; + + -- CMP $xxxx (absolute) + when ABCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABCMP_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABCMP_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- CPX $xxxx (absolute) + when ABCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABCPX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABCPX_OP2 => + if x = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABCPX_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM(msb)\O(lsb); EI + end if; + + -- CPY $xxxx (absolute) + when ABCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABCPY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABCPY_OP2 => + if x = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- X-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABCPY_OP3 => + if x = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM(msb)\O(lsb); EI + end if; + + -- ORA $xxxx (absolute) + when ABORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABORA_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABORA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM(msb)\O(lsb); EI + end if; + + -- AND $xxxx (absolute) + when ABAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABAND_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABAND_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM(msb)\O(lsb); EI + end if; + + -- EOR $xxxx (absolute) + when ABEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABEOR_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ABEOR_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM(msb)\O(lsb); EI + end if; + + -- ASL $xxxx (absolute) + when ABASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABASL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABASL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O (lsb) SHIFT LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when ABASL_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & SHL_A & O16_R & ORD_O; -- O (msb\lsb) SHIFT LEFT -> O; MP-1 + end if; + when ABASL_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when ABASL_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- LSR $xxxx (absolute) + when ABLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLSR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABLSR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O (lsb) SHIFT RIGHT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when ABLSR_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & SHR_A & O16_R & ORD_O; -- O (msb\lsb) SHIFT RIGHT -> O; MP-1 + end if; + when ABLSR_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when ABLSR_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- ROL $xxxx (absolute) + when ABROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABROL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABROL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O (lsb) ROTATE LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when ABROL_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & ROL_A & O16_R & ORD_O; -- O (msb\lsb) ROTATE LEFT -> O; MP-1 + end if; + when ABROL_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when ABROL_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- ROR $xxxx (absolute) + when ABROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABROR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABROR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O (lsb) ROTATE RIGHT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when ABROR_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & ROR_A & O16_R & ORD_O; -- O (msb\lsb) ROTATE RIGHT -> O; MP-1 + end if; + when ABROR_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when ABROR_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- INC $xxxx (absolute) + when ABINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABINC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABINC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 -> O (lsb) + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when ABINC_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLD_P & INC_A & O16_R & ORD_O; -- O = O +1 (msb\lsb) -> O; MP-1 + end if; + when ABINC_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when ABINC_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- DEC $xxxx (absolute) + when ABDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABDEC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ABDEC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 -> O (lsb) + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when ABDEC_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLD_P & DEC_A & O16_R & ORD_O; -- O = O -1 (msb\lsb) -> O; MP-1 + end if; + when ABDEC_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP+1 + when ABDEC_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- TSB $xxxx (absolute) + when ABTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABTSB_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + end if; + when ABTSB_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> O + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; + end if; + when ABTSB_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O => O + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & O16_R & ARD_O; -- A AND O -> O + end if; + when ABTSB_OP5 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & NOP_P & TSB_A & O16_R & ARD_O; -- A OR O => O; MP-1 + end if; + when ABTSB_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP+1 + when ABTSB_OP7 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- TRB $xxxx (absolute) + when ABTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABTRB_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + end if; + when ABTRB_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> O + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; + end if; + when ABTRB_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O => O + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & O16_R & ARD_O; -- A AND O -> O + end if; + when ABTRB_OP5 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & NOP_P & TRB_A & O16_R & ARD_O; -- A NAND O => O; MP-1 + end if; + when ABTRB_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP+1 + when ABTRB_OP7 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + ------------------------------------ + -- ABSOLUTE,X -- + ------------------------------------ + -- DMUX: ALU operand #2 multiplexer + -- | AI: effective address is indexed (X or Y) + -- | | VP: vector pull + -- | | | ML: memory lock + -- | | | | VPA: vali program address + -- | | | | | VDA: valid data address + -- | | | | | | EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction) + -- | | | | | | | W: read/write control + -- | | | | | | | | CLI: clear interrupt request + -- | | | | | | | | | PD: PC/MP address output multiplexer select + -- | | | | | | | | | | PCR: register PC (program counter) + -- | | | | | | | | | | | MPR: register MP (memory pointer) + -- | | | | | | | | | | | | P_OP: register P set/reset bit + -- | | | | | | | | | | | | | ALUOP: ALU operation + -- | | | | | | | | | | | | | | REGOP: registers load/increment/decrement etc. + -- | | | | | | | | | | | | | | | RSEL: registers output multiplexer select + -- | | | | | | | | | | | | | | | | + -- | | | | | | | | | | | | | | | | + -- DMUX AI VP ML VPA VDA EI W CLI PD PCR MPR P_OP ALUOP REGOP RSEL + -- LDA $xxxx,X (absolute indexed) + when AXLDA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXLDA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXLDA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXLDA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; EI + end if; + + -- LDY $xxxx,X (absolute indexed) + when AXLDY_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXLDY_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXLDY_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->Y; EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXLDY_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & Y16_R & EXM_O; -- MP->MEM; MEM->Y; EI + end if; + + -- STA $xxxx,X (absolute indexed) + when AXSTA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXSTA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXSTA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; MP+1 + end if; + when AXSTA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A->MEM; MP+1 + end if; + + -- STZ $xxxx,X (absolute indexed) + when AXSTZ_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXSTZ_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXSTZ_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; MP+1 + end if; + when AXSTZ_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI + end if; + + -- ADC $xxxx,X (absolute indexed) + when AXADC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXADC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXADC_OP2 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AXADC_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xxxx,X (absolute indexed) + when AXSBC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXSBC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXSBC_OP2 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AXSBC_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A - MEM(msb)\O(lsb)=> A (msb\lsb); EI + end if; + + -- CMP $xxxx,X (absolute indexed) + when AXCMP_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXCMP_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXCMP_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AXCMP_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- INC $xxxx,X (absolute indexed) + when AXINC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXINC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXINC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXINC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 -> O (lsb) + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when AXINC_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLD_P & INC_A & O16_R & ORD_O; -- O = O +1 (msb\lsb) -> O; MP-1 + end if; + when AXINC_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when AXINC_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- DEC $xxxx,X (absolute indexed) + when AXDEC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXDEC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXDEC_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXDEC_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 -> O (lsb) + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when AXDEC_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLD_P & DEC_A & O16_R & ORD_O; -- O = O -1 (msb\lsb) -> O; MP-1 + end if; + when AXDEC_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when AXDEC_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- ASL $xxxx,X (absolute indexed) + when AXASL_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXASL_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXASL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXASL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O (lsb) SHIFT LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when AXASL_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & SHL_A & O16_R & ORD_O; -- O (msb\lsb) SHIFT LEFT -> O; MP-1 + end if; + when AXASL_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when AXASL_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- LSR $xxxx,X (absolute indexed) + when AXLSR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXLSR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXLSR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXLSR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O (lsb) SHIFT RIGHT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when AXLSR_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & SHR_A & O16_R & ORD_O; -- O (msb\lsb) SHIFT RIGHT -> O; MP-1 + end if; + when AXLSR_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when AXLSR_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- ROL $xxxx,X (absolute indexed) + when AXROL_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXROL_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXROL_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXROL_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O (lsb) ROTATE LEFT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when AXROL_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & ROL_A & O16_R & ORD_O; -- O (msb\lsb) ROTATE LEFT -> O; MP-1 + end if; + when AXROL_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when AXROL_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- ROR $xxxx,X (absolute indexed) + when AXROR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXROR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXROR_OP2 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AXROR_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O (lsb) ROTATE RIGHT; + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + end if; + when AXROR_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & DEC_M & FLC_P & ROR_A & O16_R & ORD_O; -- O (msb\lsb) ROTATE RIGHT -> O; MP-1 + end if; + when AXROR_OP5 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O (lsb) ->MEM; MP +1 + when AXROR_OP6 => q <= NOP_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & OMD_O; -- MP->MEM; O (msb) ->MEM; + + -- AND $xxxx,X (absolute indexed) + when AXAND_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXAND_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXAND_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & NOP_R & ARD_O; -- A AND EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AXAND_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & NOP_R & ARD_O; -- A AND MEM(msb)\O(lsb); EI + end if; + + -- ORA $xxxx,X (absolute indexed) + when AXORA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXORA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXORA_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & NOP_R & ARD_O; -- A OR EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AXORA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & NOP_R & ARD_O; -- A OR MEM(msb)\O(lsb); EI + end if; + + -- EOR $xxxx,X (absolute indexed) + when AXEOR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXEOR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXEOR_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & NOP_R & ARD_O; -- A XOR EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AXEOR_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & NOP_R & ARD_O; -- A XOR MEM(msb)\O(lsb); EI + end if; + + -- BIT $xxxx,X (absolute indexed) + when AXBIT_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXBIT_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXBIT_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A BIT EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AXBIT_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A BIT MEM(msb)\O(lsb); EI + end if; + + ------------------------------------ + -- ABSOLUTE,Y -- + ------------------------------------ + -- LDA $xxxx,Y (absolute indexed) + when AYLDA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYLDA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYLDA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AYLDA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; EI + end if; + + -- LDX $xxxx,Y (absolute indexed) + when AYLDX_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYLDX_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYLDX_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AYLDX_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & EXM_O; -- MP->MEM; MEM->X; EI + end if; + + -- STA $xxxx,Y (absolute indexed) + when AYSTA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYSTA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYSTA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; MP+1 + end if; + when AYSTA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A->MEM; MP+1 + end if; + + -- ADC $xxxx,Y (absolute indexed) + when AYADC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYADC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYADC_OP2 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AYADC_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xxxx,Y (absolute indexed) + when AYSBC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYSBC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYSBC_OP2 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AYSBC_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A - MEM(msb)\O(lsb)=> A (msb\lsb); EI + end if; + + -- CMP $xxxx,Y (absolute indexed) + when AYCMP_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYCMP_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AYCMP_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AYCMP_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- AND $xxxx,Y (absolute indexed) + when AYAND_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYAND_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYAND_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & NOP_R & ARD_O; -- A AND EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AYAND_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & NOP_R & ARD_O; -- A AND MEM(msb)\O(lsb); EI + end if; + + -- ORA $xxxx,Y (absolute indexed) + when AYORA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYORA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYORA_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & NOP_R & ARD_O; -- A OR EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AYORA_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & NOP_R & ARD_O; -- A OR MEM(msb)\O(lsb); EI + end if; + + -- EOR $xxxx,Y (absolute indexed) + when AYEOR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYEOR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYEOR_OP2 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & NOP_R & ARD_O; -- A XOR EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AYEOR_OP3 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & NOP_R & ARD_O; -- A XOR MEM(msb)\O(lsb); EI + end if; + + + -------------------------------------- + -- ABSOLUTE LONG -- + -------------------------------------- + -- JML $xxxxxx (absolute long) + when ABJML_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJML_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ABJML_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; EXT->PBR; EI + + -- JSL $xxxxxx (absolute long) + when ABJSL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJSL_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ABJSL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- PBR->S; SP-1; + when ABJSL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1; + when ABJSL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1; + when ABJSL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; EXT->PBR; EI + + ------------------------------------ + -- RELATIVE -- + ------------------------------------ + -- BRA xx + when BRA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BEQ xx + when BEQ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BNE xx + when BNE_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BCC xx + when BCC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BCS xx + when BCS_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BVC xx + when BVC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BVS xx + when BVS_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BPL xx + when BPL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BMI xx + when BMI_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + ----------------------------------------- + -- RELATIVE LONG -- + ----------------------------------------- + -- BRL xxxx + when BRL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb offset); + when BRL_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRL_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset + + ------------------------------- + -- STACK -- + ------------------------------- + -- PEA xxxx + when PEA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when PEA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; PC+1 + when PEA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & OMD_O; -- O (msb) ->S; SP-1; + when PEA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ORD_O; -- O (lsb) ->S; SP-1; + + -- PEI xx + when PEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when PEI_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when PEI_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when PEI_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & OMD_O; -- O (msb) ->S; SP-1; + when PEI_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ORD_O; -- O (lsb) ->S; SP-1; + + -- PER xxxx + when PER_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb offset); + when PER_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (msb offset) + when PER_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & SWC_A & O16_R & PCR_O; -- O = O + PC + when PER_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & OMD_O; -- O (msb) ->S; SP-1; + when PER_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ORD_O; -- O (lsb) ->S; SP-1; + + ---------------------------------- + -- DIRECT,Y -- + ---------------------------------- + -- LDA [$xx],Y (zeropage - direct long - indexed) + when DYLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYLDA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYLDA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYLDA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MPR MSB + when DYLDA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYLDA_OP5 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DYLDA_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA [$xx],Y (zeropage - indirect long - indexed) + when DYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYSTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYSTA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYSTA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYSTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYSTA_OP5 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; MP +1 + end if; + when DYSTA_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A->MEM; EI + end if; + + -- ADC [$xx],Y (zeropage - indirect long - indexed) + when DYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYADC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYADC_OP5 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DYADC_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- A=A+MEM (msb)/O (lsb); EI + end if; + + -- SBC [$xx],Y (zeropage - indirect long - indexed) + when DYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYSBC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYSBC_OP5 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DYSBC_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A=A-MEM (msb)/O (lsb); EI + end if; + + -- CMP [$xx],Y (zeropage - indirect long - indexed) + when DYCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYCMP_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYCMP_OP5 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DYCMP_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A=A-MEM (msb)/O (lsb); EI + end if; + + -- AND [$xx],Y (zeropage - indirect long - indexed) + when DYAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYAND_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYAND_OP5 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DYAND_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM (msb)/O (lsb); EI + end if; + + -- ORA [$xx],Y (zeropage - indirect long - indexed) + when DYORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYORA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYORA_OP5 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DYORA_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM (msb)/O (lsb); EI + end if; + + -- EOR [$xx],Y (zeropage - indirect long - indexed) + when DYEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYEOR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYEOR_OP5 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DYEOR_OP6 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM (msb)/O (lsb); EI + end if; + + -------------------------------- + -- DIRECT -- + -------------------------------- + -- LDA [$xx] (zeropage - direct long) + when DILDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DILDA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DILDA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DILDA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DILDA_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DILDA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA [$xx] (zeropage - indirect long) + when DISTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DISTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DISTA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DISTA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DISTA_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; MP +1 + end if; + when DISTA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A->MEM; EI + end if; + + -- ADC [$xx] (zeropage - indirect long) + when DIADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIADC_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DIADC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- A=A+MEM (msb)/O (lsb); EI + end if; + + -- SBC [$xx] (zeropage - indirect long) + when DISBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DISBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DISBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DISBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DISBC_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DISBC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A=A-MEM (msb)/O (lsb); EI + end if; + + -- CMP [$xx] (zeropage - indirect long) + when DICMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DICMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DICMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DICMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DICMP_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DICMP_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A=A-MEM (msb)/O (lsb); EI + end if; + + -- AND [$xx] (zeropage - indirect long) + when DIAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIAND_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DIAND_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM (msb)/O (lsb); EI + end if; + + -- ORA [$xx] (zeropage - indirect long) + when DIORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIORA_OP4 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DIORA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM (msb)/O (lsb); EI + end if; + + -- EOR [$xx] (zeropage - indirect long) + when DIEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIEOR_OP4 => + if m = '1' then + q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when DIEOR_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM (msb)/O (lsb); EI + end if; + + ---------------------------------------- + -- ABSOLUTE LONG -- + ---------------------------------------- + -- LDA $xxxxxx (absolute long) + when ALLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALLDA_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A (lsb); + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when ALLDA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA $xxxxxx (absolute long) + when ALSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALSTA_OP3 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A (lsb) ->MEM; + end if; + when ALSTA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A (msb) ->MEM; + end if; + + -- ADC $xxxxxx (absolute long) + when ALADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALADC_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ALADC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xxxxxx (absolute long) + when ALSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALSBC_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ALSBC_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A = A - MEM(msb)\O(lsb); EI + end if; + + -- CMP $xxxxxx (absolute long) + when ALCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALCMP_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ALCMP_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- ORA $xxxxxx (absolute long) + when ALORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALORA_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ALORA_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM(msb)\O(lsb); EI + end if; + + -- AND $xxxxxx (absolute long) + when ALAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALAND_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ALAND_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM(msb)\O(lsb); EI + end if; + + -- EOR $xxxxxx (absolute long) + when ALEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALEOR_OP3 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when ALEOR_OP4 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM(msb)\O(lsb); EI + end if; + + ------------------------------------------ + -- ABSOLUTE LONG,X -- + ------------------------------------------ + -- LDA $xxxxxx,X (absolute long indexed X) + when AILDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AILDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AILDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AILDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AILDA_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A (lsb); + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when AILDA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA $xxxxxx,X (absolute long indexed X) + when AISTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AISTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AISTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AISTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AISTA_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A (lsb) ->MEM; + end if; + when AISTA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A (msb) ->MEM; + end if; + + -- ADC $xxxxxx,X (absolute long indexed X) + when AIADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIADC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIADC_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AIADC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xxxxxx,X (absolute long indexed X) + when AISBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AISBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AISBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AISBC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AISBC_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AISBC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A = A - MEM(msb)\O(lsb); EI + end if; + + -- CMP $xxxxxx,X (absolute long indexed X) + when AICMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AICMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AICMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AICMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AICMP_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AICMP_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- ORA $xxxxxx,X (absolute long indexed X) + when AIORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIORA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIORA_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AIORA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM(msb)\O(lsb); EI + end if; + + -- AND $xxxxxx,X (absolute long indexed X) + when AIAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIAND_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIAND_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AIAND_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM(msb)\O(lsb); EI + end if; + + -- EOR $xxxxxx,X (absolute long indexed X) + when AIEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIEOR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIEOR_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when AIEOR_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM(msb)\O(lsb); EI + end if; + + ---------------------------------------- + -- STACK RELATIVE -- + ---------------------------------------- + -- LDA $xx,S (S + offset) + when SRLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRLDA_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when SRLDA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA $xx,S (S + offset) + when SRSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRSTA_OP1 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A (lsb) ->MEM; + end if; + when SRSTA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A (msb) ->MEM; + end if; + + -- ADC $xx,S (S + offset) + when SRADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRADC_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SRADC_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC $xx,S (S + offset) + when SRSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRSBC_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SRSBC_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A = A - MEM(msb)\O(lsb); EI + end if; + + -- CMP $xx,S (S + offset) + when SRCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRCMP_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SRCMP_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- ORA $xx,S (S + offset) + when SRORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRORA_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SRORA_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM(msb)\O(lsb); EI + end if; + + -- AND $xx,S (S + offset) + when SRAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRAND_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SRAND_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM(msb)\O(lsb); EI + end if; + + -- EOR $xx,S (S + offset) + when SREOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SREOR_OP1 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SREOR_OP2 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM(msb)\O(lsb); EI + end if; + + ------------------------------------------------- + -- STACK RELATIVE INDEXED Y -- + ------------------------------------------------- + -- LDA ($xx,S),Y + when SYLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYLDA_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb); MP+1 + end if; + when SYLDA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & EXM_O; -- MP->MEM; MEM->A; PC+1 + end if; + + -- STA ($xx,S),Y + when SYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYSTA_OP4 => + if m = '1' then + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A (lsb) ->MEM; + end if; + when SYSTA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARM_O; -- MP->MEM; A (msb) ->MEM; + end if; + + -- ADC ($xx,S),Y + when SYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYADC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYADC_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SYADC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & A16_R & ARD_O; -- MEM(msb)\O(lsb) + A => A (msb\lsb); PC +1; EI + end if; + + -- SBC ($xx,S),Y + when SYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYSBC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYSBC_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SYSBC_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & A16_R & ARD_O; -- A = A - MEM(msb)\O(lsb); EI + end if; + + -- CMP ($xx,S),Y + when SYCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYCMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYCMP_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SYCMP_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A - MEM(msb)\O(lsb); EI + end if; + + -- ORA ($xx,S),Y + when SYORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYORA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYORA_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SYORA_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & A16_R & ARD_O; -- A=A OR MEM(msb)\O(lsb); EI + end if; + + -- AND ($xx,S),Y + when SYAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYAND_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYAND_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SYAND_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & A16_R & ARD_O; -- A=A AND MEM(msb)\O(lsb); EI + end if; + + -- EOR ($xx,S),Y + when SYEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYEOR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYEOR_OP4 => + if m = '1' then + q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + else + q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM=>O (lsb); MP +1; + end if; + when SYEOR_OP5 => + if m = '1' then + q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + else + q <= EXM_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & A16_R & ARD_O; -- A=A XOR MEM(msb)\O(lsb); EI + end if; + + ------------------------------------ + -- MOVE BLOCK -- + ------------------------------------ + when MBMVN_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (source) + when MBMVN_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADXR & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; read byte + when MBMVN_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (destination) + when MBMVN_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADYR & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O->MEM; write byte + when MBMVN_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MVN_R & EXT_O; -- X +1; Y +1; A -1; + when MBMVN_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & DE3_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- check for A = $FFFF + + when MBMVP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (source) + when MBMVP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADXR & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; read byte + when MBMVP_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (destination) + when MBMVP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADYR & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O->MEM; write byte + when MBMVP_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MVP_R & EXT_O; -- X -1; Y -1; A -1; + when MBMVP_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & DE3_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- check for A = $FFFF + + ---------------------------------- + -- MULTIPLY -- + ---------------------------------- + when MPU_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MUI_R & EXT_O; -- load A/B & X on multiplier + when MPU_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MUS_R & EXT_O; -- start multiplication (unsigned) + when MPU_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & MUF_P & NOP_A & MUL_R & EXT_O; -- load result on A/B and X + when MPU_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- EI + + when MPS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MUI_R & EXT_O; -- load A/B & X on multiplier + when MPS_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MSS_R & EXT_O; -- start multiplication (signed) + when MPS_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & MSF_P & NOP_A & MUL_R & EXT_O; -- load result on A/B and X + when MPS_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- EI + + when others => q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + + end case; + else + ----------------------------------- + -- EMULATION MODE -- + ----------------------------------- + -- DMUX: ALU operand #2 multiplexer + -- | AI: effective address is indexed (X or Y) + -- | | VP: vector pull + -- | | | ML: memory lock + -- | | | | VPA: vali program address + -- | | | | | VDA: valid data address + -- | | | | | | EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction) + -- | | | | | | | W: read/write control + -- | | | | | | | | CLI: clear interrupt request + -- | | | | | | | | | PD: PC/MP address output multiplexer select + -- | | | | | | | | | | PCR: register PC (program counter) + -- | | | | | | | | | | | MPR: register MP (memory pointer) + -- | | | | | | | | | | | | P_OP: register P set/reset bit + -- | | | | | | | | | | | | | ALUOP: ALU operation + -- | | | | | | | | | | | | | | REGOP: registers load/increment/decrement etc. + -- | | | | | | | | | | | | | | | RSEL: registers output multiplexer select + -- | | | | | | | | | | | | | | | | + -- | | | | | | | | | | | | | | | | + case a is -- DMUX AI VP ML VPA VDA EI W CLI PD PCR MPR P_OP ALUOP REGOP RSEL + ------------------------------------ + -- IMPLIED -- + ------------------------------------ + -- BRK + when BRK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & IN2_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- if no interrupt request then PC=PC+2 + when BRK_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1 + when BRK_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1 + when BRK_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & SDW_R & PRD_O; -- VEC->MP; SEI; CLD; 1->B (stack); P->S; + when BRK_OP4 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; interrupt ack; VP + when BRK_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP + + -- COP + when COP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & IN2_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC=PC+2 + when COP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1 + when COP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRL &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1 + when COP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & VEC_M & SID_P & NOP_A & SDW_R & PRD_O; -- VEC->MP; SEI; CLD; 1->B (stack); P->S; + when COP_OP4 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'0'& RDE &'1'& ADMP & LSB_PC & INC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCL; MP+1; interrupt ack; VP + when COP_OP5 => q <= ORD_D &'0'&'1'&'0'&'0'&'1'&'1'& RDE &'1'& ADMP & MSB_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->PCH; EI; VP + + -- NOP + when NOP_OP0 => q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + + -- CLC + when CLC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLC_P & NOP_A & NOP_R & EXT_O; -- 0->C; EI + + -- SEC + when SEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEC_P & NOP_A & NOP_R & EXT_O; -- 1->C; EI + + -- CLI + when CLI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLI_P & NOP_A & NOP_R & EXT_O; -- 0->I; EI + + -- SEI + when SEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SEI_P & NOP_A & NOP_R & EXT_O; -- 1->I; EI + + -- CLV + when CLV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLV_P & NOP_A & NOP_R & EXT_O; -- 0->V; EI + + -- CLD + when CLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & CLD_P & NOP_A & NOP_R & EXT_O; -- 0->D; EI + + -- SED + when SED_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & SED_P & NOP_A & NOP_R & EXT_O; -- 1->D; EI + + -- TAX + when TAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & ARD_O; -- A->X; EI + + -- TXA + when TXA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & XRD_O; -- X->A; EI + + -- TAY + when TAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & ARD_O; -- A->Y; EI + + -- TYA + when TYA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & YRD_O; -- Y->A; EI + + -- TXY + when TXY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & XRD_O; -- X->Y; EI + + -- TYX + when TYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & YRD_O; -- Y->X; EI + + -- TCD + when TCD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & D16_R & ARD_O; -- C->D; EI + + -- TDC + when TDC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & DRD_O; -- D->C; EI + + -- TXS + when TXS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & S16_R & XRD_O; -- X->S; EI + + -- TSX + when TSX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & X16_R & SRD_O; -- S->X; EI + + -- INC A + when INC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & ALL_R & ARD_O; -- A+1; EI + + -- DEC A + when DEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & ALL_R & ARD_O; -- A-1; EI + + -- INX + when INX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & XLL_R & XRD_O; -- X+1; EI + + -- DEX + when DEX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & XLL_R & XRD_O; -- X-1; EI + + -- INY + when INY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & INC_A & YLL_R & YRD_O; -- Y+1; EI + + -- DEY + when DEY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DEC_A & YLL_R & YRD_O; -- Y-1; EI + + -- PHP + when PHP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PRD_O; -- P->S; SP-1; EI + + -- PHD + when PHD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & DRM_O; -- D (msb) ->S; SP-1; + when PHD_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & DRD_O; -- D (lsb) ->S; SP-1; EI + + -- PHA + when PHA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A->S; SP-1; EI + + -- PHX + when PHX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1; EI + + -- PHY + when PHY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- X->S; SP-1; EI + + -- PHR (in emulation mode PHR pushes ALWAYS XY 8 bit registers and A as 16 bit register) + when PHR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARM_O; -- A(msb)->S; SP-1; (two byte instruction) + when PHR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A(lsb)->S; SP-1; (two byte instruction) + when PHR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1; (two byte instruction) + when PHR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & SDW_R & YRD_O; -- Y->S; SP-1; EI (two byte instruction) + + -- PLP + when PLP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & NOP_R & EXT_O; -- S->P; EI + + -- SAV (in emulation mode SAV pushes ALWAYS XY 8 bit registers and A as 16 bit register) + when SAV_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARM_O; -- A(msb)->S; SP-1; (two byte instruction) + when SAV_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ARD_O; -- A(lsb)->S; SP-1; (two byte instruction) + when SAV_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & XRD_O; -- X->S; SP-1; (two byte instruction) + when SAV_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & YRD_O; -- Y->S; SP-1; (two byte instruction) + when SAV_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & BRD_O; -- B->S; SP-1; (two byte instruction) + when SAV_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & DRM_O; -- D (msb) ->S; SP-1; (two byte instruction) + when SAV_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & SDW_R & DRD_O; -- D (lsb) ->S; SP-1; (two byte instruction) + + -- RST (in emulation mode RST pulls ALWAYS AXY 8 bit registers) + when RST_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 (two byte instruction) + when RST_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OSU_R & EXT_O; -- S->O (lsb); SP+1 + when RST_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & DLS_R & EXM_O; -- S msb) & O (lsb) -> D;/SP+1 + when RST_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & BLS_R & EXT_O; -- S->B; SP +1 + when RST_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYU_R & EXT_O; -- S->Y; (two byte instruction) + when RST_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXU_R & EXT_O; -- S->X; (two byte instruction) + when RST_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SAU_R & EXT_O; -- S->A (lsb); SP+1 (two byte instruction) + when RST_OP7 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & ALM_R & EXT_O; -- S->A (msb); EI (two byte instruction) + + -- PLD + when PLD_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLD_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OSU_R & EXT_O; -- S->O (lsb); SP+1 + when PLD_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & D16_R & EXM_O; -- S msb) & O (lsb) -> D; + + -- PLA + when PLA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- S->A; EI + + -- PLX + when PLX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- S->X; EI + + -- PLY + when PLY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- S->Y; EI + + -- PLR (in emulation mode PLR pulls ALWAYS XY 8 bit registers and A as 16 bit register) + when PLR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 (two byte instruction) + when PLR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SYU_R & EXT_O; -- S->Y; (two byte instruction) + when PLR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SXU_R & EXT_O; -- S->X; (two byte instruction) + when PLR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SAU_R & EXT_O; -- S->A (lsb); SP+1 (two byte instruction) + when PLR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & WDC_P & NOP_A & ALM_R & EXT_O; -- S->A (msb); EI (two byte instruction) + + -- RTI + when RTI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- PC->MEM; MP=01XX (STACK) + when RTI_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & PLD_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; MEM->P; SP +1 + when RTI_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB PC->O; SP +1; + when RTI_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1; + when RTI_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; MSB->MP; EI + + -- RTS + when RTS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1 + when RTS_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O; + when RTS_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1; + when RTS_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC + when RTS_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI + + -- ASL (A) + when ASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHL_A & ALL_R & ARD_O; -- A SHIFT LEFT; EI + + -- LSR (A) + when LSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHR_A & ALL_R & ARD_O; -- A SHIFT RIGHT; EI + + -- ROL (A) + when ROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROL_A & ALL_R & ARD_O; -- A ROTATE LEFT; EI + + -- ROR (A) + when ROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROR_A & ALL_R & ARD_O; -- A ROTATE RIGHT; EI + + -- EXT (A) + when EXT_OP0 => q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- NOP; EI (two byte instruction) + + -- NEG (A) + when NEG_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NEG_A & ALL_R & ARD_O; -- negates A (lsb); EI (two byte instruction) + + -- XYX + when XYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O; (two byte instruction) + when XYX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLL_R & YRD_O; -- Y->X; + when XYX_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NOP_A & YLL_R & ORD_O; -- O->Y; EI + + -- XAX + when XAX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O; (two byte instruction) + when XAX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & XLL_R & ARD_O; -- A->X; + when XAX_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NOP_A & ALL_R & ORD_O; -- O->A; EI + + -- XAY + when XAY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & YRD_O; -- Y->O; (two byte instruction) + when XAY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & YLL_R & ARD_O; -- A->Y; + when XAY_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLW_P & NOP_A & ALL_R & ORD_O; -- O->A; EI + + -- TCS + when TCS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & S16_R & ARD_O; -- C->S; + + -- TSC + when TSC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & SRD_O; -- S->C; + + -- XCE + when XCE_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & XCE_P & NOP_A & NOP_R & EXT_O; -- E-<>C; EI + + -- WDM + when WDM_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDM_P & NOP_A & NOP_R & EXT_O; -- set two byte instruction bit + + -- PHK + when PHK_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- K->S; SP-1; EI + + -- PHB + when PHB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & BRD_O; -- B->S; SP-1; EI + + -- PLB + when PLB_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MP; SP+1 + when PLB_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADSP & NOP_PC & NOP_M & FLD_P & NOP_A & BLD_R & EXT_O; -- S->B; EI + + -- RTL + when RTL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1 + when RTL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; LSB->O; + when RTL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- SP->MEM; SP +1 + when RTL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MSB->O; + when RTL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SUP_R & EXT_O; -- MP->MEM; SP +1; + when RTL_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADSP & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; MEM->PBR; + when RTL_OP6 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI + + -- XBA + when XBA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & NOP_A & A16_R & ARM_O; -- swap A<->B; EI + + -- WAI + when WAI_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & WAI_R & EXT_O; -- set WAI flipflop + when WAI_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + + -- STP + when STP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & STP_R & EXT_O; -- set STP flipflop + when STP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + + ------------------------------------ + -- IMMEDIATE -- + ------------------------------------ + -- LDA #xx + when IMLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MEM->A; PC +1; EI + + -- LDX #xx + when IMLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MEM->X; PC +1; EI + + -- LDY #yy + when IMLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MEM->Y; PC +1; EI + + -- ADC #xx (immediate) + when IMADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; PC +1; EI + when IMADC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALL_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI + + -- SBC #xx (immediate) + when IMSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A-EXT; PC +1; EI + when IMSBC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALL_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI + + -- CMP #xx (immediate) + when IMCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; PC +1; EI + + -- CPX #xx (immediate) + when IMCPX_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; PC +1; EI + + -- CPY #xx (immediate) + when IMCPY_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; PC +1; EI + + -- AND #xx (immediate) + when IMAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A AND MEM -> A; PC +1; + + -- ORA #xx (immediate) + when IMORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A OR MEM -> A; PC +1; + + -- EOR #xx (immediate) + when IMEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A XOR MEM -> A; PC +1; + + -- BIT #xx (immediate) + when IMBIT_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & LDZ_P & BIT_A & NOP_R & ARD_O; -- A AND MEM; PC +1; + + -- SEP #xx (immediate) + when IMSEP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & SEP_P & OR_A & ALL_R & ARD_O; -- P = P OR MEM; PC +1; + + -- REP #xx (immediate) + when IMREP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & REP_P & OR_A & ALL_R & ARD_O; -- P = P AND NOT MEM; PC +1; + + ------------------------------------ + -- ZERO PAGE -- + ------------------------------------ + -- LDA $xx (zero page) + when ZPLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & INC_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; PC+1; EI + + -- LDX $xx (zero page) + when ZPLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & INC_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; PC+1; EI + + -- LDY $xx (zero page) + when ZPLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & INC_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->Y; PC+1; EI + + -- STA $xx (zero page) + when ZPSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1; EI + + -- STX $xx (zero page) + when ZPSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1; EI + + -- STY $xx (zero page) + when ZPSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1; EI + + -- STZ $xx (zero page) + when ZPSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1; EI + + -- ADC $xx (zero page) + when ZPADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+MEM; EI + when ZPADC_OP2 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALL_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI + + -- SBC $xx (zero page) + when ZPSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A-MEM; EI + when ZPSBC_OP2 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALL_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI + + -- CMP $xx (zeropage) + when ZPCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI + + -- CPX $xx (zeropage) + when ZPCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPCPX_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; EI + + -- CPY $xx (zeropage) + when ZPCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPCPY_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; EI + + -- AND $xx (zeropage) + when ZPAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + + -- ORA $xx (zeropage) + when ZPORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + + -- EOR $xx (zeropage) + when ZPEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + + -- BIT $xx (zero page) + when ZPBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPBIT_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & INC_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1; EI + + -- ASL $xx (zero page) + when ZPASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPASL_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPASL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT; + when ZPASL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + -- LSR $xx (zero page) + when ZPLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPLSR_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPLSR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT; + when ZPLSR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + -- ROL $xx (zero page) + when ZPROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPROL_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPROL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT; + when ZPROL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + -- ROR $xx (zero page) + when ZPROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPROR_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPROR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT; + when ZPROR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + -- INC $xx (zero page) + when ZPINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPINC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPINC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 + when ZPINC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + -- DEC $xx (zero page) + when ZPDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPDEC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPDEC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 + when ZPDEC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + -- TSB $xx (zero page) + when ZPTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPTSB_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPTSB_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z + when ZPTSB_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O -> O + when ZPTSB_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + -- TRB $xx (zero page) + when ZPTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when ZPTRB_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI + when ZPTRB_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z + when ZPTRB_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O -> O + when ZPTRB_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI + + ------------------------------------ + -- ZERO PAGE,X -- + ------------------------------------ + -- LDA $xx,X (zero page indexed) + when ZXLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- LDY $xx,X (zero page indexed) + when ZXLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->Y; EI + + -- STA $xx,X (zero page indexed) + when ZXSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + + -- STY $xx,X (zero page indexed) + when ZXSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; EI + + -- STZ $xx,X (zero page indexed) + when ZXSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; X->MEM; EI + + -- ADC $xx,X (zero page indexed) + when ZXADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+MEM; EI + when ZXADC_OP2 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALL_R & ARD_O; -- A=A+BCD ADJ (DAA); EI + + -- SBC $xx,X (zero page indexed) + when ZXSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A-MEM; EI + when ZXSBC_OP2 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALL_R & ARD_O; -- A=A-BCD ADJ (DAS); EI + + -- CMP $xx,X (zero page indexed) + when ZXCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI + + -- AND $xx,X (zero page indexed) + when ZXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + + -- ORA $xx,X (zero page indexed) + when ZXORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + + -- EOR $xx,X (zero page indexed) + when ZXEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + + -- ASL $xx,X (zero page indexed) + when ZXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXASL_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + when ZXASL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT; + when ZXASL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- LSR $xx,X (zero page indexed) + when ZXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXLSR_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + when ZXLSR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT; + when ZXLSR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- ROL $xx,X (zero page indexed) + when ZXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXROL_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + when ZXROL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT; + when ZXROL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- ROR $xx,X (zero page indexed) + when ZXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXROR_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + when ZXROR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT; + when ZXROR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- INC $xx,X (zero page indexed) + when ZXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXINC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + when ZXINC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 + when ZXINC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- DEC $xx,X (zero page indexed) + when ZXDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXDEC_OP1 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; + when ZXDEC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 + when ZXDEC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- BIT $xx,X (zero page indexed) + when ZXBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZXBIT_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- A = A AND MEM; EI + + ------------------------------------ + -- ZERO PAGE,Y -- + ------------------------------------ + -- LDX $xx,Y (zero page indexed) + when ZYLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZYLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADDI & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; EI + + -- STX $xx,Y (zero page indexed) + when ZYSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & DOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+=D+O+X; PC+1; + when ZYSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADDI & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; EI + + ------------------------------------ + -- INDIRECT -- + ------------------------------------ + -- JMP ($xxxx) (indirect) + when INJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when INJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when INJMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + when INJMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->PC; O->PC; EI + + -- JML ($xxxx) (indirect) + when INJML_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when INJML_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when INJML_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + when INJML_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MP->MEM; MEM->O; MP+1 + when INJML_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; EXT->PBR; EI + + ------------------------------------ + -- INDIRECT,Y -- + ------------------------------------ + -- LDA ($xx),Y (zeropage - indirect - indexed) + when IYLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYLDA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- STA ($xx),Y (zeropage - indirect - indexed) + when IYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYSTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + + -- ADC ($xx),Y (zeropage - indirect - indexed) + when IYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + + -- SBC ($xx),Y (zeropage - indirect - indexed) + when IYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT + + -- CMP ($xx),Y (zeropage - indirect - indexed) + when IYCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI + + -- AND ($xx),Y (zeropage - indirect - indexed) + when IYAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + + -- ORA ($xx),Y (zeropage - indirect - indexed) + when IYORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + + -- EOR ($xx),Y (zeropage - indirect - indexed) + when IYEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when IYEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when IYEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ABY_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O+Y->MP + when IYEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + + ------------------------------------ + -- INDIRECT,X -- + ------------------------------------ + -- LDA ($xx,X) (zero page - indexed - indirect) + when IXLDA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; + when IXLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI=1 + + -- STA ($xx,X) (zero page - indexed - indirect) + when IXSTA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; + when IXSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- A->MEM; EI=1 + + -- AND ($xx,X) (zero page - indexed - indirect) + when IXAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; + when IXAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- MP->MEM; A=A AND MEM; EI=1 + + -- ORA ($xx,X) (zero page - indexed - indirect) + when IXORA_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; + when IXORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- MP->MEM; A=A OR MEM; EI=1 + + -- EOR ($xx,X) (zero page - indexed - indirect) + when IXEOR_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; + when IXEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1 + + -- ADC ($xx,X) (zero page - indexed - indirect) + when IXADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; + when IXADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1 + when IXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALL_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI + + -- SBC ($xx,X) (zero page - indexed - indirect) + when IXSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1 + when IXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALL_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI + + -- CMP ($xx,X) (zero page - indexed - indirect) + when IXCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1 + when IXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1 + when IXCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O) + when IXCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1 + + -- JMP ($xxxx,X) (absolute indexed - indirect) + when IXJMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when IXJMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when IXJMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MEM->A; MP_MSB+CARRY, EI + when IXJMP_OP3 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when IXJMP_OP4 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + -- JSR ($xxxx,X) (absolute indexed - indirect) + when IXJSR_OP0 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when IXJSR_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1; + when IXJSR_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1; + when IXJSR_OP3 => q <= ORD_D &'1'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when IXJSR_OP4 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when IXJSR_OP5 => q <= ORD_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + ------------------------------------ + -- ABSOLUTE -- + ------------------------------------ + -- LDA $xxxx (absolute) + when ABLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; PC+1 + + -- LDX $xxxx (absolute) + when ABLDX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLDX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; PC+1 + + -- LDY $xxxx (absolute) + when ABLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLDY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLDY_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->Y; PC+1 + + -- STA $xxxx (absolute) + when ABSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + + -- STX $xxxx (absolute) + when ABSTX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTX_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & XRD_O; -- MP->MEM; X->MEM; PC+1 + + -- STY $xxxx (absolute) + when ABSTY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTY_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & YRD_O; -- MP->MEM; Y->MEM; PC+1 + + -- STZ $xxxx (absolute) + when ABSTZ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSTZ_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSTZ_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; PC+1 + + -- JMP $xxxx (absolute) + when ABJMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + -- JSR $xxxx (absolute) + when ABJSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1; + when ABJSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1; + when ABJSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LOD_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->PC; O->PC; EI + + -- BIT $xxxx (absolute) + when ABBIT_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABBIT_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; MEM->ALU; PC+1 + + -- ADC $xxxx (absolute) + when ABADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + when ABADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALL_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI + + -- SBC $xxxx (absolute) + when ABSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A-EXT; EI + when ABSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALL_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI + + -- CMP $xxxx (absolute) + when ABCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + + -- CPX $xxxx (absolute) + when ABCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABCPX_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABCPX_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-EXT; EI + + -- CPY $xxxx (absolute) + when ABCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABCPY_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABCPY_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-EXT; EI + + -- ORA $xxxx (absolute) + when ABORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + + -- AND $xxxx (absolute) + when ABAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + + -- EOR $xxxx (absolute) + when ABEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + + -- ASL $xxxx (absolute) + when ABASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABASL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABASL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT; + when ABASL_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + -- LSR $xxxx (absolute) + when ABLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABLSR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABLSR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT; + when ABLSR_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + -- ROL $xxxx (absolute) + when ABROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABROL_OP1 => q <= ORD_D &'0'&'0'&'1'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABROL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABROL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT; + when ABROL_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + -- ROR $xxxx (absolute) + when ABROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABROR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABROR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT; + when ABROR_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + -- INC $xxxx (absolute) + when ABINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABINC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABINC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABINC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 + when ABINC_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + -- DEC $xxxx (absolute) + when ABDEC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABDEC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABDEC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABDEC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 + when ABDEC_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + -- TSB $xxxx (absolute) + when ABTSB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABTSB_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABTSB_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABTSB_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z + when ABTSB_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TSB_A & OLD_R & ARD_O; -- A OR O => O + when ABTSB_OP5 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + -- TRB $xxxx (absolute) + when ABTRB_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1 + when ABTRB_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1 + when ABTRB_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1 + when ABTRB_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & LDZ_P & AND_A & NOP_R & ARD_O; -- A AND O -> Z + when ABTRB_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & TRB_A & OLD_R & ARD_O; -- A NAND O => O + when ABTRB_OP5 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1 + + ------------------------------------ + -- ABSOLUTE,X -- + ------------------------------------ + -- DMUX: ALU operand #2 multiplexer + -- | AI: effective address is indexed (X or Y) + -- | | VP: vector pull + -- | | | ML: memory lock + -- | | | | VPA: vali program address + -- | | | | | VDA: valid data address + -- | | | | | | EI: end of microcode sequence (the hidden extra cycle it's always executed after this microinstruction) + -- | | | | | | | W: read/write control + -- | | | | | | | | CLI: clear interrupt request + -- | | | | | | | | | PD: PC/MP address output multiplexer select + -- | | | | | | | | | | PCR: register PC (program counter) + -- | | | | | | | | | | | MPR: register MP (memory pointer) + -- | | | | | | | | | | | | P_OP: register P set/reset bit + -- | | | | | | | | | | | | | ALUOP: ALU operation + -- | | | | | | | | | | | | | | REGOP: registers load/increment/decrement etc. + -- | | | | | | | | | | | | | | | RSEL: registers output multiplexer select + -- | | | | | | | | | | | | | | | | + -- | | | | | | | | | | | | | | | | + -- DMUX AI VP ML VPA VDA EI W CLI PD PCR MPR P_OP ALUOP REGOP RSEL + -- LDA $xxxx,X (absolute indexed) + when AXLDA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXLDA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXLDA_OP2 => q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- LDY $xxxx,X (absolute indexed) + when AXLDY_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXLDY_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXLDY_OP2 => q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & YLL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- STA $xxxx,X (absolute indexed) + when AXSTA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXSTA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXSTA_OP2 => q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + + -- STZ $xxxx,X (absolute indexed) + when AXSTZ_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXSTZ_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXSTZ_OP2 => q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & Z00_O; -- MP->MEM; 0->MEM; EI + + -- ADC $xxxx,X (absolute indexed) + when AXADC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXADC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + + -- SBC $xxxx,X (absolute indexed) + when AXSBC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXSBC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT; EI + + -- CMP $xxxx,X (absolute indexed) + when AXCMP_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXCMP_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI + + -- INC $xxxx,X (absolute indexed) + when AXINC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXINC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXINC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when AXINC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & INC_A & OLD_R & ORD_O; -- O = O +1 + when AXINC_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- DEC $xxxx,X (absolute indexed) + when AXDEC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXDEC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXDEC_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when AXDEC_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & DEC_A & OLD_R & ORD_O; -- O = O -1 + when AXDEC_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- ASL $xxxx,X (absolute indexed) + when AXASL_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXASL_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXASL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when AXASL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT + when AXASL_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- LSR $xxxx,X (absolute indexed) + when AXLSR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXLSR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXLSR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when AXLSR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT + when AXLSR_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- ROL $xxxx,X (absolute indexed) + when AXROL_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXROL_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXROL_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when AXROL_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT + when AXROL_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- ROR $xxxx,X (absolute indexed) + when AXROR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXROR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXROR_OP2 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI + when AXROR_OP3 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT + when AXROR_OP4 => q <= ORD_D &'0'&'0'&'1'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI + + -- AND $xxxx,X (absolute indexed) + when AXAND_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXAND_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- MP->MEM; EXT AND A; EI + + -- ORA $xxxx,X (absolute indexed) + when AXORA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXORA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- MP->MEM; EXT OR A; EI + + -- EOR $xxxx,X (absolute indexed) + when AXEOR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXEOR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- MP->MEM; EXT XOR A; EI + + -- BIT $xxxx,X (absolute indexed) + when AXBIT_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AXBIT_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1; + when AXBIT_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & BIT_A & NOP_R & ARD_O; -- MP->MEM; EXT BIT A; EI + + ------------------------------------ + -- ABSOLUTE,Y -- + ------------------------------------ + -- LDA $xxxx,X (absolute indexed) + when AYLDA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYLDA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYLDA_OP2 => q <= NOP_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- LDX $xxxx,Y (absolute indexed) + when AYLDX_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYLDX_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYLDX_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; MP_MSB+CARRY, EI + when AYLDX_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & XLL_R & EXT_O; -- MP->MEM; MEM->X; EI + + -- STA $xxxx,Y (absolute indexed) + when AYSTA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYSTA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI + when AYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + + -- ADC $xxxx,Y (absolute indexed) + when AYADC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYADC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI + when AYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + when AYADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALL_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI + + -- SBC $xxxx,Y (absolute indexed) + when AYSBC_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYSBC_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI + when AYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT + when AYSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALL_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI + + -- CMP $xxxx,Y (absolute indexed) + when AYCMP_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYCMP_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI + when AYCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI + + -- AND $xxxx,Y (absolute indexed) + when AYAND_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYAND_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & AND_A & ALL_R & ARD_O; -- MP->MEM; EXT AND A; MP_MSB+CARRY, EI + when AYAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- MP->MEM; EXT AND A; EI + + -- ORA $xxxx,Y (absolute indexed) + when AYORA_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYORA_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & OR_A & ALL_R & ARD_O; -- MP->MEM; EXT OR A; MP_MSB+CARRY, EI + when AYORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- MP->MEM; EXT OR A; EI + + -- EOR $xxxx,Y (absolute indexed) + when AYEOR_OP0 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when AYEOR_OP1 => q <= NOP_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ABY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1; + when AYEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & XOR_A & ALL_R & ARD_O; -- MP->MEM; EXT XOR A; MP_MSB+CARRY, EI + when AYEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- MP->MEM; EXT XOR A; EI + + -------------------------------------- + -- ABSOLUTE LONG -- + -------------------------------------- + -- JML $xxxxxx (absolute long) + when ABJML_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJML_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ABJML_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; EXT->PRB; EI + + -- JSL $xxxxxx (absolute long) + when ABJSL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ABJSL_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ABJSL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & KRD_O; -- PBR->S; SP-1; + when ABJSL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PHR_O; -- PCH->S; SP-1; + when ABJSL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & PLR_O; -- PCL->S; SP-1; + when ABJSL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & LML_PC & NOP_M & NOP_P & NOP_A & KLD_R & EXT_O; -- O->PC; EXT->PBR; EI + + ------------------------------------ + -- RELATIVE -- + ------------------------------------ + -- BRA xx + when BRA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BEQ xx + when BEQ_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BNE xx + when BNE_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BCC xx + when BCC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BCS xx + when BCS_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BVC xx + when BVC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BVS xx + when BVS_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BPL xx + when BPL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + -- BMI xx + when BMI_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRA_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset; + + ----------------------------------------- + -- RELATIVE LONG -- + ----------------------------------------- + -- BRL xxxx + when BRL_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb offset); + when BRL_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'1'& RDE &'0'& ADPC & BRL_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC +1 + offset + + ------------------------------- + -- STACK -- + ------------------------------- + -- PEA xxxx + when PEA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1 + when PEA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; PC+1 + when PEA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & OMD_O; -- O (msb) ->S; SP-1; + when PEA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ORD_O; -- O (lsb) ->S; SP-1; + + -- PEI xx + when PEI_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when PEI_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when PEI_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when PEI_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & OMD_O; -- O (msb) ->S; SP-1; + when PEI_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ORD_O; -- O (lsb) ->S; SP-1; + + -- PER xxxx + when PER_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O (lsb offset); + when PER_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (msb offset) + when PER_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & SWC_A & O16_R & PCR_O; -- O = O + PC + when PER_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & OMD_O; -- O (msb) ->S; SP-1; + when PER_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADSP & NOP_PC & NOP_M & NOP_P & NOP_A & SDW_R & ORD_O; -- O (lsb) ->S; SP-1; + + ---------------------------------- + -- DIRECT,Y -- + ---------------------------------- + -- LDA [$xx],Y (zeropage - direct long - indexed) + when DYLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYLDA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYLDA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYLDA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYLDA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYLDA_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- STA [$xx],Y (zeropage - indirect long - indexed) + when DYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYSTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYSTA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYSTA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYSTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYSTA_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + + -- ADC [$xx],Y (zeropage - indirect long - indexed) + when DYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYADC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYADC_OP5 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + + -- SBC [$xx],Y (zeropage - indirect long - indexed) + when DYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYSBC_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYSBC_OP5 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT + + -- CMP [$xx],Y (zeropage - indirect long - indexed) + when DYCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYCMP_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYCMP_OP5 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI + + -- AND [$xx],Y (zeropage - indirect long - indexed) + when DYAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYAND_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYAND_OP5 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + + -- ORA [$xx],Y (zeropage - indirect long - indexed) + when DYORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYORA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYORA_OP5 => q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + + -- EOR [$xx],Y (zeropage - indirect long - indexed) + when DYEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DYEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DYEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DYEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DYEOR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & ADY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when DYEOR_OP5 => q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + + -------------------------------- + -- DIRECT -- + -------------------------------- + -- LDA [$xx] (zeropage - direct long) + when DILDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DILDA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DILDA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DILDA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DILDA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- STA [$xx] (zeropage - indirect long) + when DISTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DISTA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DISTA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DISTA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DISTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; EI + + -- ADC [$xx] (zeropage - indirect long) + when DIADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- MP->MEM; A=A+EXT + + -- SBC [$xx] (zeropage - indirect long) + when DISBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DISBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DISBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DISBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DISBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- MP->MEM; A=A-EXT + + -- CMP [$xx] (zeropage - indirect long) + when DICMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DICMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DICMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DICMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DICMP_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI + + -- AND [$xx] (zeropage - indirect long) + when DIAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIAND_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIAND_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A = A AND MEM; EI + + -- ORA [$xx] (zeropage - indirect long) + when DIORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIORA_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIORA_OP4 => q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A = A OR MEM; EI + + -- EOR [$xx] (zeropage - indirect long) + when DIEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1 + when DIEOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; (LSB POINTER) + when DIEOR_OP2 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MEM->O; (MSB POINTER) + when DIEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MEM->B + when DIEOR_OP4 => q <= EXT_D &'1'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A = A XOR MEM; EI + + ---------------------------------------- + -- ABSOLUTE LONG -- + ---------------------------------------- + -- LDA $xxxxxx (absolute long) + when ALLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A + + -- STA $xxxxxx (absolute long) + when ALSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; + + -- ADC $xxxxxx (absolute long) + when ALADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- SBC $xxxxxx (absolute long) + when ALSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- CMP $xxxxxx (absolute long) + when ALCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + + -- ORA $xxxxxx (absolute long) + when ALORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALORA_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + + -- AND $xxxxxx (absolute long) + when ALAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALAND_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + + -- EOR $xxxxxx (absolute long) + when ALEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when ALEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when ALEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when ALEOR_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + + ------------------------------------------ + -- ABSOLUTE LONG,X -- + ------------------------------------------ + -- LDA $xxxxxx,X (absolute long indexed X) + when AILDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AILDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AILDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AILDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AILDA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A (lsb); + + -- STA $xxxxxx,X (absolute long indexed X) + when AISTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AISTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AISTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AISTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AISTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + + -- ADC $xxxxxx,X (absolute long indexed X) + when AIADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIADC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- SBC $xxxxxx,X (absolute long indexed X) + when AISBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AISBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AISBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AISBC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AISBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- CMP $xxxxxx,X (absolute long indexed X) + when AICMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AICMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AICMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AICMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AICMP_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + + -- ORA $xxxxxx,X (absolute long indexed X) + when AIORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIORA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIORA_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + + -- AND $xxxxxx,X (absolute long indexed X) + when AIAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIAND_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIAND_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + + -- EOR $xxxxxx,X (absolute long indexed X) + when AIEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; PC+1 + when AIEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; PC+1 + when AIEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MHB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- HIGH->MP; PC+1 + when AIEOR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ADX_M & NOP_P & NOP_A & NOP_R & EXT_O; -- O+Y->MP (24 bit) + when AIEOR_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + + ---------------------------------------- + -- STACK RELATIVE -- + ---------------------------------------- + -- LDA $xx,S (S + offset) + when SRLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- STA $xx,S (S + offset) + when SRSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + + -- ADC $xx,S (S + offset) + when SRADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- SBC $xx,S (S + offset) + when SRSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- CMP $xx,S (S + offset) + when SRCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + + -- ORA $xx,S (S + offset) + when SRORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRORA_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + + -- AND $xx,S (S + offset) + when SRAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SRAND_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + + -- EOR $xx,S (S + offset) + when SREOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SREOR_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + + ------------------------------------------------- + -- STACK RELATIVE INDEXED Y -- + ------------------------------------------------- + -- LDA ($xx,S),Y + when SYLDA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYLDA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYLDA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYLDA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYLDA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & NOP_A & ALL_R & EXT_O; -- MP->MEM; MEM->A; EI + + -- STA ($xx,S),Y + when SYSTA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYSTA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYSTA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYSTA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYSTA_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ARD_O; -- MP->MEM; A->MEM; PC+1 + + -- ADC ($xx,S),Y + when SYADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYADC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- SBC ($xx,S),Y + when SYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYSBC_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYSBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALL_R & ARD_O; -- A=A+EXT; EI + + -- CMP ($xx,S),Y + when SYCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYCMP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYCMP_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI + + -- ORA ($xx,S),Y + when SYORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYORA_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYORA_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYORA_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYORA_OP5 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & OR_A & ALL_R & ARD_O; -- A=A OR MEM; EI + + -- AND ($xx,S),Y + when SYAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYAND_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYAND_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYAND_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYAND_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & AND_A & ALL_R & ARD_O; -- A=A AND MEM; EI + + -- EOR ($xx,S),Y + when SYEOR_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & AOS_M & NOP_P & NOP_A & NOP_R & EXT_O; -- S+OFFSET->MP; PC+1 + when SYEOR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- LSB->O; MP+1 + when SYEOR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OMD_R & EXT_O; -- MSB->O; + when SYEOR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & AOY_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP+O+Y + when SYEOR_OP4 => q <= EXT_D &'0'&'0'&'0'&'0'&'1'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & XOR_A & ALL_R & ARD_O; -- A=A XOR MEM; EI + + ------------------------------------ + -- MOVE BLOCK -- + ------------------------------------ + when MBMVN_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (source) + when MBMVN_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADXR & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; read byte + when MBMVN_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (destination) + when MBMVN_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADYR & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O->MEM; write byte + when MBMVN_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MVN_R & EXT_O; -- X +1; Y +1; A -1; + when MBMVN_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & DE3_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- check for A = $FFFF + + when MBMVP_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (source) + when MBMVP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& RDE &'0'& ADXR & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; read byte + when MBMVP_OP2 => q <= ORD_D &'0'&'0'&'0'&'1'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & BLD_R & EXT_O; -- MEM->DBR (destination) + when MBMVP_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'1'&'0'& WRE &'0'& ADYR & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- O->MEM; write byte + when MBMVP_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MVP_R & EXT_O; -- X -1; Y -1; A -1; + when MBMVP_OP5 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & DE3_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- check for A = $FFFF + + ---------------------------------- + -- MULTIPLY -- + ---------------------------------- + when MPU_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MUI_R & EXT_O; -- load A/B & X on multiplier + when MPU_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MUS_R & EXT_O; -- start multiplication (unsigned) + when MPU_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & MUF_P & NOP_A & MUL_R & EXT_O; -- load result on A/B and X + when MPU_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- EI + + when MPS_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MUI_R & EXT_O; -- load A/B & X on multiplier + when MPS_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & MSS_R & EXT_O; -- start multiplication (signed) + when MPS_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & MSF_P & NOP_A & MUL_R & EXT_O; -- load result on A/B and X + when MPS_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & WDC_P & NOP_A & NOP_R & EXT_O; -- EI + + when others => q <= NOP_D &'0'&'0'&'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- EI + end case; + end if; + end process; +end comb; + + Index: mcseq.vhd =================================================================== --- mcseq.vhd (nonexistent) +++ mcseq.vhd (revision 2) @@ -0,0 +1,40 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- opcode => microcode address generation +entity mcseq is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + mc_nop: in STD_LOGIC; + fwait: in STD_LOGIC; + q: out STD_LOGIC_VECTOR(3 downto 0) + ); +end mcseq; + +architecture comb of mcseq is +signal reg: STD_LOGIC_VECTOR(3 downto 0); +begin + process(clk) + begin + if(clk'event and clk = '1')then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then + reg <= "0000"; + else + if mc_nop = '1' then + reg <= "1111"; + else + reg <= reg +1; + end if; + end if; + end if; + end if; + end process; + q <= reg; +end comb; + + Index: mpr.vhd =================================================================== --- mpr.vhd (nonexistent) +++ mpr.vhd (revision 2) @@ -0,0 +1,83 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit memory pointer address register +entity mpr is + port( clk: in STD_LOGIC; + fwait: in STD_LOGIC; + dbr_ld: in STD_LOGIC; + c: in STD_LOGIC; + fc: in STD_LOGIC_VECTOR(4 downto 0); + din_l: in STD_LOGIC_VECTOR(7 downto 0); + din_h: in STD_LOGIC_VECTOR(7 downto 0); + dbr: in STD_LOGIC_VECTOR(7 downto 0); + dr: in STD_LOGIC_VECTOR(15 downto 0); + op: in STD_LOGIC_VECTOR(15 downto 0); + xr: in STD_LOGIC_VECTOR(15 downto 0); + yr: in STD_LOGIC_VECTOR(15 downto 0); + sr: in STD_LOGIC_VECTOR(15 downto 0); + v: in STD_LOGIC_VECTOR(7 downto 0); + dout: out STD_LOGIC_VECTOR(23 downto 0) + ); +end mpr; + +architecture rtl of mpr is +constant NOP_M: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- no operation +constant LSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- load lsb +constant MSB_M: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- load msb +constant INC_M: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- increment +constant DEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- decrement +constant VEC_M: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- load vector +constant ZPL_M: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- load ZEROPAGE +constant ALL_M: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- load all 16 bit register +constant ICC_M: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- increment MSB with carry +constant DOX_M: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- add D + offset + X +constant DOY_M: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- add D + offset + Y +constant AOS_M: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- add S + offset +constant ABX_M: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- add opr+X +constant ABY_M: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- add opr+Y +constant ADX_M: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- add X +constant ADY_M: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- add Y +constant MHB_M: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- load high byte +constant AOY_M: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- add opr+Y and concatenates SBR + +signal reg: STD_LOGIC_VECTOR(23 downto 0); +begin + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if dbr_ld = '1' then -- on every opcode fetch the high byte of MPR is loaded with DBR value + reg(23 downto 16) <= dbr; + end if; + case fc is + when LSB_M => reg(7 downto 0) <= din_l; reg(23 downto 8) <= reg(23 downto 8); -- load LSB (bit 7..0) + when MSB_M => reg(15 downto 8) <= din_h; reg(7 downto 0) <= reg(7 downto 0); reg(23 downto 16) <= reg(23 downto 16); -- load MSB (bit 15..8) + when ALL_M => reg(15 downto 8) <= din_h; reg(7 downto 0) <= din_l; reg(23 downto 16) <= reg(23 downto 16); -- load LSB/MSB (bit 15..0) + when INC_M => reg <= reg +1; -- increment 24 bit + when DEC_M => reg <= reg -1; -- decrement 24 bit + when VEC_M => reg <= "0000000011111111" & v; -- 0x00FFXX load vector + when ZPL_M => reg(15 downto 0) <= dr + ("00000000" & din_l); -- 0x00XXXX zeropage operation (D + 0x0000XX) + when ICC_M => reg(15 downto 8) <= reg(15 downto 8) + c; -- increment MSB for indexed addressing mode + when DOX_M => reg(15 downto 0) <= dr + ("00000000" & din_l) + xr; -- D+offset+X + when DOY_M => reg(15 downto 0) <= dr + ("00000000" & din_l) + yr; -- D+offset+Y + when AOS_M => reg(15 downto 0) <= sr + ("00000000" & din_h); reg(23 downto 16) <= "00000000"; -- S+offset + when ABX_M => reg(15 downto 0) <= din_h & op(7 downto 0) + xr; -- +O+X + when ABY_M => reg(15 downto 0) <= din_h & op(7 downto 0) + yr; -- +O+Y + when ADX_M => reg <= reg + ("00000000" & xr); -- +X (24 bit SUM) + when ADY_M => reg <= reg + ("00000000" & yr); -- +Y (24 bit SUM) + when MHB_M => reg(23 downto 16) <= din_h; reg(15 downto 0) <= op; -- load high byte (bit 23..16) + when AOY_M => reg <= (dbr & op) + ("00000000" & yr); -- O+Y (24 bit SUM) + when others => reg <= reg; + end case; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: multiplier.vhd =================================================================== --- multiplier.vhd (nonexistent) +++ multiplier.vhd (revision 2) @@ -0,0 +1,143 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16X16->32 bit multiplier signed/unsigned +entity multiplier is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + init: in STD_LOGIC; + start_u: in STD_LOGIC; + start_s: in STD_LOGIC; + mpcand: in STD_LOGIC_VECTOR(15 downto 0); + mplier: in STD_LOGIC_VECTOR(15 downto 0); + busy: out STD_LOGIC; + res_lsb: out STD_LOGIC_VECTOR(15 downto 0); + res_msb: out STD_LOGIC_VECTOR(15 downto 0); + z_flg: out STD_LOGIC; + n_flg: out STD_LOGIC + ); +end multiplier; + +architecture rtl of multiplier is +type state_type is (s0, s1, s2, s3, s4); +signal state: state_type; +signal s: STD_LOGIC; +signal a: STD_LOGIC_VECTOR(31 downto 0); +signal b: STD_LOGIC_VECTOR(15 downto 0); +signal accum: STD_LOGIC_VECTOR(31 downto 0); +signal sign_a: STD_LOGIC; +signal sign_b: STD_LOGIC; +signal mpy: STD_LOGIC_VECTOR(1 downto 0); + +begin + mpy <= start_s & start_u; + process(clk,clr) + begin + if (clr = '1') THEN + state <= s0; + elsif rising_edge(clk) then + case state is + -- wait for init + when s0 => + if clr = '1' or init = '1' then + s <= '0'; + a <= "0000000000000000" & mpcand; + b <= mplier; + accum <= (others => '0'); + state <= s0; + else + a <= a; + b <= b; + accum <= accum; + sign_a <= sign_a; + sign_b <= sign_a; + case mpy is + when "01" => s <= '1'; -- start multiply unsigned + state <= s1; + when "10" => s <= '1'; -- start multiply signed + state <= s2; + when others => s <= '0'; + state <= s0; + end case; + end if; + + -- multiply unsigned + when s1 => + sign_a <= sign_a; + sign_b <= sign_b; + if b = 0 then -- if finished + accum <= accum; + s <= '0'; + state <= s0; + else + if b(0) = '1' then -- if bit #0 = 1 sum the (left) shifted multiplicand to the accumulator + accum <= accum + a; + else + accum <= accum; + end if; + s <= '1'; + a <= a(30 downto 0) & '0'; -- shift left moltiplicand + b <= '0' & b(15 downto 1); -- shift right multiplier + state <= s1; + end if; + + -- multiply signed + when s2 => + sign_a <= a(15); -- save sign of factors + sign_b <= b(15); + a <= "00000000000000000" & mpcand(14 downto 0); -- reload factors without sign bits + b <= '0' & mplier(14 downto 0); + state <= s3; + + when s3 => + sign_a <= sign_a; + sign_b <= sign_b; + if b = 0 then -- if finished + accum <= accum; + if (sign_a = '1' and sign_b = '0') or (sign_a = '0' and sign_b = '1') then -- if two's complement is needed + s <= '1'; + state <= s4; + else + s <= '0'; + state <= s0; + end if; + else + if b(0) = '1' then -- if bit #0 = 1 sum the (left) shifted multiplicand to the accumulator + accum <= accum + a; + else + accum <= accum; + end if; + s <= '1'; + a <= a(30 downto 0) & '0'; -- shift left moltiplicand + b <= '0' & b(15 downto 1); -- shift right multiplier + state <= s3; + end if; + + when s4 => + accum <= 0 - accum; -- two's complement + s <= '0'; + state <= s0; + + -- illegal state covering + when others => + a <= a; + b <= b; + sign_a <= sign_a; + sign_b <= sign_b; + accum <= accum; + s <= '0'; + state <= s0; + + end case; + end if; + end process; + res_lsb <= accum(15 downto 0); + res_msb <= accum(31 downto 16); + z_flg <= '1' when accum = "00000000000000000000000000000000" else '0'; + n_flg <= accum(31); + busy <= s; +end rtl; + + Index: oper.vhd =================================================================== --- oper.vhd (nonexistent) +++ oper.vhd (revision 2) @@ -0,0 +1,49 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit operand hold operand register +entity oper is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + ld: in STD_LOGIC; + ld_lsb: in STD_LOGIC; + ld_msb: in STD_LOGIC; + din: in STD_LOGIC_VECTOR(15 downto 0); + dout: out STD_LOGIC_VECTOR(15 downto 0) + ); +end oper; + +architecture rtl of oper is +signal reg: STD_LOGIC_VECTOR(15 downto 0); +begin + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then + reg <= "0000000000000000"; + else + if ld = '1' then + reg <= din; + end if; + if ld_lsb = '1' then + reg(7 downto 0) <= din(7 downto 0); + reg(15 downto 8) <= reg(15 downto 8); + end if; + if ld_msb = '1' then + reg(15 downto 8) <= din(7 downto 0); + reg(7 downto 0) <= reg(7 downto 0); + end if; + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: opr.vhd =================================================================== --- opr.vhd (nonexistent) +++ opr.vhd (revision 2) @@ -0,0 +1,62 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8 bit opcode hold register +entity opr is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + ld: in STD_LOGIC; + din: in STD_LOGIC_VECTOR(7 downto 0); + brk_f: out STD_LOGIC; + cop_f: out STD_LOGIC; + dout: out STD_LOGIC_VECTOR(7 downto 0) + ); +end opr; + +architecture rtl of opr is +constant BRK_OP: STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- 0x00 BRK/IRQ/NMI/RES +constant COP_OP: STD_LOGIC_VECTOR(7 downto 0) := "00000010"; -- 0x02 COP +signal reg: STD_LOGIC_VECTOR(7 downto 0); +signal bf: STD_LOGIC; +signal cf: STD_LOGIC; +begin + process(clk) + begin + if(clk'event and clk = '1')then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then -- clr serves to force an "BRK" opcode on RES-NMI-IRQ interrupt + reg <= BRK_OP; + bf <= '0'; + else + if ld = '1' then + reg <= din; + if din = BRK_OP then -- check if the opcode "BRK" was loaded as normal instruction or it was forced + bf <= '1'; -- by an interrupt request, thus in order to set properly the flag "B" of status register + cf <= '0'; + else + if din = COP_OP THEN + cf <= '1'; + else + cf <= '0'; + end if; + bf <= '0'; + end if; + else + reg <= reg; + bf <= bf; + end if; + end if; + end if; + end if; + end process; + brk_f <= bf; + cop_f <= cf; + dout <= reg; +end rtl; + + Index: pcr.vhd =================================================================== --- pcr.vhd (nonexistent) +++ pcr.vhd (revision 2) @@ -0,0 +1,91 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit program counter register "PC" +entity pcr is + port( clk: in STD_LOGIC; + i: in STD_LOGIC; + fwait: in STD_LOGIC; + brk_op: in STD_LOGIC; -- forced BRK (by interrupt request) + branch_flg: in STD_LOGIC; -- branch flag + mov_f: in STD_LOGIC; -- MVN/MVP end transfer + fc: in STD_LOGIC_VECTOR(3 downto 0); + din1: in STD_LOGIC_VECTOR(7 downto 0); + din2: in STD_LOGIC_VECTOR(15 downto 0); + dout: out STD_LOGIC_VECTOR(15 downto 0) + ); +end pcr; + +architecture rtl of pcr is +constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PC no operation +constant LSB_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PC load lsb +constant MSB_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- PC load msb +constant INC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- PC increment by 1 +constant LOD_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- PC load lsb\msb (used by JMP\JSR instructions) +constant LML_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- PC load lsb\msb from oper register (used for JML\JSL instructions) +constant IN2_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- PC = PC +2 (BRK opcode) +constant DE3_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- PC = PC -3 (MVN/MVP opcodes) +constant BRA_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- PC branch +constant BRL_P: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- PC branch long + +signal reg: STD_LOGIC_VECTOR(15 downto 0); + +begin + + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if i = '1' then + reg <= reg +1; + else + case fc is + when LSB_P => reg(7 downto 0) <= din1; reg(15 downto 8) <= reg(15 downto 8); + when MSB_P => reg(15 downto 8) <= din1; reg(7 downto 0) <= reg(7 downto 0); + when INC_P => reg <= reg +1; + when LOD_P => reg(15 downto 8) <= din1; reg(7 downto 0) <= din2(7 downto 0); + when BRA_P => + if branch_flg = '1' THEN -- if branch taken + if din1(7) = '0' THEN -- if branch forward + reg <= reg + "0000000000000001" + ("00000000" & din1); + else -- if branch backwards + reg <= reg + "0000000000000001" - ("00000000" & (0 - din1)); + end if; + else -- if branch not taken + reg <= reg + "0000000000000001"; + end if; + when BRL_P => + if din1(7) = '0' THEN -- if branch forward + reg <= reg + "0000000000000001" + (din1 & din2(7 downto 0)); + else -- if branch backwards + reg <= reg + "0000000000000001" - (0 - (din1 & din2(7 downto 0))); + end if; + + when LML_P => reg <= din2; + when IN2_P => + if brk_op = '1' then -- if BRK opcode PC=PC+2 + reg <= reg +1; -- PC already incremented by 1 by cpufsm + else + reg <= reg; + end if; + when DE3_P => + if mov_f = '0' then -- if MVN/MVP transfer not finished + reg <= reg - "0000000000000011"; + else + reg <= reg; + end if; + when NOP_P => reg <= reg; + when others => reg <= reg; + end case; + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: pr.vhd =================================================================== --- pr.vhd (nonexistent) +++ pr.vhd (revision 2) @@ -0,0 +1,216 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8 bit processor status register P +-- NV1BDIZC +-- 76543210 +-- |||||||| +-- ||||||||--- C/E = carry/borrow flag (emulation bit: 1 = emulation mode, 0 = native mode) +-- |||||||---- Z = zero flag +-- ||||||----- I = interrupt mask +-- |||||------ D = decimal/binary alu mode +-- ||||------- B/X = index reg. select (1 = 8 bit, 0 = 16 bit) (B Break: 0 on stack after interrupt if E emulation mode = 1) +-- |||-------- M = memory/acc. select (1 = 8 bit, 0 = 16 bit) (always 1 if E = 1) +-- ||--------- V = overflow flag +-- |---------- N = negative flag +entity pr is + port( clk: in STD_LOGIC; -- clock + clr: in STD_LOGIC; -- clear + fwait: in STD_LOGIC; + n: in STD_LOGIC; -- N input + v: in STD_LOGIC; -- V input + z: in STD_LOGIC; -- Z input + c: in STD_LOGIC; -- C input + mpy_z: in STD_LOGIC; -- Z input from multiplier + mpy_n: in STD_LOGIC; -- N input from multiplier + swi: in STD_LOGIC; -- software interrupt (BRK/COP opcode flag) + acr_in: in STD_LOGIC; -- auxiliary carry in + fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code + din: in STD_LOGIC_VECTOR(7 downto 0); -- input + dout: out STD_LOGIC_VECTOR(7 downto 0); -- output + acr_out: out STD_LOGIC; -- auxiliary carry out + em: out STD_LOGIC; -- emulation (1)/native mode (0) + two_op: out STD_LOGIC -- two byte instruction + ); +end pr; + +architecture rtl of pr is +constant NOP_P: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- PR no operation +constant PLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- PR load +constant FLD_P: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- NZ load +constant FLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- NZC load +constant FLV_P: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- NVZC load +constant SEC_P: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- 1 => C +constant CLC_P: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- 0 => C +constant SEI_P: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- 1 => I +constant CLI_P: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- 0 => I +constant SED_P: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- 1 => D +constant CLD_P: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- 0 => D +constant CLV_P: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- 0 => V +constant AUC_P: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- auc => ACR +constant HAC_P: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- hold ACR +constant SID_P: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- 1 => I/D +constant LDZ_P: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- Z load +constant XCE_P: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- E => C; C => E +constant SEP_P: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- P = P OR din +constant REP_P: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- P = P AND not din +constant WDM_P: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- 1 => op_exp; +constant WDC_P: STD_LOGIC_VECTOR(4 downto 0) := "10100"; -- 0 => op_exp; +constant FLW_P: STD_LOGIC_VECTOR(4 downto 0) := "10101"; -- NZ load, 0 -> op_exp +constant MUF_P: STD_LOGIC_VECTOR(4 downto 0) := "10110"; -- Z load from unsigned multplier +constant MSF_P: STD_LOGIC_VECTOR(4 downto 0) := "10111"; -- NZ load from unsigned multplier + +signal reg: STD_LOGIC_VECTOR(7 downto 0); +signal acr: STD_LOGIC; -- carry/borrow used for effective address calculation +signal eb: STD_LOGIC; -- emulation/native bit +signal op_exp: STD_LOGIC; -- two opcode bit +signal swint: STD_LOGIC; -- bit 4 saved on stack when BRK/COP + +begin + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then + reg <= "00110100"; -- on reset M,X,I = '1' + acr <= '0'; + eb <= '1'; -- on reset set emulation mode + op_exp <= '0'; + else + case fc is + when PLD_P => reg <= din; -- load NVMXDIZC + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + when FLD_P => reg <= n & reg(6 downto 2) & z & reg(0); -- load NZ + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + when FLC_P => reg <= n & reg(6 downto 2) & z & c; -- load NZC + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + when FLV_P => reg <= n & v & reg(5 downto 2) & z & c; -- load NVZC + acr <= '0'; + when SEC_P => reg <= reg or "00000001"; -- 1 => C + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when CLC_P => reg <= reg and "11111110"; -- 0 => C + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when CLI_P => reg <= reg and "11111011"; -- 0 => I + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when SED_P => reg <= reg or "00001000"; -- 1 => D + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when CLD_P => reg <= reg and "11110111"; -- 0 => D + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when LDZ_P => reg(1) <= z; -- z => Z + reg(7 downto 2) <= reg(7 downto 2); + reg(0) <= reg(0); + eb <= eb; + op_exp <= op_exp; + when SEI_P => reg(7 downto 3) <= reg(7 downto 3); + reg(2) <= '1'; -- 1 => I + reg(1 downto 0) <= reg(1 downto 0); + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when SID_P => reg(7 downto 4) <= reg(7 downto 4); -- set I and clear D decimal flag (used by interrupt sequence) + reg(3) <= '0'; -- 0 -> D + reg(2) <= '1'; -- 1 => I + reg(1 downto 0) <= reg(1 downto 0); + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when CLV_P => reg <= reg and "10111111"; -- 0 => V + acr <= acr; + eb <= eb; + op_exp <= op_exp; + when AUC_P => acr <= acr_in; -- store auxiliary carry (ACR) + reg <= reg; + eb <= eb; + op_exp <= op_exp; + when HAC_P => acr <= acr; -- holds auxiliary carry (ACR) + reg <= reg; + eb <= eb; + op_exp <= op_exp; + when XCE_P => eb <= reg(0); -- exchange C <=> E (switch emulation/native mode) + reg(0) <= eb; + reg(7 downto 1) <= reg(7 downto 1); + acr <= '0'; + op_exp <= op_exp; + when SEP_P => reg <= reg or din; -- SEP + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + when REP_P => reg <= reg and (not din); -- REP + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + when WDM_P => op_exp <= '1'; -- set two byte opcode + reg <= reg; + acr <= '0'; + eb <= eb; + when WDC_P => op_exp <= '0'; -- clear two byte opcode + reg <= reg; + acr <= '0'; + eb <= eb; + when FLW_P => reg <= n & reg(6 downto 2) & z & reg(0); -- load NZ, 0 => op_exp + acr <= '0'; + eb <= eb; + op_exp <= '0'; + when MUF_P => reg <= "00" & reg(5 downto 2) & mpy_z & '0'; -- load Z from multiplier, C/VN=0 + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + when MSF_P => reg <= mpy_n & '0' & reg(5 downto 2) & mpy_z & '0'; -- load NZ from multiplier, CV=0 + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + when others => reg <= reg; + acr <= '0'; + eb <= eb; + op_exp <= op_exp; + end case; + if eb = '1' then -- in emulation mode M/X are always set to '1' + reg(5 downto 4) <= "11"; + end if; + end if; + end if; + end if; + end process; + + process(fc,reg(4),eb,swi) + begin + if fc = SID_P then + if eb = '0' then + swint <= reg(4); + else + swint <= swi; -- when emulation mode is set the bit 4 reflects BRK opcode (pushed on stack) + end if; + else + swint <= reg(4); + end if; + end process; + + dout(7 downto 5) <= reg(7 downto 5); + dout(4) <= swint; -- save BRK/COP B="1" on stack if emulation mode + dout(3 downto 0) <= reg(3 downto 0); + acr_out <= acr; + em <= eb; + two_op <= op_exp; +end rtl; + + Index: pre_dec.vhd =================================================================== --- pre_dec.vhd (nonexistent) +++ pre_dec.vhd (revision 2) @@ -0,0 +1,167 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- opcode decimal instructions and prefetch prediction logic +entity pre_dec is + port( op: in STD_LOGIC_VECTOR(7 downto 0); + fetch: in STD_LOGIC; + ei: out STD_LOGIC; + dec: out STD_LOGIC + ); +end pre_dec; + +architecture comb of pre_dec is +constant NOP_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101010"; -- 0xEA NOP +constant CLC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011000"; -- 0x18 CLC 0->C +constant SEC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111000"; -- 0x38 SEC 1->C +constant CLI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01011000"; -- 0x58 CLI 0->I +constant SEI_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111000"; -- 0x78 SEI 1->I +constant CLV_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111000"; -- 0xB8 CLV 0->V +constant CLD_OP: STD_LOGIC_VECTOR(7 downto 0) := "11011000"; -- 0xD8 CLD 0->D +constant SED_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111000"; -- 0xF8 SED 1->D +constant TAX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101010"; -- 0xAA TAX A->X +constant TAY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10101000"; -- 0xA8 TAY A->Y +constant TXA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001010"; -- 0x8A TXA X->A +constant TYA_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011000"; -- 0x98 TYA Y->A +constant TXY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011011"; -- 0x9B TXY X->Y +constant TYX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111011"; -- 0xBB TYX Y->X +constant TXS_OP: STD_LOGIC_VECTOR(7 downto 0) := "10011010"; -- 0x9A TXS X->S +constant TSX_OP: STD_LOGIC_VECTOR(7 downto 0) := "10111010"; -- 0xBA TSX S->X +constant TCD_OP: STD_LOGIC_VECTOR(7 downto 0) := "01011011"; -- 0x5B TCD C->D +constant TDC_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111011"; -- 0x7B TDC D->C +constant TCS_OP: STD_LOGIC_VECTOR(7 downto 0) := "00011011"; -- 0x1B TCS C->S +constant TSC_OP: STD_LOGIC_VECTOR(7 downto 0) := "00111011"; -- 0x3B TSC S->C +constant INX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101000"; -- 0xE8 INX X +1 +constant DEX_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001010"; -- 0xCA DEX X -1 +constant INY_OP: STD_LOGIC_VECTOR(7 downto 0) := "11001000"; -- 0xC8 INY Y +1 +constant DEY_OP: STD_LOGIC_VECTOR(7 downto 0) := "10001000"; -- 0x88 DEY Y -1 +constant ASL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00001010"; -- 0x0A ASL A +constant LSR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01001010"; -- 0x4A LSR A +constant ROL_OP: STD_LOGIC_VECTOR(7 downto 0) := "00101010"; -- 0x2A ROL A +constant ROR_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101010"; -- 0x6A ROR A +constant XCE_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111011"; -- 0xFB XCE E<->C +constant XBA_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101011"; -- 0xEB XBA (swap A/B) +constant WDM_OP: STD_LOGIC_VECTOR(7 downto 0) := "01000010"; -- 0x42 WDM +constant ADC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100001"; -- 0x61 ADC ($xx,X) +constant ADC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110001"; -- 0x71 ADC ($xx),Y +constant ADC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "01100101"; -- 0x65 ADC $xx +constant ADC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "01110101"; -- 0x75 ADC $xx,X +constant ADC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "01101001"; -- 0x69 ADC #xx +constant ADC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111001"; -- 0x79 ADC $xxxx,Y +constant ADC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "01111101"; -- 0x7D ADC $xxxx,X +constant SBC1_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100001"; -- 0xE1 SBC ($xx,X) +constant SBC2_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110001"; -- 0xF1 SBC ($xx),Y +constant SBC3_OP: STD_LOGIC_VECTOR(7 downto 0) := "11100101"; -- 0xE5 SBC $xx +constant SBC4_OP: STD_LOGIC_VECTOR(7 downto 0) := "11110101"; -- 0xF5 SBC $xx,X +constant SBC5_OP: STD_LOGIC_VECTOR(7 downto 0) := "11101001"; -- 0xE9 SBC #xx +constant SBC6_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111001"; -- 0xF9 SBC $xxxx,Y +constant SBC7_OP: STD_LOGIC_VECTOR(7 downto 0) := "11111101"; -- 0xFD SBC $xxxx,X + +signal eoi: STD_LOGIC; +begin + process(op) + begin + case op is + when NOP_OP => eoi <= '1'; + dec <= '0'; + when CLC_OP => eoi <= '1'; + dec <= '0'; + when SEC_OP => eoi <= '1'; + dec <= '0'; + when CLI_OP => eoi <= '1'; + dec <= '0'; + when SEI_OP => eoi <= '1'; + dec <= '0'; + when CLV_OP => eoi <= '1'; + dec <= '0'; + when CLD_OP => eoi <= '1'; + dec <= '0'; + when SED_OP => eoi <= '1'; + dec <= '0'; + when TAX_OP => eoi <= '1'; + dec <= '0'; + when TAY_OP => eoi <= '1'; + dec <= '0'; + when TCD_OP => eoi <= '1'; + dec <= '0'; + when TDC_OP => eoi <= '1'; + dec <= '0'; + when TXA_OP => eoi <= '1'; + dec <= '0'; + when TYA_OP => eoi <= '1'; + dec <= '0'; + when TXY_OP => eoi <= '1'; + dec <= '0'; + when TYX_OP => eoi <= '1'; + dec <= '0'; + when TXS_OP => eoi <= '1'; + dec <= '0'; + when TSX_OP => eoi <= '1'; + dec <= '0'; + when TCS_OP => eoi <= '1'; + dec <= '0'; + when TSC_OP => eoi <= '1'; + dec <= '0'; + when INX_OP => eoi <= '1'; + dec <= '0'; + when DEX_OP => eoi <= '1'; + dec <= '0'; + when INY_OP => eoi <= '1'; + dec <= '0'; + when DEY_OP => eoi <= '1'; + dec <= '0'; + when ASL_OP => eoi <= '1'; + dec <= '0'; + when LSR_OP => eoi <= '1'; + dec <= '0'; + when ROL_OP => eoi <= '1'; + dec <= '0'; + when ROR_OP => eoi <= '1'; + dec <= '0'; + when XCE_OP => eoi <= '1'; + dec <= '0'; + when XBA_OP => eoi <= '1'; + dec <= '0'; + when WDM_OP => eoi <= '1'; + dec <= '0'; + -- ADC/SBC + when ADC1_OP => eoi <= '0'; + dec <= '1'; + when ADC2_OP => eoi <= '0'; + dec <= '1'; +-- when ADC3_OP => eoi <= '0'; +-- dec <= '1'; + when ADC4_OP => eoi <= '0'; + dec <= '1'; + when ADC5_OP => eoi <= '0'; + dec <= '1'; + when ADC6_OP => eoi <= '0'; + dec <= '1'; + when ADC7_OP => eoi <= '0'; + dec <= '1'; + when SBC1_OP => eoi <= '0'; + dec <= '1'; + when SBC2_OP => eoi <= '0'; + dec <= '1'; + when SBC3_OP => eoi <= '0'; + dec <= '1'; + when SBC4_OP => eoi <= '0'; + dec <= '1'; + when SBC5_OP => eoi <= '0'; + dec <= '1'; + when SBC6_OP => eoi <= '0'; + dec <= '1'; + when SBC7_OP => eoi <= '0'; + dec <= '1'; + when others => eoi <= '0'; + dec <= '0'; + end case; + end process; + ei <= eoi when fetch = '1' else '0'; +end comb; + + + + Index: regmux.vhd =================================================================== --- regmux.vhd (nonexistent) +++ regmux.vhd (revision 2) @@ -0,0 +1,90 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8 bit seven-way multiplexer +entity regmux is + port( sel: in STD_LOGIC_VECTOR(4 downto 0); + a: in STD_LOGIC_VECTOR(7 downto 0); + b: in STD_LOGIC_VECTOR(15 downto 0); + c: in STD_LOGIC_VECTOR(15 downto 0); + d: in STD_LOGIC_VECTOR(15 downto 0); + e: in STD_LOGIC_VECTOR(15 downto 0); + g: in STD_LOGIC_VECTOR(7 downto 0); + h: in STD_LOGIC_VECTOR(7 downto 0); + i: in STD_LOGIC_VECTOR(7 downto 0); + j: in STD_LOGIC_VECTOR(15 downto 0); + k: in STD_LOGIC_VECTOR(15 downto 0); + l: in STD_LOGIC_VECTOR(7 downto 0); + m: in STD_LOGIC_VECTOR(7 downto 0); + y: out STD_LOGIC_VECTOR(15 downto 0) + ); +end regmux; + +architecture comb of regmux is +constant EXT_O: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- external data bus +constant ARD_O: STD_LOGIC_VECTOR(4 downto 0) := "00001"; -- register C msb & lsb select +constant ARM_O: STD_LOGIC_VECTOR(4 downto 0) := "00010"; -- register C msb select (also returns C swapped) +constant XRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00011"; -- register X msb & lsb select +constant XRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- register X msb select +constant YRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00101"; -- register Y msb & lsb select +constant YRM_O: STD_LOGIC_VECTOR(4 downto 0) := "00110"; -- register Y msb select +constant SRD_O: STD_LOGIC_VECTOR(4 downto 0) := "00111"; -- register S lsb select +constant PRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- register P select +constant PLR_O: STD_LOGIC_VECTOR(4 downto 0) := "01001"; -- register PCL select +constant PHR_O: STD_LOGIC_VECTOR(4 downto 0) := "01010"; -- register PCH select +constant ORD_O: STD_LOGIC_VECTOR(4 downto 0) := "01011"; -- register O msb & lsb select +constant Z00_O: STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- select (all zero output) +constant DRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01101"; -- register D msb & lsb select +constant DRM_O: STD_LOGIC_VECTOR(4 downto 0) := "01110"; -- register D msb select +constant KRD_O: STD_LOGIC_VECTOR(4 downto 0) := "01111"; -- register K PBR +constant BRD_O: STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- register B PBR +constant EXM_O: STD_LOGIC_VECTOR(4 downto 0) := "10001"; -- external data bus on MSB, O on lsb +constant OMD_O: STD_LOGIC_VECTOR(4 downto 0) := "10010"; -- register O msb select +constant PCR_O: STD_LOGIC_VECTOR(4 downto 0) := "10011"; -- register PC (16 bit) select + +begin + process(sel,a,b,c,d,e,g,h,i,j,k,l,m) + begin + case sel is + when EXT_O => y(7 downto 0) <= a; + y(15 downto 8) <= (others => '0'); + when EXM_O => y(15 downto 8) <= a; + y(7 downto 0) <= j(7 downto 0); + when ARD_O => y <= b; + when ARM_O => y(7 downto 0) <= b(15 downto 8); + y(15 downto 8) <= b(7 downto 0); + when XRD_O => y <= c; + when XRM_O => y(7 downto 0) <= c(15 downto 8); + y(15 downto 8) <= (others => '0'); + when YRD_O => y <= d; + when YRM_O => y(7 downto 0) <= d(15 downto 8); + y(15 downto 8) <= (others => '0'); + when SRD_O => y <= e; + when PRD_O => y(7 downto 0) <= g; + y(15 downto 8) <= (others => '0'); + when PLR_O => y(7 downto 0) <= h; + y(15 downto 8) <= (others => '0'); + when PHR_O => y(7 downto 0) <= i; + y(15 downto 8) <= (others => '0'); + when ORD_O => y <= j; + when Z00_O => y <= (others => '0'); + when DRD_O => y <= k; + when DRM_O => y(7 downto 0) <= k(15 downto 8); + y(15 downto 8) <= (others => '0'); + when KRD_O => y(7 downto 0) <= l; + y(15 downto 8) <= (others => '0'); + when BRD_O => y(7 downto 0) <= m; + y(15 downto 8) <= (others => '0'); + when OMD_O => y(7 downto 0) <= j(15 downto 8); + y(15 downto 8) <= (others => '0'); + when PCR_O => y(7 downto 0) <= h; + y(15 downto 8) <= i; + when others => y(7 downto 0) <= a; + y(15 downto 8) <= (others => '0'); + end case; + end process; +end comb; + + Index: spr.vhd =================================================================== --- spr.vhd (nonexistent) +++ spr.vhd (revision 2) @@ -0,0 +1,68 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 8/16 bit stack pointer register "S" +entity spr is + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + em: in STD_LOGIC; + ld_l: in STD_LOGIC; + ld_h: in STD_LOGIC; + u: in STD_LOGIC; + d: in STD_LOGIC; + din: in STD_LOGIC_VECTOR(15 downto 0); + dout: out STD_LOGIC_VECTOR(15 downto 0) + ); +end spr; + +architecture rtl of spr is +constant SP_6502_VALUE: STD_LOGIC_VECTOR(15 downto 0) := "0000000111111111"; -- $01FF standard 6502 stack pointer +signal x: STD_LOGIC_VECTOR(3 downto 0); +signal reg: STD_LOGIC_VECTOR(15 downto 0); + +begin + x(0) <= ld_l; + x(1) <= ld_h; + x(2) <= u; + x(3) <= d; + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if clr = '1' then + reg <= SP_6502_VALUE; + else + if em = '0' then -- native mode (S full 16 bit) + case x is + when "0001" => reg(7 downto 0) <= din(7 downto 0); + reg(15 downto 8) <= reg(15 downto 8); + when "0010" => reg(15 downto 8) <= din(7 downto 0); + reg(7 downto 0) <= reg(7 downto 0); + when "0011" => reg <= din; + when "0100" => reg <= reg + 1; + when "1000" => reg <= reg - 1; + when others => reg <= reg; + end case; + else -- emulation mode (S is forced to 0x01XX) + case x is + when "0001" => reg(7 downto 0) <= din(7 downto 0); + when "0011" => reg(7 downto 0) <= din(7 downto 0); + when "0100" => reg(7 downto 0) <= reg(7 downto 0) + 1; + when "1000" => reg(7 downto 0) <= reg(7 downto 0) - 1; + when others => reg(7 downto 0) <= reg(7 downto 0); + end case; + reg(15 downto 8) <= SP_6502_VALUE(15 downto 8); + end if; + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: v65c816.vhd =================================================================== --- v65c816.vhd (nonexistent) +++ v65c816.vhd (revision 2) @@ -0,0 +1,1054 @@ +---------------------------------------------------------------------- +-- 8 bit microprocessor (65C816) VHDL project -- +-- Full RTL synchronous pipelined architecture -- +-- Project by Valerio Venturi (Italy) -- +-- Date: 5/04/2020 -- +-- Last revision: 5/04/2020 -- +---------------------------------------------------------------------- + +-- I don't makes any claims, promises or guarantees about the accuracy, completeness, or +-- adequacy of the contents of this website and expressly disclaims liability for errors and +-- omissions in the contents of this website. No warranty of any kind, implied, expressed or statutory, +-- including to fitness for a particular purpose and freedom from computer virus, is given with respect to +-- the contents of this website or its hyperlinks to other Internet resources. +-- Reference in this website to any specific commercial products, processes, or services, or +-- the use of any trade, firm or corporation name is for the information, and does +-- not constitute endorsement, recommendation, or favoring by me. +-- All the source code and tutorials are to be used on your own risk. All the ideas and views in this site are my own and +-- are not by any means related to my past or current employers. + +You can use the codes given in this website for non-commercial purposes without my permission. But if you are using it for commercial purposes then contact me with the details of your project for my permission. + +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- global architecture +entity v65c816 is + port( clk0: in STD_LOGIC; -- PHASE0 clock input + res: in STD_LOGIC; -- reset input + irq: in STD_LOGIC; -- interrupt request input + nmi: in STD_LOGIC; -- not maskable interrupt input + rdy: in STD_LOGIC; -- wait state request input (read/write) + rdy_out: out STD_LOGIC; -- CPU in wait state (WAI instruction) + stp_out: out STD_LOGIC; -- CPU in stop state (STP instruction) + rw: out STD_LOGIC; -- read/write out + vpa: out STD_LOGIC; -- vpa + vda: out STD_LOGIC; -- vda + ml: out STD_LOGIC; -- ml + vp: out STD_LOGIC; -- vector pull + ope: out STD_LOGIC; -- microcode end + e: out STD_LOGIC; -- emulation (1)/native mode (0) + m: out STD_LOGIC; -- M status + x: out STD_LOGIC; -- X status + op_exp: out STD_LOGIC; -- two byte instruction running + addr: out STD_LOGIC_VECTOR(23 downto 0); -- 16 bit address bus out + data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus + data_out: out STD_LOGIC_VECTOR(7 downto 0) -- 8 bit output data bus +-- DEBUG +-- a_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit A register +-- x_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit X register +-- y_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Y register +-- s_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit S register +-- op_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Operand register +-- p_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit P register +-- k_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit K register +-- b_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit B register +-- o_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit Opcode register +-- mcode: out STD_LOGIC_VECTOR(3 downto 0) -- 4 bit microcode sequence register + ); +end v65c816; + +architecture struct of v65c816 is + signal i_res: STD_LOGIC; -- internal global reset RES + signal i_irq: STD_LOGIC; -- internal interrupt request IRQ + signal i_nmi: STD_LOGIC; -- internal interrupt request NMI + signal i_rdy: STD_LOGIC; -- internal wait request RDY + signal e_rdy: STD_LOGIC; -- external invertedf RDY + signal i_vp: STD_LOGIC; -- internal VP (vector pull) + signal int: STD_LOGIC; -- internal global interrupt (instruction boundary synchronized) + signal we: STD_LOGIC; -- write enable (combinatorial from PLA) + signal we_r: STD_LOGIC; -- write enable (registered) + signal ien: STD_LOGIC; -- interrupt IRQ enable + signal emu: STD_LOGIC; -- emulation mode + signal two_byte_op: STD_LOGIC; -- two byte instruction + + -- microcode signals (register control) + signal regop: STD_LOGIC_VECTOR(5 downto 0); -- register operation microcode + signal rsel: STD_LOGIC_VECTOR(4 downto 0); -- register select microcode + signal a_l_lsb: STD_LOGIC; -- A load lsb + signal a_l_msb: STD_LOGIC; -- A load msb + signal a_dec: STD_LOGIC; -- A decrement (MVN/MVP) + signal x_l_lsb: STD_LOGIC; -- X load lsb + signal x_l_msb: STD_LOGIC; -- X load msb + signal x_d: STD_LOGIC; -- X decrement + signal x_u: STD_LOGIC; -- X increment + signal y_d: STD_LOGIC; -- Y decrement + signal y_u: STD_LOGIC; -- Y increment + signal y_l_lsb: STD_LOGIC; -- Y load lsb + signal y_l_msb: STD_LOGIC; -- Y load msb + signal d_l_lsb: STD_LOGIC; -- D load lsb + signal d_l_msb: STD_LOGIC; -- D load msb + signal p_l: STD_LOGIC; -- P load + signal k_l: STD_LOGIC; -- program bank register PBR K load + signal b_l: STD_LOGIC; -- data bank register DBR B load + signal k_cl: STD_LOGIC; -- program bank register PBR K clear + signal b_cl: STD_LOGIC; -- data bank register DBR B clear + signal o_l: STD_LOGIC; -- OPE load msb & lsb + signal o_l_lsb: STD_LOGIC; -- OPE load lsb + signal o_l_msb: STD_LOGIC; -- OPE load msb + signal sp_ll: STD_LOGIC; -- SP load lsb + signal sp_lh: STD_LOGIC; -- SP load msb + signal sp_u: STD_LOGIC; -- SP increment + signal sp_d: STD_LOGIC; -- SP decrement + signal dmux_sel: STD_LOGIC_VECTOR(2 downto 0); -- ALU operand #2 data multiplexer + signal kr_clear: STD_LOGIC; -- K clear + signal br_clear: STD_LOGIC; -- B clear + signal sp_emu: STD_LOGIC; -- '1' when S must be set in emulation mode + + -- microcode signals (ALU control) + signal aluop: STD_LOGIC_VECTOR(4 downto 0); -- ALU operation code + + -- microcode signals CPU control logic + signal mc_addr: STD_LOGIC_VECTOR(12 downto 0); -- microcode PLA address + signal opfetch: STD_LOGIC; -- opcode fetch + signal i_sync: STD_LOGIC; -- internal SYNC not latched + signal m_sync: STD_LOGIC; -- internal SYNC latched + signal opdec: STD_LOGIC; -- opcode decode + signal pcmp: STD_LOGIC_VECTOR(2 downto 0); -- PC/MP out control effective + signal pcmp_mc: STD_LOGIC_VECTOR(2 downto 0); -- PC/MP out control microcode + signal pcinc: STD_LOGIC; -- PC increment + signal e_eop: STD_LOGIC; -- early microcode sequence end (for some opcodes) + signal mc_eop: STD_LOGIC; -- microcode sequence end + signal eop: STD_LOGIC; -- microcode sequence end (effective) + signal we_mc: STD_LOGIC; -- microcode write enable + signal we_mc_l: STD_LOGIC; -- microcode write enable to latch + signal fbrk: STD_LOGIC; -- force BRK opcode (used by hardware interrupts) + signal opbrk: STD_LOGIC; -- BRK opcode (used for distinguish between hardware/software interrupts) + signal opcop: STD_LOGIC; -- COP opcode + signal sw_int: STD_LOGIC; -- software interrupt request + signal branch_taken: STD_LOGIC; -- branch condition resolved + signal pcc: STD_LOGIC; -- PC carry + signal clri: STD_LOGIC; -- clear interrupt request pending microcode + signal mc_vda: STD_LOGIC; -- microcode VDA + signal mc_vpa: STD_LOGIC; -- microcode VPA + signal mc_ml: STD_LOGIC; -- microcode ML + signal adc_sbc_mc: STD_LOGIC; -- ADC/SBC opcode (used for decimal adjustment) + signal ai_op: STD_LOGIC; -- opcode with absolute indexed addressing mode + signal daa_req: STD_LOGIC; -- DAA required + signal mcad: STD_LOGIC_VECTOR(11 downto 0); -- microcode address + signal mcscan: STD_LOGIC_VECTOR(3 downto 0); -- microcode pointer control + signal p_op: STD_LOGIC_VECTOR(4 downto 0); -- microcode control bits register P + signal pcr_fc: STD_LOGIC_VECTOR(3 downto 0); -- microcode control PC + signal mpr_fc: STD_LOGIC_VECTOR(4 downto 0); -- microcode control MP + signal mcbit: STD_LOGIC_VECTOR(44 downto 0); -- microcode control bits + signal regbit: STD_LOGIC_VECTOR(29 downto 0); -- microcode control bits on registers + signal ivoffs: STD_LOGIC_VECTOR(7 downto 0); -- interrupt vector offset encoding + signal mcn: STD_LOGIC; -- microcode does NOPs + signal add_sub_op: STD_LOGIC; -- ADC/SBC opcode + signal m_bit: STD_LOGIC; -- M bit of status register + signal x_bit: STD_LOGIC; -- X bit of status register + signal index_size: STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit + signal m_size8: STD_LOGIC; -- memory operation size: 1 = 8 bit + signal m_size16: STD_LOGIC; -- memory operation size: 1 = 16 bit + signal s_size16: STD_LOGIC; -- memory operation size: 1 = 16 bit for special cases + signal m_size: STD_LOGIC; -- memory operation size: 1 = 8 bit, 0 = 16 bit + signal acc_size: STD_LOGIC; -- accumulator C size: 1 = 8 bit, 0 = 16 bit + signal mov_end: STD_LOGIC; -- MVN/MVP end transfer + signal ld_acc: STD_LOGIC; -- load accumulator C register (16 bit) + signal ld_xy: STD_LOGIC; -- load X/Y registers (16 bit) + + -- ALU signals + signal c_flg: STD_LOGIC; -- ALU carry flag + signal z_flg: STD_LOGIC; -- ALU zero flag + signal v_flg: STD_LOGIC; -- ALU overflow flag + signal n_flg: STD_LOGIC; -- ALU negative flag + signal pc_c_alu_flg: STD_LOGIC; -- ALU PC carry flag + signal acr_reg: STD_LOGIC; -- ALU auxiliary carry (registered) + + -- multiplier signals + signal mul_init: STD_LOGIC; -- multiplier initialize + signal mul_start_u: STD_LOGIC; -- multiplier unsigned start + signal mul_start_s: STD_LOGIC; -- multiplier signed start + signal mul_busy: STD_LOGIC; -- multiplier busy + signal mul_r_lsb: STD_LOGIC_VECTOR(15 downto 0); -- multiplier lsb result + signal mul_r_msb: STD_LOGIC_VECTOR(15 downto 0); -- multiplier msb result + signal mul_l_res: STD_LOGIC; -- load multiplier lsb result on register A/B and multiplier msb result on register X + signal mul_z_flg: STD_LOGIC; -- multiplier Z flag + signal mul_n_flg: STD_LOGIC; -- multiplier N flag + + -- WAI/STP signals + signal wai_ff: STD_LOGIC; -- WAI instruction flipflop + signal stp_ff: STD_LOGIC; -- STP instruction flipflop + signal wai_set: STD_LOGIC; -- WAI flipflop set + signal stp_set: STD_LOGIC; -- STP flipflop set + + -- bus + signal dbin: STD_LOGIC_VECTOR(7 downto 0); -- input data bus D0..D7 + signal dbout: STD_LOGIC_VECTOR(7 downto 0); -- output data bus D0..D7 + signal a_bus: STD_LOGIC_VECTOR(15 downto 0); -- accumulator register A/B/C bus + signal x_bus: STD_LOGIC_VECTOR(15 downto 0); -- index register X bus + signal y_bus: STD_LOGIC_VECTOR(15 downto 0); -- index register Y bus + signal k_bus: STD_LOGIC_VECTOR(7 downto 0); -- program bank PBR K bus + signal b_bus: STD_LOGIC_VECTOR(7 downto 0); -- program data DBR B bus + signal d_bus: STD_LOGIC_VECTOR(15 downto 0); -- zero page/direct register D bus + signal sp_bus: STD_LOGIC_VECTOR(15 downto 0); -- stack pointer register S bus + signal p_bus: STD_LOGIC_VECTOR(7 downto 0); -- status register P bus + signal op_bus: STD_LOGIC_VECTOR(7 downto 0); -- opcode register bus + signal o_bus: STD_LOGIC_VECTOR(15 downto 0); -- operand register bus + signal oper_bus: STD_LOGIC_VECTOR(15 downto 0); -- operand bus (ALU operand #2 bus) + signal r_bus: STD_LOGIC_VECTOR(15 downto 0); -- general register bus (ALU operand #2 bus) + signal alu_bus: STD_LOGIC_VECTOR(15 downto 0); -- ALU output bus + signal pc_bus: STD_LOGIC_VECTOR(15 downto 0); -- program counter register PC bus + signal mp_bus: STD_LOGIC_VECTOR(23 downto 0); -- memory data pointer register bus + signal ad_bus: STD_LOGIC_VECTOR(15 downto 0); -- address bus + signal i_addr_bus: STD_LOGIC_VECTOR(23 downto 0); -- internal 24 bit address bus + + -- 16 bit program counter register (PC) + component pcr + port( clk: in STD_LOGIC; -- clock + i: in STD_LOGIC; -- increment + fwait: in STD_LOGIC; -- wait + brk_op: in STD_LOGIC; -- forced BRK (by interrupt request) + branch_flg: in STD_LOGIC; -- branch flag + mov_f: in STD_LOGIC; -- MVN/MVP end transfer + fc: in STD_LOGIC_VECTOR(3 downto 0); -- function code + din1: in STD_LOGIC_VECTOR(7 downto 0); -- input + din2: in STD_LOGIC_VECTOR(15 downto 0); -- input + dout: out STD_LOGIC_VECTOR(15 downto 0) -- output + ); + end component; + + -- 8 bit PBR program bank register K + component kr + port( clk: in STD_LOGIC; -- clock + clr: in STD_LOGIC; -- reset + fwait: in STD_LOGIC; + ld: in STD_LOGIC; -- load + din: in STD_LOGIC_VECTOR(7 downto 0); -- input + dout: out STD_LOGIC_VECTOR(7 downto 0) -- output + ); + end component; + + -- 8 bit DBR program bank register B + component br + port( clk: in STD_LOGIC; -- clock + clr: in STD_LOGIC; -- reset + fwait: in STD_LOGIC; + ld: in STD_LOGIC; -- load + din: in STD_LOGIC_VECTOR(7 downto 0); -- input + dout: out STD_LOGIC_VECTOR(7 downto 0) -- output + ); + end component; + + -- 16 bit memory pointer register (MP) + component mpr + port( clk: in STD_LOGIC; -- clock + fwait: in STD_LOGIC; -- wait + dbr_ld: in STD_LOGIC; -- load DBR + c: in STD_LOGIC; -- carry + fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code + din_l: in STD_LOGIC_VECTOR(7 downto 0); -- input LSB + din_h: in STD_LOGIC_VECTOR(7 downto 0); -- input MSB + dbr: in STD_LOGIC_VECTOR(7 downto 0); + dr: in STD_LOGIC_VECTOR(15 downto 0); + op: in STD_LOGIC_VECTOR(15 downto 0); + xr: in STD_LOGIC_VECTOR(15 downto 0); + yr: in STD_LOGIC_VECTOR(15 downto 0); + sr: in STD_LOGIC_VECTOR(15 downto 0); + v: in STD_LOGIC_VECTOR(7 downto 0); -- vector offset input + dout: out STD_LOGIC_VECTOR(23 downto 0) -- output + ); + end component; + + -- 8 bit opcode register opr (pipeline opcode prefetch register) + component opr + port( clk: in STD_LOGIC; -- clock + clr: in STD_LOGIC; -- force BRK opcode + fwait: in STD_LOGIC; -- wait + ld: in STD_LOGIC; -- load + din: in STD_LOGIC_VECTOR(7 downto 0); -- input + brk_f: out STD_LOGIC; -- BRK opcode + cop_f: out STD_LOGIC; -- COP opcode + dout: out STD_LOGIC_VECTOR(7 downto 0) -- output + ); + end component; + + -- 16 bit operand hold register oper + component oper + port( clk: in STD_LOGIC; -- clock + clr: in STD_LOGIC; -- clear + fwait: in STD_LOGIC; -- wait + ld: in STD_LOGIC; + ld_lsb: in STD_LOGIC; -- load lsb + ld_msb: in STD_LOGIC; -- load msb + din: in STD_LOGIC_VECTOR(15 downto 0); -- input + dout: out STD_LOGIC_VECTOR(15 downto 0) -- output + ); + end component; + + -- 16 bit accumulator register A + component ar + port( clk: in STD_LOGIC; -- clock + fwait: in STD_LOGIC; + size: in STD_LOGIC; -- accumulator register size: 1 = 8 bit, 0 = 16 bit + ld_lsb: in STD_LOGIC; -- load lsb + ld_msb: in STD_LOGIC; -- load msb + ld_mul_lsb: in STD_LOGIC; -- load multiplication lsb result + d: in STD_LOGIC; -- decrement + end_count: out STD_LOGIC; -- '1' when a is 0xFF or 0xFFFF + din: in STD_LOGIC_VECTOR(15 downto 0); -- input + mul_lsb: in STD_LOGIC_VECTOR(15 downto 0); -- input multiplication lsb result + dout: out STD_LOGIC_VECTOR(15 downto 0) -- output + ); + end component; + + -- 16 bit index register X + component xr + port( clk: in STD_LOGIC; -- clock + fwait: in STD_LOGIC; + size: in STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit + ld_lsb: in STD_LOGIC; -- load lsb + ld_msb: in STD_LOGIC; -- load msb + ld_mul_msb: in STD_LOGIC; + u: in STD_LOGIC; -- increment + d: in STD_LOGIC; -- decrement + din: in STD_LOGIC_VECTOR(15 downto 0); -- input + mul_msb: in STD_LOGIC_VECTOR(15 downto 0); -- input multiplication msb result + dout: out STD_LOGIC_VECTOR(15 downto 0) -- output + ); + end component; + + -- 16 bit index register Y + component yr + port( clk: in STD_LOGIC; -- clock + fwait: in STD_LOGIC; + size: in STD_LOGIC; -- index register size: 1 = 8 bit, 0 = 16 bit + ld_lsb: in STD_LOGIC; -- load lsb + ld_msb: in STD_LOGIC; -- load msb + u: in STD_LOGIC; -- increment + d: in STD_LOGIC; -- decrement + din: in STD_LOGIC_VECTOR(15 downto 0); -- input + dout: out STD_LOGIC_VECTOR(15 downto 0) -- output + ); + end component; + + -- 16 bit zero page/direct register D + component dr + port( clk: in STD_LOGIC; -- clock + clr: in STD_LOGIC; -- reset + fwait: in STD_LOGIC; + ld_lsb: in STD_LOGIC; -- load lsb + ld_msb: in STD_LOGIC; -- load msb + din: in STD_LOGIC_VECTOR(15 downto 0); -- input + dout: out STD_LOGIC_VECTOR(15 downto 0) -- output + ); + end component; + + -- 16 bit stack pointer SP + component spr + port( clk: in STD_LOGIC; -- clock + fwait: in STD_LOGIC; -- wait + em: in STD_LOGIC; -- emulation mode (1)/native mode (0) + clr: in STD_LOGIC; -- load init value + ld_l: in STD_LOGIC; -- load lsb + ld_h: in STD_LOGIC; -- load msb + u: in STD_LOGIC; -- increment + d: in STD_LOGIC; -- decrement + din: in STD_LOGIC_VECTOR(15 downto 0); -- input + dout: out STD_LOGIC_VECTOR(15 downto 0) -- output + ); + end component; + +-- 8 bit processor status register P +-- NV1BDIZC +-- 76543210 +-- |||||||| +-- ||||||||--- C/E = carry/borrow flag (emulation bit: 1 = emulation mode, 0 = native mode) +-- |||||||---- Z = zero flag +-- ||||||----- I = interrupt mask +-- |||||------ D = decimal/binary alu mode +-- ||||------- B/X = index reg. select (1 = 8 bit, 0 = 16 bit) (B Break: 0 on stack after interrupt if E emulation mode = 1) +-- |||-------- M = memory/acc. select (1 = 8 bit, 0 = 16 bit) (always 1 if E = 1) +-- ||--------- V = overflow flag +-- |---------- N = negative flag + -- The P register also contains an additional carry/borrow flag (ACR) used for effective address calculation but + -- it is not visible at program level + component pr + port( clk: in STD_LOGIC; -- clock + clr: in STD_LOGIC; -- clear + fwait: in STD_LOGIC; -- wait + n: in STD_LOGIC; -- N input + v: in STD_LOGIC; -- V input + z: in STD_LOGIC; -- Z input + c: in STD_LOGIC; -- C input + mpy_z: in STD_LOGIC; -- Z input from multiplier + mpy_n: in STD_LOGIC; -- N input from multiplier + swi: in STD_LOGIC; -- software interrupt (BRK/COP opcode) + acr_in: in STD_LOGIC; -- auxiliary carry in + fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code + din: in STD_LOGIC_VECTOR(7 downto 0); -- input + dout: out STD_LOGIC_VECTOR(7 downto 0); -- output + acr_out: out STD_LOGIC; -- auxiliary carry out + em: out STD_LOGIC; -- emulation (1)/native mode (0) + two_op: out STD_LOGIC -- two byte instruction + ); + end component; + + -- 16 bit (binary/bcd) two-way through pass ALU + component alu_bin + port( alu_byp: in STD_LOGIC; -- ALU bypass (no operation) + bcd: in STD_LOGIC; -- BCD mode + size: in STD_LOGIC; -- ALU size operation: 1 = 8 bit, 0 = 16 bit + cin: in STD_LOGIC; -- carry/borrow in + vin: in STD_LOGIC; -- overflow in + op1: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #1 + op2: in STD_LOGIC_VECTOR(15 downto 0); -- 16 bit operand #2 + fc: in STD_LOGIC_VECTOR(4 downto 0); -- function code + cf: out STD_LOGIC; -- carry/borrow (byte) out + zf: out STD_LOGIC; -- zero flag out + nf: out STD_LOGIC; -- negative flag out + vf: out STD_LOGIC; -- overflow flag out + pc_cf: out STD_LOGIC; -- carry/borrow out for PC operation + dout: out STD_LOGIC_VECTOR(15 downto 0) -- 16 bit result out + ); + end component; + + -- PC/MP address multiplexer + component addrmux + port( sel: in STD_LOGIC_VECTOR(2 downto 0); + a: in STD_LOGIC_VECTOR(23 downto 0); + b: in STD_LOGIC_VECTOR(23 downto 0); + dbr: in STD_LOGIC_VECTOR(7 downto 0); + s: in STD_LOGIC_VECTOR(15 downto 0); + xr: in STD_LOGIC_VECTOR(15 downto 0); + yr: in STD_LOGIC_VECTOR(15 downto 0); + y: out STD_LOGIC_VECTOR(23 downto 0) + ); + end component; + + -- register multiplexer + component regmux + port( sel: in STD_LOGIC_VECTOR(4 downto 0); + a: in STD_LOGIC_VECTOR(7 downto 0); + b: in STD_LOGIC_VECTOR(15 downto 0); + c: in STD_LOGIC_VECTOR(15 downto 0); + d: in STD_LOGIC_VECTOR(15 downto 0); + e: in STD_LOGIC_VECTOR(15 downto 0); + g: in STD_LOGIC_VECTOR(7 downto 0); + h: in STD_LOGIC_VECTOR(7 downto 0); + i: in STD_LOGIC_VECTOR(7 downto 0); + j: in STD_LOGIC_VECTOR(15 downto 0); + k: in STD_LOGIC_VECTOR(15 downto 0); + l: in STD_LOGIC_VECTOR(7 downto 0); + m: in STD_LOGIC_VECTOR(7 downto 0); + y: out STD_LOGIC_VECTOR(15 downto 0) + ); + end component; + + -- data multiplexer (register "O" bypass) + component dmux is + port( sel: in STD_LOGIC_VECTOR(2 downto 0); + a: in STD_LOGIC_VECTOR(15 downto 0); + b: in STD_LOGIC_VECTOR(7 downto 0); + y: out STD_LOGIC_VECTOR(15 downto 0) + ); + end component dmux; + + -- microcode sequencer logic + component mcseq + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + mc_nop: in STD_LOGIC; + fwait: in STD_LOGIC; + q: out STD_LOGIC_VECTOR(3 downto 0) + ); + end component; + + -- micropla logic + -- output fields format: + -- a[12] is two byte instruction bit + -- a[11..4] is 8 bit opcode + -- a[3..0] is 4 bit microinstruction counter + component mcpla + port( em: in STD_LOGIC; -- emulation mode (1)/native mode (0) + m: in STD_LOGIC; -- M memory/acc. 8 bit (1), M memory/acc. 16 bit (0) + x: in STD_LOGIC; -- X index reg. 8 bit (1), X index reg. 16 bit (0) + a: in STD_LOGIC_VECTOR(12 downto 0); -- two byte bit & 8 bit opcode & 4 bit microinstruction counter + q: out STD_LOGIC_VECTOR(44 downto 0) -- microcode output + ); + end component; + + -- register operation decoding logic + component decreg + port( r: in STD_LOGIC_VECTOR(5 downto 0); + y: out STD_LOGIC_VECTOR(29 downto 0) + ); + end component; + + -- cpu main state machine + component cpufsm + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + fwait: in STD_LOGIC; + ireq: in STD_LOGIC; + aim: in STD_LOGIC; + bcarry: in STD_LOGIC; + icarry: in STD_LOGIC; + p1: in STD_LOGIC_VECTOR(2 downto 0); + e_ei: in STD_LOGIC; + mc_ei: in STD_LOGIC; + addsub: in STD_LOGIC; + dec_mode: in STD_LOGIC; + fetch: out STD_LOGIC; + op_sync: out STD_LOGIC; + pci: out STD_LOGIC; + pq: out STD_LOGIC_VECTOR(2 downto 0); + fb: out STD_LOGIC; + od: out STD_LOGIC; + mc_nop: out STD_LOGIC + ); + end component; + + -- interrupt logic + component intlog + port( clk: in STD_LOGIC; + iack: in STD_LOGIC; -- interrupt acknowledge by microcode + r: in STD_LOGIC; -- RESET request + n: in STD_LOGIC; -- NMI request + i: in STD_LOGIC; -- IRQ request + brk: in STD_LOGIC; -- BRK opcode + cop: in STD_LOGIC; -- COP opcode + e: in STD_LOGIC; -- native\emulation mode + gmask: in STD_LOGIC; -- interrupt mask valid for IRQ and NMI (used by two byte instruction) + imask: in STD_LOGIC; -- interrupt mask (valid only for IRQ) + ioffs: in STD_LOGIC_VECTOR(7 downto 0); -- interrupt servicing offset + ireq: out STD_LOGIC; -- global interrupt requestb (IRQ/NMI) + voffs: out STD_LOGIC_VECTOR(7 downto 0) -- interrupt vector offset + ); + end component; + + -- branch logic + component branch + port( op: in STD_LOGIC_VECTOR(3 downto 0); + n: in STD_LOGIC; + v: in STD_LOGIC; + z: in STD_LOGIC; + c: in STD_LOGIC; + bres: out STD_LOGIC + ); + end component; + + -- opcode decimal instructions and prefetch prediction logic + component pre_dec + port( op: in STD_LOGIC_VECTOR(7 downto 0); + fetch: in STD_LOGIC; + ei: out STD_LOGIC; + dec: out STD_LOGIC + ); + end component; + + -- 16X16->32 bit multiplier signed/unsigned + component multiplier + port( clk: in STD_LOGIC; + clr: in STD_LOGIC; + init: in STD_LOGIC; + start_u: in STD_LOGIC; + start_s: in STD_LOGIC; + mpcand: in STD_LOGIC_VECTOR(15 downto 0); + mplier: in STD_LOGIC_VECTOR(15 downto 0); + busy: out STD_LOGIC; + res_lsb: out STD_LOGIC_VECTOR(15 downto 0); + res_msb: out STD_LOGIC_VECTOR(15 downto 0); + z_flg: out STD_LOGIC; + n_flg: out STD_LOGIC + ); + end component; + + begin + u1:pcr port map(clk=>clk0, + i=>pcinc, + fwait=>i_rdy, + brk_op=>opbrk, + branch_flg=>branch_taken, + mov_f=>mov_end, + fc=>pcr_fc, + din1=>alu_bus(7 downto 0), + din2=>o_bus, + dout=>pc_bus + ); + + u2:kr port map(clk=>clk0, + clr=>kr_clear, + fwait=>i_rdy, + ld=>k_l, + din=>alu_bus(7 downto 0), + dout=>k_bus + ); + + u3:br port map(clk=>clk0, + clr=>br_clear, + fwait=>i_rdy, + ld=>b_l, + din=>alu_bus(7 downto 0), + dout=>b_bus + ); + + u4:mpr port map(clk=>clk0, + fwait=>i_rdy, + dbr_ld=>opfetch, + c=>acr_reg, + fc=>mpr_fc, + din_l=>alu_bus(7 downto 0), + din_h=>dbin, + dbr=>b_bus, + dr=>d_bus, + op=>o_bus, + xr=>x_bus, + yr=>y_bus, + sr=>sp_bus, + v=>ivoffs, + dout=>mp_bus + ); + + u5:ar port map(clk=>clk0, + fwait=>i_rdy, + size=>acc_size, + ld_lsb=>a_l_lsb, + ld_msb=>a_l_msb, + ld_mul_lsb=>mul_l_res, + d=>a_dec, + end_count=>mov_end, + din=>alu_bus, + mul_lsb=>mul_r_lsb, + dout=>a_bus + ); + + u6:xr port map(clk=>clk0, + fwait=>i_rdy, + size=>index_size, + ld_lsb=>x_l_lsb, + ld_msb=>x_l_msb, + ld_mul_msb=>mul_l_res, + u=>x_u, + d=>x_d, + din=>alu_bus, + mul_msb=>mul_r_msb, + dout=>x_bus + ); + + u7:yr port map(clk=>clk0, + fwait=>i_rdy, + size=>index_size, + ld_lsb=>y_l_lsb, + ld_msb=>y_l_msb, + u=>y_u, + d=>y_d, + din=>alu_bus, + dout=>y_bus + ); + + u8:dr port map(clk=>clk0, + clr=>i_res, + fwait=>i_rdy, + ld_lsb=>d_l_lsb, + ld_msb=>d_l_msb, + din=>alu_bus, + dout=>d_bus + ); + + u9:spr port map(clk=>clk0, + clr=>i_res, + fwait=>i_rdy, + em=>sp_emu, + ld_l=>sp_ll, + ld_h=>sp_lh, + u=>sp_u, + d=>sp_d, + din=>alu_bus, + dout=>sp_bus + ); + + u10:pr port map(clk=>clk0, + clr=>i_res, + fwait=>i_rdy, + n=>n_flg, + v=>v_flg, + z=>z_flg, + c=>c_flg, + mpy_z=>mul_z_flg, + mpy_n=>mul_n_flg, + swi=>sw_int, + acr_in=>pc_c_alu_flg, + fc=>p_op, + din=>dbin, + dout=>p_bus, + acr_out=>acr_reg, + em=>emu, + two_op=>two_byte_op + ); + + u11:opr port map(clk=>clk0, + clr=>fbrk, + fwait=>i_rdy, + ld=>opfetch, + din=>dbin, + brk_f=>opbrk, + cop_f=>opcop, + dout=>op_bus + ); + + u12:oper port map(clk=>clk0, + clr=>opfetch, + fwait=>i_rdy, + ld=>o_l, + ld_lsb=>o_l_lsb, + ld_msb=>o_l_msb, + din=>alu_bus, + dout=>o_bus + ); + + u13:alu_bin port map(alu_byp=>acr_reg, + bcd=>p_bus(3), + size=>m_size, + cin=>p_bus(0), + vin=>p_bus(6), + op1=>r_bus, + op2=>oper_bus, + fc=>aluop, + cf=>c_flg, + zf=>z_flg, + nf=>n_flg, + vf=>v_flg, + pc_cf=>pc_c_alu_flg, + dout=>alu_bus + ); + + u14:addrmux port map(sel=>pcmp, + a=>i_addr_bus, + b=>mp_bus, + dbr=>b_bus, + s=>sp_bus, + xr=>x_bus, + yr=>y_bus, + y=>addr + ); + + u15:regmux port map(sel=>rsel, + a=>dbin, + b=>a_bus, + c=>x_bus, + d=>y_bus, + e=>sp_bus, + g=>p_bus, + h=>pc_bus(7 downto 0), + i=>pc_bus(15 downto 8), + j=>o_bus, + k=>d_bus, + l=>k_bus, + m=>b_bus, + y=>r_bus + ); + + u16:dmux port map(sel=>dmux_sel, + a=>o_bus, + b=>dbin, + y=>oper_bus + ); + + u17:mcseq port map(clk=>clk0, + clr=>opdec, + mc_nop=>mcn, + fwait=>i_rdy or mul_busy, + q=>mcscan + ); + + u18:mcpla port map(em=>emu, + m=>m_bit, + x=>x_bit, + a=>mc_addr, + q=>mcbit + ); + + u19:decreg port map(r=>regop, + y=>regbit + ); + + u20:cpufsm port map(clk=>clk0, + clr=>i_res, + fwait=>i_rdy, + ireq=>int, + aim=>ai_op, + bcarry=>pcc, + icarry=>acr_reg, + p1=>pcmp_mc, + e_ei=>e_eop, + mc_ei=>mc_eop, + addsub=>add_sub_op, + dec_mode=>p_bus(3), + fetch=>opfetch, + op_sync=>i_sync, + pci=>pcinc, + pq=>pcmp, + fb=>fbrk, + od=>opdec, + mc_nop=>mcn + ); + + u21:intlog port map(clk=>clk0, + iack=>clri, + r=>i_res, + n=>i_nmi, + i=>i_irq, + brk=>opbrk, + cop=>opcop, + e=>emu, + gmask=>two_byte_op, + imask=>ien, + ioffs=>mp_bus(7 downto 0), + ireq=>int, + voffs=>ivoffs + ); + + u22:branch port map(op=>op_bus(7 downto 4), + n=>p_bus(7), + v=>p_bus(6), + z=>p_bus(1), + c=>p_bus(0), + bres=>branch_taken + ); + + u23:pre_dec port map(op=>dbin, + fetch=>opfetch, + ei=>e_eop, + dec=>add_sub_op + ); + + u24:multiplier port map(clk=>clk0, + clr=>i_res, + init=>mul_init, + start_u=>mul_start_u, + start_s=>mul_start_s, + mpcand=>a_bus, + mplier=>x_bus, + busy=>mul_busy, + res_lsb=>mul_r_lsb, + res_msb=>mul_r_msb, + z_flg=>mul_z_flg, + n_flg=>mul_n_flg + ); + + -- asynchronous CPU link section + mc_addr <= two_byte_op & mcad; + e <= emu; -- emulation mode + ien <= p_bus(2); -- P(I) flag + i_res <= not res; -- internal reset + i_nmi <= not nmi; -- internal NMI + i_irq <= not irq; -- internal IRQ + e_rdy <= not rdy; -- external RDY inverted + i_rdy <= e_rdy or wai_ff or stp_ff; -- internal RDY + mcad <= op_bus & mcscan; -- microcode address + rsel <= mcbit(4 downto 0); -- registers read microcode + regop <= mcbit(10 downto 5); -- registers operation microcode + aluop <= mcbit(15 downto 11); -- ALU microcode + p_op <= mcbit(20 downto 16); -- register P microcode + mpr_fc <= mcbit(25 downto 21); -- MPR microcode + pcr_fc <= mcbit(29 downto 26); -- PCR microcode + pcmp_mc <= mcbit(32 downto 30); -- PCR/MPR multiplexer microcode + clri <= mcbit(33); -- clear interrupt request + we_mc <= mcbit(34); -- write enable (combinatorial) microcode + we_mc_l <= mcbit(35); -- write enable (latched) microcode + mc_eop <= mcbit(36); -- end of instruction reached + mc_vda <= mcbit(37); -- microcode VDA + mc_vpa <= mcbit(38); -- microcode VPA + mc_ml <= mcbit(39); -- microcode ML + i_vp <= mcbit(40); -- vector pull + ai_op <= mcbit(41); -- opcode with addressing indexed microcode + dmux_sel <= mcbit(44 downto 42); -- data multiplexer microcode + ope <= eop; + i_addr_bus <= k_bus & pc_bus; + eop <= '1' when mc_eop = '1' or e_eop = '1' else '0'; + vp <= not i_vp; + op_exp <= two_byte_op; + vda <= m_sync or mc_vda; + vpa <= m_sync or mc_vpa; + ml <= mc_ml; + sw_int <= opbrk or opcop; + + -- ALU/memory size + m_size8 <= '1' when emu = '1' or m_bit = '1' else + '1' when op_bus = x"EB" or op_bus = x"AB" else -- when XBA and PLB opcodes the ALU size is always 8 bit + '1' when (op_bus = x"AA" or op_bus = x"A8") and x_bit = '1' else -- when TAX and TAY opcodes and X is '1' the ALU size is 8 bit + '1' when (op_bus = x"8A" or op_bus = x"98") and m_bit = '1' else -- when TXA and TXA opcodes and M is '1' the ALU size is 8 bit + '1' when op_bus = x"68" and m_bit = '1' else -- when PLA opcode and M is '1' the ALU size is 8 bit + '1' when (op_bus = x"FA" or op_bus = x"7A") and x_bit = '1' else -- when PLX or PLY opcode and X = '1' the ALU size is 8 bit + '0'; + m_size16 <= '0' when (op_bus = x"5B" or op_bus = x"7B") else -- when TCD or TDC opcodes the transfer size is always 16 bit + '0' when (op_bus = x"1B" or op_bus = x"3B") else -- when TCS or TSC opcodes the transfer size is always 16 bit + '0' when (op_bus = x"82" or op_bus = x"62") else -- when BRL or PER opcodes the transfer size is always 16 bit + '0' when op_bus = x"2B" else -- when PLD opcode the transfer size is always 16 bit + '0' when (op_bus = x"AB" and two_byte_op = '1') and emu = '0' else -- when PLR opcode and native mode + '0' when ld_acc = '1' and m_bit = '0' else -- when load accumulator C register + '0' when ld_xy = '1' and x_bit = '0' else -- when load X/Y registers (16 bit size) + '1'; + s_size16 <= '0' when op_bus = x"EB" else '1'; -- special case for XBA: accumulator size is 16 bit so it can reloads itself swapped in only one cycle + m_size <= m_size8 and m_size16; -- ALU size + acc_size <= m_size8 and m_size16 and s_size16; -- accumulator register C size + index_size <= emu or x_bit; -- index registers size + + -- S native/emulation mode (set by XCE opcode and E bit) + sp_emu <= p_bus(0) when op_bus = x"FB" else emu; + + -- register operations + a_l_lsb <= regbit(0); -- A load lsb + a_l_msb <= regbit(1); -- A load msb + a_dec <= regbit(2); -- A decrement + x_l_lsb <= regbit(3); -- X load lsb + x_l_msb <= regbit(4); -- X load msb + x_d <= regbit(5); -- X -= 1 + x_u <= regbit(6); -- X += 1 + y_l_lsb <= regbit(7); -- Y load lsb + y_l_msb <= regbit(8); -- Y load msb + y_d <= regbit(9); -- Y -= 1 + y_u <= regbit(10); -- Y += 1 + d_l_lsb <= regbit(11); -- D load lsb + d_l_msb <= regbit(12); -- D load msb + o_l <= regbit(13); -- O load msb & lsb + o_l_lsb <= regbit(14); -- O load lsb + o_l_msb <= regbit(15); -- O load msb + sp_ll <= regbit(16); -- S load lsb + sp_lh <= regbit(17); -- S load msb + sp_u <= regbit(18); -- S += 1 + sp_d <= regbit(19); -- S -= 1 + k_l <= regbit(20); -- PBR K load + b_l <= regbit(21); -- DBR B load + k_cl <= regbit(22); -- PBR K clear + b_cl <= regbit(23); -- DBR B clear + mul_l_res <= regbit(24); -- load multiplication result on A/B and X + mul_init <= regbit(25); -- init multiplier + mul_start_u <= regbit(26); -- start multiplier unsigned + mul_start_s <= regbit(27); -- start multiplier signed + wai_set <= regbit(28); -- WAI enter wait + stp_set <= regbit(29); -- STP enter wait + we <= we_mc or opfetch; -- write enable + m_bit <= p_bus(5) or emu; -- M bit + x_bit <= p_bus(4) or emu; -- X bit + m <= m_bit; + x <= x_bit; + kr_clear <= i_res or k_cl; + br_clear <= i_res or b_cl; + ld_acc <= regbit(0) and regbit(1); + ld_xy <= (regbit(3) and regbit(4)) or (regbit(7) and regbit(8)); + -- VPA latched + process(clk0) + begin + if (clk0'event and clk0 = '1') then + if i_rdy = '0' then + m_sync <= i_sync; + else + m_sync <= m_sync; + end if; + end if; + end process; + + -- PC carry logic + process(o_bus,pc_c_alu_flg) + begin + if o_bus(7) = '0' then -- check for positive/negative branch offset (bit 7) + pcc <= pc_c_alu_flg; + else + pcc <= not pc_c_alu_flg; + end if; + end process; + + -- write enable registered + process(clk0) + begin + if (clk0'event and clk0 = '1') then + if i_res = '1' then + we_r <= '1'; + else + if i_rdy = '0' then + we_r <= we_mc_l; + else + we_r <= we_r; + end if; + end if; + end if; + end process; + + rw <= we and we_r; + + -- WAI + process(clk0) + begin + if (clk0'event and clk0 = '1') then + if wai_ff = '0' then + if wai_set then + wai_ff <= '1'; + else + wai_ff <= wai_ff; + end if; + else + if i_res = '1' or i_nmi = '1' or i_irq = '1' then + wai_ff <= '0'; + else + wai_ff <= wai_ff; + end if; + end if; + end if; + end process; + rdy_out <= not wai_ff; + + -- STP + process(clk0) + begin + if (clk0'event and clk0 = '1') then + if stp_ff = '0' then + if stp_set then + stp_ff <= '1'; + else + stp_ff <= stp_ff; + end if; + else + if i_res = '1' then + stp_ff <= '0'; + else + stp_ff <= stp_ff; + end if; + end if; + end if; + end process; + stp_out <= not stp_ff; + + + -- data bus tristate (buffer ring gated) control logic + --process(clk0,we,we_r,alu_bus) + --begin + -- if clock = '0' and (we = '0' or we_r = '0') then + -- data <= alu_bus; + -- else + -- data <= "ZZZZZZZZ"; + -- end if; + --end process; + + + data_out <= alu_bus(7 downto 0); + dbin <= data_in or "00000000"; + -- DEBUG +-- a_reg <= a_bus; +-- x_reg <= x_bus; +-- y_reg <= y_bus; +-- s_reg <= sp_bus; +-- op_reg <= o_bus; +-- p_reg <= p_bus; +-- k_reg <= k_bus; +-- b_reg <= b_bus; +-- o_reg <= op_bus; +-- mcode <= mcscan; + +end struct; + + + Index: v65c816_bench.vhd =================================================================== --- v65c816_bench.vhd (nonexistent) +++ v65c816_bench.vhd (revision 2) @@ -0,0 +1,262 @@ +--------------------------------------------------------------------------------------- +-- CN3 glue logic -- +-- autoinitializing logic -- +-- full synchronous logic design -- +-- full VHDL-RTL style coding design -- +-- target: ALTERA CPLD MAX II EPM570F256C5 -- +-- project by Valerio Venturi ELMA Riva del Garda (TN) Italy (2009) -- +-- Date: 16/10/2009 -- +--------------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types + +-- global architecture +entity v65c816_bench is +end v65c816_bench; + +use work.v65c816; + +architecture behavior of v65c816_bench is + component v65c816 is + port( clk0: in STD_LOGIC; -- PHASE0 clock input + res: in STD_LOGIC; -- reset input + irq: in STD_LOGIC; -- interrupt request input + nmi: in STD_LOGIC; -- not maskable interrupt input + rdy: in STD_LOGIC; -- wait state input (read/write) + rw: out STD_LOGIC; -- read/write out + vpa: out STD_LOGIC; -- vpa + vda: out STD_LOGIC; -- vda + vp: out STD_LOGIC; -- vector pull + ope: out STD_LOGIC; -- microcode end + e: out STD_LOGIC; -- emulation (1)/native mode (0) + m: out STD_LOGIC; -- M status + x: out STD_LOGIC; -- X status + op_exp: out STD_LOGIC; -- two byte instruction running + addr: out STD_LOGIC_VECTOR(23 downto 0); -- 16 bit address bus out + data_in: in STD_LOGIC_VECTOR(7 downto 0); -- 8 bit input data bus + data_out: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit output data bus + a_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit A register + x_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit X register + y_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Y register + s_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit S register + op_reg: out STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Operand register + p_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit P register + k_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit K register + b_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit B register + o_reg: out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit Opcode register + mcode: out STD_LOGIC_VECTOR(3 downto 0) -- 4 bit microcode sequence register + ); + end component; + + signal clk0,res,irq,nmi,rdy,rw,vpa,vda,vp,ope,e,m,x,op_exp: STD_LOGIC; + signal addr: STD_LOGIC_VECTOR(23 downto 0); + signal data_in: STD_LOGIC_VECTOR(7 downto 0); + signal data_out: STD_LOGIC_VECTOR(7 downto 0); + signal a_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit A register + signal x_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit X register + signal y_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Y register + signal s_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit S register + signal op_reg: STD_LOGIC_VECTOR(15 downto 0); -- 16 bit Operand register + signal p_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit P register + signal k_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit K register + signal b_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit B register + signal o_reg: STD_LOGIC_VECTOR(7 downto 0); -- 8 bit Opcode register + signal mcode: STD_LOGIC_VECTOR(3 downto 0); -- 4 bit microcode sequence register + + constant clk_period: time := 50 ns; + --signal clock: STD_LOGIC := '0'; + + begin + u1: v65c816 port map( + clk0, + res, + irq, + nmi, + rdy, + rw, + vpa, + vda, + vp, + ope, + e, + m, + x, + op_exp, + addr, + data_in, + data_out, + a_reg, + x_reg, + y_reg, + s_reg, + op_reg, + p_reg, + k_reg, + b_reg, + o_reg, + mcode + ); + + + tst_clock: process -- 10 MHZ (period 100 ns) clock generation + variable clktmp: STD_LOGIC := '0'; + begin + clktmp := not clktmp; + clk0 <= clktmp; + wait for 50 ns; + end process; + + stimulus: process + begin + -- signal initialization before reset + res <= '0'; + irq <= '1'; + nmi <= '1'; + rdy <= '1'; + wait for 350 ns; + + -- device reset completed + res <= '1'; + wait for 600 ns; + data_in <= "00000000"; -- fetch lsb reset PC vector 0x00 + wait for 50 ns; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11000001"; -- fetch msb reset PC vector 0xc1 (0xc100) + wait for 70 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "00011000"; -- CLC + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "11111011"; -- XCE + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "ZZZZZZZZ"; -- XCE execution + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "11000010"; -- REP #%00100000 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "00100000"; -- $20 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "10101001"; -- LDA #$0000 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "00000000"; -- $00 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "00000000"; -- $00 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + wait for 50 ns; + data_in <= "00011000"; -- CLC + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "01101001"; -- ADC #$0001 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "00000001"; -- $01 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "00000000"; -- $00 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "00111000"; -- SEC + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11101001"; -- SBC #0002 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "00000010"; -- $02 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "00000000"; -- $00 + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11101010"; -- NOP + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11101010"; -- NOP + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11101010"; -- NOP + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11101010"; -- NOP + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11101010"; -- NOP + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + data_in <= "ZZZZZZZZ"; + wait for 50 ns; + data_in <= "11101010"; -- NOP + wait for 50 ns; + data_in <= "ZZZZZZZZ"; + + + --wait for 1000000 ns; + wait; + end process; +end behavior; + + + Index: xr.vhd =================================================================== --- xr.vhd (nonexistent) +++ xr.vhd (revision 2) @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit index register "X" +entity xr is + port( clk: in STD_LOGIC; + fwait: in STD_LOGIC; + size: in STD_LOGIC; + ld_lsb: in STD_LOGIC; + ld_msb: in STD_LOGIC; + ld_mul_msb: in STD_LOGIC; + u: in STD_LOGIC; + d: in STD_LOGIC; + din: in STD_LOGIC_VECTOR(15 downto 0); + mul_msb: in STD_LOGIC_VECTOR(15 downto 0); + dout: out STD_LOGIC_VECTOR(15 downto 0) + ); +end xr; + +architecture rtl of xr is +signal reg: STD_LOGIC_VECTOR(15 downto 0); +signal op: STD_LOGIC_VECTOR(4 downto 0); +begin + op <= ld_mul_msb & u & d & ld_msb & ld_lsb; + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + case op is + when "00001" => reg(7 downto 0) <= din(7 downto 0); -- load lsb + reg(15 downto 8) <= reg(15 downto 8); + when "00010" => reg(15 downto 8) <= din(7 downto 0); -- load msb + reg(7 downto 0) <= reg(7 downto 0); + when "00011" => reg <= din; -- load msb & lsb + when "00100" => reg <= reg - "0000000000000001"; -- decrement + when "01000" => reg <= reg + "0000000000000001"; -- increment + when "10000" => reg <= mul_msb; -- load multiplication msb result + when others => reg <= reg; + end case; + if size = '1' then + reg(15 downto 8) <= (others => '0'); -- with size = '1' (X = '1') the msb of index register is always zero + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + + Index: yr.vhd =================================================================== --- yr.vhd (nonexistent) +++ yr.vhd (revision 2) @@ -0,0 +1,54 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_unsigned.all; +use IEEE.STD_LOGIC_arith.all; + +-- 16 bit index register "Y" +entity yr is + port( clk: in STD_LOGIC; + fwait: in STD_LOGIC; + size: in STD_LOGIC; + ld_lsb: in STD_LOGIC; + ld_msb: in STD_LOGIC; + u: in STD_LOGIC; + d: in STD_LOGIC; + din: in STD_LOGIC_VECTOR(15 downto 0); + dout: out STD_LOGIC_VECTOR(15 downto 0) + ); +end yr; + +architecture rtl of yr is +signal reg: STD_LOGIC_VECTOR(15 downto 0); +signal op: STD_LOGIC_VECTOR(3 downto 0); +begin + op <= u & d & ld_msb & ld_lsb; + process(clk) + begin + if (clk'event and clk = '1') then + if fwait = '1' then + reg <= reg; + else + if fwait = '1' then + reg <= reg; + else + case op is + when "0001" => reg(7 downto 0) <= din(7 downto 0); -- load lsb + reg(15 downto 8) <= reg(15 downto 8); + when "0010" => reg(15 downto 8) <= din(7 downto 0); -- load msb + reg(7 downto 0) <= reg(7 downto 0); + when "0011" => reg <= din; -- load msb & lsb + when "0100" => reg <= reg - "0000000000000001"; -- decrement + when "1000" => reg <= reg + "0000000000000001"; -- increment + when others => reg <= reg; + end case; + if size = '1' then + reg(15 downto 8) <= (others => '0'); -- with size = '1' (X = '1') the msb of index register is always zero + end if; + end if; + end if; + end if; + end process; + dout <= reg; +end rtl; + +

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