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URL https://opencores.org/ocsvn/wb2axi4/wb2axi4/trunk

Subversion Repositories wb2axi4

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  • This comparison shows the changes necessary to convert path
    /wb2axi4/trunk/rtl/ifaces
    from Rev 2 to Rev 3
    Reverse comparison

Rev 2 → Rev 3

/wishbone_if.sv
7,7 → 7,7
interface wishbone_if #(
WB_ADR_WIDTH = 32,
WB_BTE_WIDTH = 2 ,
WB_CIT_WIDTH = 3 ,
WB_CTI_WIDTH = 3 ,
WB_DAT_WIDTH = 32,
WB_TGA_WIDTH = 8,
WB_TGD_WIDTH = 8,
15,74 → 15,63
WB_SEL_WIDTH = 4
 
);
logic [WB_ADR_WIDTH -1 : 0] ADR;
logic [WB_TGA_WIDTH -1 :0 ] TGA;
logic [WB_DAT_WIDTH -1 : 0] DAT_I;
logic [WB_TGD_WIDTH -1 : 0] TGD_I;
logic [WB_DAT_WIDTH -1 : 0] DAT_O;
logic [WB_TGD_WIDTH -1 : 0] TGD_I;
logic [WB_TGD_WIDTH -1 : 0] TGD_O;
logic ACK_I;
logic [WB_ADR_WIDTH -1 : 0] ADR_O;
logic CYC_O;
logic ERR_I;
logic LOCK_O;
logic RTY_I;
logic [WB_SEL_WIDTH -1 : 0] SEL_O;
logic STB_O;
logic [WB_TGA_WIDTH -1 :0 ] TGA_O;
logic [WB_TGA_WIDTH -1 :0 ] TGC_O;
logic WE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_I;
logic [WB_CTI_WIDTH -1 :0 ] CTI_O;
logic [WB_CTI_WIDTH -1 :0 ] CTI_I;
logic WE;
logic [WB_SEL_WIDTH -1 : 0] SEL;
logic STB;
logic ACK;
logic CYC;
logic ERR;
logic LOCK;
logic [WB_BTE_WIDTH -1 :0 ] BTE;
logic RTY;
logic [WB_CTI_WIDTH -1 :0 ] CTI;
logic [WB_TGA_WIDTH -1 :0 ] TGC;
 
 
logic ACK_O;
logic [WB_ADR_WIDTH -1 : 0] ADR_I;
logic CYC_I;
logic ERR_O;
logic LOCK_I;
logic RTY_O;
logic [WB_SEL_WIDTH -1 : 0] SEL_I;
logic [WB_TGA_WIDTH -1 :0 ] TGA_I;
logic [WB_TGA_WIDTH -1 :0 ] TGC_I;
logic WE_I;
 
modport master(
output ADR_O,
output TGA_O,
output ADR ,
output TGA ,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
output WE_O,
output SEL_O,
output STB_O,
input ACK_I,
output CYC_O,
input ERR_I,
output LOCK_O,
output BTE_O,
input RTY_I,
output TGC_O
output WE ,
output SEL ,
output STB ,
input ACK ,
output CYC ,
input ERR ,
output LOCK ,
output BTE ,
input RTY ,
output CTI ,
output TGC
);
 
modport slave(
output ADR_I,
output TGA_I,
input ADR ,
input TGA ,
output DAT_O,
output TGD_O,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
output WE_I,
output SEL_I,
output STB_I,
input ACK_O,
output CYC_I,
input ERR_O,
output LOCK_I,
input BTE_I,
input RTY_O,
output TGC_I
input WE ,
input SEL ,
input STB ,
output ACK ,
input CYC ,
output ERR ,
input LOCK ,
input BTE ,
output RTY ,
input CTI ,
input TGC
);
 
 
/axi_if.sv
1,59 → 1,59
interface axi_if
#(AXI_WID_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
AXI_DATA_WIDTH = 32,
AXI_PROT_WIDTH = 3,
AXI_STB_WIDTH = 4,
AXI_LEN_W = 4,
AXI_ASIZE_W = 3,
AXI_ABURST_W = 2,
AXI_ALOCK_W = 2,
AXI_ACACHE_W = 4,
AXI_RESP_W = 2
#(AXI_ID_W = 8,
AXI_ADDR_W = 32,
AXI_DATA_W = 32,
AXI_PROT_W = 3,
AXI_STB_W = 4,
AXI_LEN_W = 4,
AXI_SIZE_W = 3,
AXI_BURST_W = 2,
AXI_LOCK_W = 2,
AXI_CACHE_W = 4,
AXI_RESP_W = 2
)
();
 
//Write control channel signals
logic [AXI_WID_WIDTH - 1:0] AWID ;
logic [AXI_ADDR_WIDTH - 1:0] AWADDR ;
logic [AXI_LEN_W - 1:0] AWLEN ;
logic [AXI_ASIZE_W - 1:0] AWSIZE ;
logic [AXI_ABURST_W - 1:0] AWBURST ;
logic [AXI_ALOCK_W - 1:0] AWLOCK ;
logic [AXI_ACACHE_W - 1:0] AWCACHE ;
logic [AXI_PROT_WIDTH - 1:0] AWPROT ;
logic AWVALID ;
logic AWREADY ;
logic [AXI_ID_W - 1:0] AWID ;
logic [AXI_ADDR_W - 1:0] AWADDR ;
logic [AXI_LEN_W - 1:0] AWLEN ;
logic [AXI_SIZE_W - 1:0] AWSIZE ;
logic [AXI_BURST_W - 1:0] AWBURST ;
logic [AXI_LOCK_W - 1:0] AWLOCK ;
logic [AXI_CACHE_W - 1:0] AWCACHE ;
logic [AXI_PROT_W - 1:0] AWPROT ;
logic AWVALID ;
logic AWREADY ;
//write data channel signals
logic [AXI_WID_WIDTH - 1:0] WID ;
logic [AXI_DATA_WIDTH - 1:0] WDATA ;
logic [AXI_STB_WIDTH - 1:0] WSTRB ;
logic WLAST ;
logic WVALID ;
logic WREADY ;
logic [AXI_ID_W - 1:0 ] WID ;
logic [AXI_DATA_W - 1:0] WDATA ;
logic [AXI_STB_W - 1:0] WSTRB ;
logic WLAST ;
logic WVALID ;
logic WREADY ;
//write response channel
logic [AXI_WID_WIDTH - 1:0] BID ;
logic [AXI_RESP_W - 1:0] BRESP ;
logic BVALID ;
logic BREADY ;
logic [AXI_ID_W - 1:0] BID ;
logic [AXI_RESP_W - 1:0] BRESP ;
logic BVALID ;
logic BREADY ;
//Read control channel signals
logic [AXI_WID_WIDTH - 1:0] ARID ;
logic [AXI_ADDR_WIDTH - 1:0] ARADDR ;
logic [AXI_ID_W - 1:0] ARID ;
logic [AXI_ADDR_W - 1:0] ARADDR ;
logic [AXI_LEN_W - 1:0] ARLEN ;
logic [AXI_ASIZE_W - 1:0] ARSIZE ;
logic [AXI_ABURST_W - 1:0] ARBURST ;
logic [AXI_ALOCK_W - 1:0] ARLOCK ;
logic [AXI_ACACHE_W - 1:0] ARCACHE ;
logic [AXI_PROT_WIDTH - 1:0] ARPROT ;
logic [AXI_SIZE_W - 1:0] ARSIZE ;
logic [AXI_BURST_W - 1:0] ARBURST ;
logic [AXI_LOCK_W - 1:0] ARLOCK ;
logic [AXI_CACHE_W - 1:0] ARCACHE ;
logic [AXI_PROT_W - 1:0] ARPROT ;
logic ARVALID ;
logic ARREADY ;
//Read data channel signals
logic [AXI_WID_WIDTH - 1:0] RID ;
logic [AXI_DATA_WIDTH - 1:0] RDATA ;
logic [AXI_RESP_W - 1:0] RRESP ;
logic RLAST ;
logic RVALID ;
logic RREADY ;
logic [AXI_ID_W - 1:0] RID ;
logic [AXI_DATA_W - 1:0] RDATA ;
logic [AXI_RESP_W - 1:0] RRESP ;
logic RLAST ;
logic RVALID ;
logic RREADY ;
 
modport initiator (
//Write control channel signals

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