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[/] [a-z80/] [trunk/] [cpu/] [alu/] [alu_flags.v] - Diff between revs 14 and 16

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Line 12... Line 12...
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
// applicable agreement for further details.
 
 
// PROGRAM              "Quartus II 64-Bit"
// PROGRAM              "Quartus II 64-Bit"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED              "Fri Dec 09 21:55:51 2016"
// CREATED              "Sat Dec 10 09:01:30 2016"
 
 
module alu_flags(
module alu_flags(
        ctl_flags_oe,
        ctl_flags_oe,
        ctl_flags_bus,
        ctl_flags_bus,
        ctl_flags_alu,
        ctl_flags_alu,
Line 44... Line 44...
        ctl_flags_nf_clr,
        ctl_flags_nf_clr,
        ctl_alu_zero_16bit,
        ctl_alu_zero_16bit,
        clk,
        clk,
        ctl_flags_cf2_sel_shift,
        ctl_flags_cf2_sel_shift,
        ctl_flags_cf2_sel_daa,
        ctl_flags_cf2_sel_daa,
        hold_clk_wait,
        nhold_clk_wait,
        flags_sf,
        flags_sf,
        flags_zf,
        flags_zf,
        flags_hf,
        flags_hf,
        flags_pf,
        flags_pf,
        flags_cf,
        flags_cf,
Line 86... Line 86...
input wire      ctl_flags_nf_clr;
input wire      ctl_flags_nf_clr;
input wire      ctl_alu_zero_16bit;
input wire      ctl_alu_zero_16bit;
input wire      clk;
input wire      clk;
input wire      ctl_flags_cf2_sel_shift;
input wire      ctl_flags_cf2_sel_shift;
input wire      ctl_flags_cf2_sel_daa;
input wire      ctl_flags_cf2_sel_daa;
input wire      hold_clk_wait;
input wire      nhold_clk_wait;
output wire     flags_sf;
output wire     flags_sf;
output wire     flags_zf;
output wire     flags_zf;
output wire     flags_hf;
output wire     flags_hf;
output wire     flags_pf;
output wire     flags_pf;
output wire     flags_cf;
output wire     flags_cf;
Line 109... Line 109...
wire    SYNTHESIZED_WIRE_3;
wire    SYNTHESIZED_WIRE_3;
wire    SYNTHESIZED_WIRE_4;
wire    SYNTHESIZED_WIRE_4;
wire    SYNTHESIZED_WIRE_5;
wire    SYNTHESIZED_WIRE_5;
wire    SYNTHESIZED_WIRE_6;
wire    SYNTHESIZED_WIRE_6;
wire    SYNTHESIZED_WIRE_7;
wire    SYNTHESIZED_WIRE_7;
reg     SYNTHESIZED_WIRE_41;
reg     SYNTHESIZED_WIRE_39;
wire    SYNTHESIZED_WIRE_42;
wire    SYNTHESIZED_WIRE_8;
wire    SYNTHESIZED_WIRE_9;
wire    SYNTHESIZED_WIRE_9;
 
wire    SYNTHESIZED_WIRE_10;
wire    SYNTHESIZED_WIRE_11;
wire    SYNTHESIZED_WIRE_11;
wire    SYNTHESIZED_WIRE_12;
wire    SYNTHESIZED_WIRE_12;
wire    SYNTHESIZED_WIRE_13;
wire    SYNTHESIZED_WIRE_13;
wire    SYNTHESIZED_WIRE_14;
wire    SYNTHESIZED_WIRE_14;
wire    SYNTHESIZED_WIRE_15;
wire    SYNTHESIZED_WIRE_15;
Line 124... Line 125...
wire    SYNTHESIZED_WIRE_18;
wire    SYNTHESIZED_WIRE_18;
wire    SYNTHESIZED_WIRE_19;
wire    SYNTHESIZED_WIRE_19;
wire    SYNTHESIZED_WIRE_20;
wire    SYNTHESIZED_WIRE_20;
wire    SYNTHESIZED_WIRE_21;
wire    SYNTHESIZED_WIRE_21;
wire    SYNTHESIZED_WIRE_22;
wire    SYNTHESIZED_WIRE_22;
wire    SYNTHESIZED_WIRE_23;
 
wire    SYNTHESIZED_WIRE_24;
 
reg     DFFE_inst_latch_sf;
reg     DFFE_inst_latch_sf;
wire    SYNTHESIZED_WIRE_25;
wire    SYNTHESIZED_WIRE_23;
reg     DFFE_inst_latch_pf;
reg     DFFE_inst_latch_pf;
reg     DFFE_inst_latch_nf;
reg     DFFE_inst_latch_nf;
 
wire    SYNTHESIZED_WIRE_24;
 
wire    SYNTHESIZED_WIRE_25;
wire    SYNTHESIZED_WIRE_26;
wire    SYNTHESIZED_WIRE_26;
wire    SYNTHESIZED_WIRE_27;
wire    SYNTHESIZED_WIRE_27;
wire    SYNTHESIZED_WIRE_28;
wire    SYNTHESIZED_WIRE_28;
wire    SYNTHESIZED_WIRE_29;
wire    SYNTHESIZED_WIRE_29;
wire    SYNTHESIZED_WIRE_30;
wire    SYNTHESIZED_WIRE_40;
wire    SYNTHESIZED_WIRE_31;
wire    SYNTHESIZED_WIRE_32;
wire    SYNTHESIZED_WIRE_43;
wire    SYNTHESIZED_WIRE_33;
wire    SYNTHESIZED_WIRE_34;
wire    SYNTHESIZED_WIRE_34;
wire    SYNTHESIZED_WIRE_35;
wire    SYNTHESIZED_WIRE_35;
wire    SYNTHESIZED_WIRE_36;
wire    SYNTHESIZED_WIRE_36;
wire    SYNTHESIZED_WIRE_37;
wire    SYNTHESIZED_WIRE_37;
wire    SYNTHESIZED_WIRE_38;
 
wire    SYNTHESIZED_WIRE_39;
 
reg     DFFE_inst_latch_cf;
reg     DFFE_inst_latch_cf;
reg     DFFE_inst_latch_cf2;
reg     DFFE_inst_latch_cf2;
wire    SYNTHESIZED_WIRE_40;
wire    SYNTHESIZED_WIRE_38;
 
 
assign  flags_sf = DFFE_inst_latch_sf;
assign  flags_sf = DFFE_inst_latch_sf;
assign  flags_zf = SYNTHESIZED_WIRE_41;
assign  flags_zf = SYNTHESIZED_WIRE_39;
assign  flags_hf = SYNTHESIZED_WIRE_25;
assign  flags_hf = SYNTHESIZED_WIRE_23;
assign  flags_pf = DFFE_inst_latch_pf;
assign  flags_pf = DFFE_inst_latch_pf;
assign  flags_cf = SYNTHESIZED_WIRE_26;
assign  flags_cf = SYNTHESIZED_WIRE_24;
assign  flags_nf = DFFE_inst_latch_nf;
assign  flags_nf = DFFE_inst_latch_nf;
assign  flags_cf_latch = DFFE_inst_latch_cf;
assign  flags_cf_latch = DFFE_inst_latch_cf;
assign  SYNTHESIZED_WIRE_40 = 0;
assign  SYNTHESIZED_WIRE_38 = 0;
 
 
 
 
 
 
assign  SYNTHESIZED_WIRE_12 = db[7] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
 
 
assign  SYNTHESIZED_WIRE_19 = alu_xf_out & ctl_flags_alu;
assign  SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
 
 
assign  SYNTHESIZED_WIRE_22 = db[2] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
 
 
assign  SYNTHESIZED_WIRE_21 = pf_sel & ctl_flags_alu;
assign  SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
 
 
assign  SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
 
 
assign  SYNTHESIZED_WIRE_25 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
assign  SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
 
 
assign  SYNTHESIZED_WIRE_24 = db[0] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
 
 
assign  SYNTHESIZED_WIRE_23 = ctl_flags_alu & alu_core_cf_out;
assign  SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
 
 
assign  SYNTHESIZED_WIRE_9 =  ~ctl_flags_cf2_we;
assign  SYNTHESIZED_WIRE_8 =  ~ctl_flags_cf2_we;
 
 
assign  SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
assign  SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
 
 
assign  SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
assign  SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
 
 
assign  SYNTHESIZED_WIRE_11 = alu_sf_out & ctl_flags_alu;
assign  SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
 
 
assign  SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
assign  SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
 
 
assign  SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
assign  SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
 
 
 
 
assign  SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
assign  SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
 
 
assign  SYNTHESIZED_WIRE_6 =  ~ctl_flags_nf_clr;
assign  SYNTHESIZED_WIRE_6 =  ~ctl_flags_nf_clr;
 
 
assign  SYNTHESIZED_WIRE_7 =  ~ctl_alu_zero_16bit;
assign  SYNTHESIZED_WIRE_7 =  ~ctl_alu_zero_16bit;
 
 
assign  SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_41;
assign  SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39;
 
 
assign  SYNTHESIZED_WIRE_42 =  ~hold_clk_wait;
assign  SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;
 
 
assign  SYNTHESIZED_WIRE_29 = ctl_flags_cf_we & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_9;
assign  SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;
 
 
assign  SYNTHESIZED_WIRE_31 = ctl_flags_cf2_we & SYNTHESIZED_WIRE_42;
assign  SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
 
 
assign  SYNTHESIZED_WIRE_14 = db[6] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
 
 
assign  SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
assign  SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
 
 
assign  SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
assign  SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
 
 
assign  SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
assign  SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
 
 
assign  SYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
assign  SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
 
 
assign  SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
assign  SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
 
 
assign  SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
assign  SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
 
 
assign  SYNTHESIZED_WIRE_13 = alu_zero & ctl_flags_alu;
assign  SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
 
 
assign  SYNTHESIZED_WIRE_28 = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24;
 
 
 
assign  db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
assign  db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
 
 
assign  SYNTHESIZED_WIRE_16 = db[5] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
 
 
assign  db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_41 : 1'bz;
assign  db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;
 
 
assign  db[5] = ctl_flags_oe ? flags_yf : 1'bz;
assign  db[5] = ctl_flags_oe ? flags_yf : 1'bz;
 
 
assign  db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_25 : 1'bz;
assign  db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
 
 
assign  db[3] = ctl_flags_oe ? flags_xf : 1'bz;
assign  db[3] = ctl_flags_oe ? flags_xf : 1'bz;
 
 
assign  db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
assign  db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
 
 
assign  db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
assign  db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
 
 
assign  db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_26 : 1'bz;
assign  db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
 
 
assign  SYNTHESIZED_WIRE_15 = alu_yf_out & ctl_flags_alu;
assign  SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
 
 
assign  SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_27;
assign  SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
 
 
assign  SYNTHESIZED_WIRE_18 = db[4] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
 
 
assign  SYNTHESIZED_WIRE_17 = alu_core_cf_out & ctl_flags_alu;
assign  SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
 
 
assign  SYNTHESIZED_WIRE_20 = db[3] & ctl_flags_bus;
assign  SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (SYNTHESIZED_WIRE_29)
if (SYNTHESIZED_WIRE_27)
        begin
        begin
        DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_28;
        DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (SYNTHESIZED_WIRE_31)
if (SYNTHESIZED_WIRE_29)
        begin
        begin
        DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_30;
        DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_hf_we)
if (ctl_flags_hf_we)
        begin
        begin
        DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_43;
        DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_hf2_we)
if (ctl_flags_hf2_we)
        begin
        begin
        flags_hf2 <= SYNTHESIZED_WIRE_43;
        flags_hf2 <= SYNTHESIZED_WIRE_40;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_nf_we)
if (ctl_flags_nf_we)
        begin
        begin
        DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_34;
        DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_pf_we)
if (ctl_flags_pf_we)
        begin
        begin
        DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_35;
        DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_sz_we)
if (ctl_flags_sz_we)
        begin
        begin
        DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_36;
        DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_xy_we)
if (ctl_flags_xy_we)
        begin
        begin
        flags_xf <= SYNTHESIZED_WIRE_37;
        flags_xf <= SYNTHESIZED_WIRE_35;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_xy_we)
if (ctl_flags_xy_we)
        begin
        begin
        flags_yf <= SYNTHESIZED_WIRE_38;
        flags_yf <= SYNTHESIZED_WIRE_36;
        end
        end
end
end
 
 
 
 
always@(posedge clk)
always@(posedge clk)
begin
begin
if (ctl_flags_sz_we)
if (ctl_flags_sz_we)
        begin
        begin
        SYNTHESIZED_WIRE_41 <= SYNTHESIZED_WIRE_39;
        SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;
        end
        end
end
end
 
 
 
 
alu_mux_2       b2v_inst_mux_cf(
alu_mux_2       b2v_inst_mux_cf(
        .in0(DFFE_inst_latch_cf),
        .in0(DFFE_inst_latch_cf),
        .in1(DFFE_inst_latch_cf2),
        .in1(DFFE_inst_latch_cf2),
        .sel1(ctl_flags_use_cf2),
        .sel1(ctl_flags_use_cf2),
        .out(SYNTHESIZED_WIRE_27));
        .out(SYNTHESIZED_WIRE_25));
 
 
 
 
alu_mux_4       b2v_inst_mux_cf2(
alu_mux_4       b2v_inst_mux_cf2(
        .in0(alu_core_cf_out),
        .in0(alu_core_cf_out),
        .in1(shift_cf_out),
        .in1(shift_cf_out),
        .in2(daa_cf_out),
        .in2(daa_cf_out),
        .in3(SYNTHESIZED_WIRE_40),
        .in3(SYNTHESIZED_WIRE_38),
        .sel(sel),
        .sel(sel),
        .out(SYNTHESIZED_WIRE_30));
        .out(SYNTHESIZED_WIRE_28));
 
 
assign  sel[0] = ctl_flags_cf2_sel_shift;
assign  sel[0] = ctl_flags_cf2_sel_shift;
assign  sel[1] = ctl_flags_cf2_sel_daa;
assign  sel[1] = ctl_flags_cf2_sel_daa;
 
 
endmodule
endmodule

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