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[/] [a-z80/] [trunk/] [cpu/] [bus/] [data_pins_lattice.v] - Diff between revs 13 and 17

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Rev 13 Rev 17
// Use this file with Lattice toolset instead of data_pins.v
// Use this file with Lattice toolset instead of data_pins.v
//
//
// data_pins.v is auto-generated by Altera Quartus IDE from a
// This file is provided courtesy by JuanS
// block schematic file data_pins.bdf
 
 
 
module data_pins(
module data_pins(
    bus_db_pin_oe,
    bus_db_pin_oe,
    bus_db_pin_re,
    bus_db_pin_re,
    ctl_bus_db_we,
    ctl_bus_db_we,
    clk,
    clk,
    ctl_bus_db_oe,
    ctl_bus_db_oe,
    D,
    D,
    db
    db
);
);
 
 
input wire bus_db_pin_oe;
input wire bus_db_pin_oe;
input wire bus_db_pin_re;
input wire bus_db_pin_re;
input wire ctl_bus_db_we;
input wire ctl_bus_db_we;
input wire clk;
input wire clk;
input wire ctl_bus_db_oe;
input wire ctl_bus_db_oe;
inout wire [7:0] D;
inout wire [7:0] D;
inout wire [7:0] db;
inout wire [7:0] db;
 
 
reg [7:0] dout;
reg [7:0] dout;
 
 
always@(negedge clk)
always@(negedge clk)
begin
begin
    if (ctl_bus_db_we | bus_db_pin_re)
    if (ctl_bus_db_we | bus_db_pin_re)
    begin
    begin
        if (bus_db_pin_re)
        if (bus_db_pin_re)
        dout <= D;
        dout <= D;
    else if (ctl_bus_db_we)
    else if (ctl_bus_db_we)
        dout <= db;
        dout <= db;
    end
    end
end
end
 
 
assign db = ctl_bus_db_oe ? dout : 8'hZ;
assign db = ctl_bus_db_oe ? dout : 8'hZ;
assign D = bus_db_pin_oe ? dout : 8'hZ;
assign D = bus_db_pin_oe ? dout : 8'hZ;
 
 
endmodule
endmodule
 
 

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