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[/] [a-z80/] [trunk/] [cpu/] [bus/] [data_pins_lattice.v] - Diff between revs 13 and 17
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| Rev 13 |
Rev 17 |
// Use this file with Lattice toolset instead of data_pins.v
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// Use this file with Lattice toolset instead of data_pins.v
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//
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//
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// data_pins.v is auto-generated by Altera Quartus IDE from a
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// This file is provided courtesy by JuanS
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// block schematic file data_pins.bdf
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module data_pins(
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module data_pins(
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bus_db_pin_oe,
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bus_db_pin_oe,
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bus_db_pin_re,
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bus_db_pin_re,
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ctl_bus_db_we,
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ctl_bus_db_we,
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clk,
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clk,
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ctl_bus_db_oe,
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ctl_bus_db_oe,
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D,
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D,
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db
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db
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);
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);
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input wire bus_db_pin_oe;
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input wire bus_db_pin_oe;
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input wire bus_db_pin_re;
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input wire bus_db_pin_re;
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input wire ctl_bus_db_we;
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input wire ctl_bus_db_we;
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input wire clk;
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input wire clk;
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input wire ctl_bus_db_oe;
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input wire ctl_bus_db_oe;
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inout wire [7:0] D;
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inout wire [7:0] D;
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inout wire [7:0] db;
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inout wire [7:0] db;
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reg [7:0] dout;
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reg [7:0] dout;
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always@(negedge clk)
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always@(negedge clk)
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begin
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begin
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if (ctl_bus_db_we | bus_db_pin_re)
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if (ctl_bus_db_we | bus_db_pin_re)
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begin
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begin
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if (bus_db_pin_re)
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if (bus_db_pin_re)
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dout <= D;
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dout <= D;
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else if (ctl_bus_db_we)
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else if (ctl_bus_db_we)
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dout <= db;
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dout <= db;
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end
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end
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end
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end
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assign db = ctl_bus_db_oe ? dout : 8'hZ;
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assign db = ctl_bus_db_oe ? dout : 8'hZ;
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assign D = bus_db_pin_oe ? dout : 8'hZ;
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assign D = bus_db_pin_oe ? dout : 8'hZ;
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endmodule
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endmodule
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