//==============================================================
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//==============================================================
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// Test address latch and increment block
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// Test address latch and increment block
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//==============================================================
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//==============================================================
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`timescale 1us/ 100 ns
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`timescale 1us/ 100 ns
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module test_bus;
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module test_bus;
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// ----------------- CLOCKS AND RESET -----------------
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// ----------------- CLOCKS AND RESET -----------------
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// Define one full T-clock cycle delay
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// Define one full T-clock cycle delay
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`define T #2
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`define T #2
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bit clk = 1;
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bit clk = 1;
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initial repeat (24) #1 clk = ~clk;
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initial repeat (26) #1 clk = ~clk;
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reg nreset;
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// ----------------------------------------------------
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// ----------------------------------------------------
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// Bi-directional bus that can also be tri-stated
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// Bi-directional bus that can also be tri-stated
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reg [15:0] abusw; // Drive it using this bus
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reg [15:0] abusw; // Drive it using this bus
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wire [15:0] abus; // Read it using this bus
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wire [15:0] abus; // Read it using this bus
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wire [15:0] address; // Final address ouput
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wire [15:0] address; // Final address ouput
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// ----------------- INPUT CONTROL -----------------
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// ----------------- INPUT CONTROL -----------------
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reg ctl_al_we; // Write enable to address latch
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reg ctl_al_we; // Write enable to address latch
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reg ctl_bus_inc_oe; // Write incrementer onto the internal data bus
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reg ctl_bus_inc_oe; // Write incrementer onto the internal data bus
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reg ctl_apin_mux; // Selects mux1
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reg ctl_apin_mux; // Selects mux1
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reg ctl_apin_mux2; // Selects mux2
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reg ctl_apin_mux2; // Selects mux2
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// ----------------- INC/DEC -----------------
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// ----------------- INC/DEC -----------------
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reg ctl_inc_dec; // Perform decrement (1) or increment (0)
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reg ctl_inc_dec; // Perform decrement (1) or increment (0)
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reg ctl_inc_limit6; // Limit increment to 6 bits (for incrementing IR)
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reg ctl_inc_limit6; // Limit increment to 6 bits (for incrementing IR)
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reg ctl_inc_cy; // Address increment, carry in value (+/-1 or 0)
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reg ctl_inc_cy; // Address increment, carry in value (+/-1 or 0)
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reg ctl_inc_zero; // Output zero from the incrementer
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reg clrpc; // Force zero (to clear PC/IR)
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// ----------------- OUTPUT/STATUS -----------------
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// ----------------- OUTPUT/STATUS -----------------
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wire address_is_1; // Signals when the final address is 1
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wire address_is_1; // Signals when the final address is 1
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// ----------------- TEST -------------------
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// ----------------- TEST -------------------
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`define CHECK(arg) \
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`define CHECK(arg) \
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assert(address==arg);
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assert(address==arg);
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initial begin
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initial begin
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nreset = 0;
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abusw = 'z;
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abusw = 'z;
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ctl_al_we = 0;
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ctl_al_we = 0;
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ctl_bus_inc_oe = 0;
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ctl_bus_inc_oe = 0;
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ctl_inc_dec = 0;
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ctl_inc_dec = 0;
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ctl_inc_limit6 = 0;
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ctl_inc_limit6 = 0;
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ctl_inc_cy = 0;
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ctl_inc_cy = 0;
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ctl_inc_zero = 0;
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clrpc = 0;
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ctl_apin_mux = 0;
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ctl_apin_mux = 0;
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ctl_apin_mux2 = 0;
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ctl_apin_mux2 = 0;
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//------------------------------------------------------------
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`T nreset = 1;
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Perform a simple increment and decrement
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// Perform a simple increment and decrement
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`T abusw = 16'h1234;
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`T abusw = 16'h1234;
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ctl_al_we = 1; // Write value to the latch
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ctl_al_we = 1; // Write value to the latch
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ctl_apin_mux = 1; // Output incrementer to the address bus
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ctl_apin_mux = 1; // Output incrementer to the address bus
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ctl_inc_cy = 1; // +1 show "1235"
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ctl_inc_cy = 1; // +1 show "1235"
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`T `CHECK(16'h1235);
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`T `CHECK(16'h1235);
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ctl_inc_dec = 1; // -1 show "1233"
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ctl_inc_dec = 1; // -1 show "1233"
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`T `CHECK(16'h1233);
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`T `CHECK(16'h1233);
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// ...through overflow
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// ...through overflow
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abusw = 16'hffff;
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abusw = 16'hffff;
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ctl_inc_dec = 0;
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ctl_inc_dec = 0;
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ctl_inc_cy = 1; // +1 show "0"
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ctl_inc_cy = 1; // +1 show "0"
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`T `CHECK(16'h0000);
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`T `CHECK(16'h0000);
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ctl_inc_dec = 1; // -1 show "FFFE"
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ctl_inc_dec = 1; // -1 show "FFFE"
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`T `CHECK(16'hFFFE);
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`T `CHECK(16'hFFFE);
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abusw = 16'h0;
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abusw = 16'h0;
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ctl_inc_dec = 0;
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ctl_inc_dec = 0;
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ctl_inc_cy = 1; // +1 show "1"
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ctl_inc_cy = 1; // +1 show "1"
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`T `CHECK(16'h0001);
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`T `CHECK(16'h0001);
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ctl_inc_dec = 1; // -1 show "FFFF"
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ctl_inc_dec = 1; // -1 show "FFFF"
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`T `CHECK(16'hFFFF);
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`T `CHECK(16'hFFFF);
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ctl_inc_cy = 0; // show "0000"
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ctl_inc_cy = 0; // show "0000"
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`T `CHECK(16'h0000);
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`T `CHECK(16'h0000);
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ctl_inc_dec = 0; // show "0000"
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ctl_inc_dec = 0; // show "0000"
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Test the address latch and the mux
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// Test the address latch and the mux
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`T abusw = 16'hAA50;
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`T abusw = 16'hAA50;
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ctl_al_we = 1; // Write AA55 to the latch
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ctl_al_we = 1; // Write AA55 to the latch
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ctl_inc_cy = 1;
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ctl_inc_cy = 1;
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`T ctl_al_we = 0; // show "AA51"
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`T ctl_al_we = 0; // show "AA51"
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`T `CHECK(16'hAA51);
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`T `CHECK(16'hAA51);
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ctl_apin_mux = 0;
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ctl_apin_mux = 0;
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ctl_apin_mux2 = 1;
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ctl_apin_mux2 = 1;
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Test the tri-state db
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// Test the tri-state db
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`T abusw = 'z;
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`T abusw = 'z;
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ctl_bus_inc_oe = 1; // Output latched value (AA50)
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ctl_bus_inc_oe = 1; // Output latched value (AA50)
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`T `CHECK(16'hAA50);
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`T `CHECK(16'hAA50);
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`T $display("End of test");
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`T $display("End of test");
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end
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end
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// Drive 3-state bidirectional bus with these statements
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// Drive 3-state bidirectional bus with these statements
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assign abus = abusw;
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assign abus = abusw;
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// Instantiate address latch block
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// Instantiate address latch block
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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address_latch address_latch_( .* );
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address_latch address_latch_( .* );
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endmodule
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endmodule
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