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[/] [a-z80/] [trunk/] [cpu/] [control/] [clk_delay.v] - Diff between revs 3 and 16

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Rev 3 Rev 16
Line 12... Line 12... 
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// applicable agreement for further details.
 
 
 
 
 
// PROGRAM              "Quartus II 64-Bit"
 
// PROGRAM              "Quartus II 64-Bit"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// CREATED              "Sun Nov 16 23:41:11 2014"
 
// CREATED              "Sat Dec 10 08:59:31 2016"
 
 
 
 
 
module clk_delay(
 
module clk_delay(
 
        clk,
 
        clk,
 
        in_intr,
 
        in_intr,
 
        nreset,
 
        nreset,
Line 29... Line 29... 
        hold_clk_iorq,
 
        hold_clk_iorq,
 
        hold_clk_wait,
 
        hold_clk_wait,
 
        iorq_Tw,
 
        iorq_Tw,
 
        busack,
 
        busack,
 
        pin_control_oe,
 
        pin_control_oe,
 
        hold_clk_busrq
 
        hold_clk_busrq,
 
 
 
        nhold_clk_wait
 
);
 
);
 
 
 
 
 
 
 
 
 
input wire      clk;
 
input wire      clk;
 
input wire      in_intr;
 
input wire      in_intr;
Line 48... Line 49... 
output wire     hold_clk_wait;
 
output wire     hold_clk_wait;
 
output wire     iorq_Tw;
 
output wire     iorq_Tw;
 
output wire     busack;
 
output wire     busack;
 
output wire     pin_control_oe;
 
output wire     pin_control_oe;
 
output wire     hold_clk_busrq;
 
output wire     hold_clk_busrq;
 
 
 
output wire     nhold_clk_wait;
 
 
 
 
 
reg     hold_clk_busrq_ALTERA_SYNTHESIZED;
 
reg     hold_clk_busrq_ALTERA_SYNTHESIZED;
 
wire    SYNTHESIZED_WIRE_6;
 
wire    SYNTHESIZED_WIRE_6;
 
wire    SYNTHESIZED_WIRE_1;
 
wire    SYNTHESIZED_WIRE_1;
 
reg     DFF_inst5;
 
reg     DFF_inst5;
 
reg     SYNTHESIZED_WIRE_7;
 
reg     SYNTHESIZED_WIRE_7;
 
reg     SYNTHESIZED_WIRE_8;
 
reg     SYNTHESIZED_WIRE_8;
 
wire    SYNTHESIZED_WIRE_3;
 
wire    SYNTHESIZED_WIRE_3;
 
wire    SYNTHESIZED_WIRE_4;
 
wire    SYNTHESIZED_WIRE_4;
 
wire    SYNTHESIZED_WIRE_5;
 
wire    SYNTHESIZED_WIRE_5;
 
reg     DFFE_inst;
 
reg     SYNTHESIZED_WIRE_9;
 
 
 
 
 
assign  hold_clk_wait = DFFE_inst;
 
assign  hold_clk_wait = SYNTHESIZED_WIRE_9;
 
assign  iorq_Tw = DFF_inst5;
 
assign  iorq_Tw = DFF_inst5;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_inst <= 0;
 
        SYNTHESIZED_WIRE_9 <= 0;
 
        end
 
        end
 
else
 
else
 
if (SYNTHESIZED_WIRE_1)
 
if (SYNTHESIZED_WIRE_1)
 
        begin
 
        begin
 
        DFFE_inst <= mwait;
 
        SYNTHESIZED_WIRE_9 <= mwait;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
Line 144... Line 146... 
        end
 
        end
 
end
 
end
 
 
 
 
 
assign  SYNTHESIZED_WIRE_4 = in_intr & M1 & T1;
 
assign  SYNTHESIZED_WIRE_4 = in_intr & M1 & T1;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_1 = latch_wait | DFFE_inst;
 
assign  SYNTHESIZED_WIRE_1 = latch_wait | SYNTHESIZED_WIRE_9;
 
 
 
 
 
 
 
assign  nhold_clk_wait =  ~SYNTHESIZED_WIRE_9;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_6 =  ~clk;
 
assign  SYNTHESIZED_WIRE_6 =  ~clk;
 
 
 
 
 
assign  hold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED;
 
assign  hold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED;
 
 
 
 

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