// Copyright (C) 1991-2013 Altera Corporation
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// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Wed Dec 07 00:18:12 2016"
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// CREATED "Sat Dec 10 08:55:35 2016"
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module decode_state(
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module decode_state(
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ctl_state_iy_set,
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ctl_state_iy_set,
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ctl_state_ixiy_clr,
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ctl_state_ixiy_clr,
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ctl_state_ixiy_we,
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ctl_state_ixiy_we,
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ctl_state_halt_set,
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ctl_state_halt_set,
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ctl_state_tbl_ed_set,
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ctl_state_tbl_ed_set,
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ctl_state_tbl_cb_set,
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ctl_state_tbl_cb_set,
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ctl_state_alu,
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ctl_state_alu,
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clk,
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clk,
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address_is_1,
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address_is_1,
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ctl_repeat_we,
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ctl_repeat_we,
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in_intr,
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in_intr,
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in_nmi,
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in_nmi,
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nreset,
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nreset,
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ctl_state_tbl_we,
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ctl_state_tbl_we,
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hold_clk_wait,
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nhold_clk_wait,
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in_halt,
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in_halt,
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table_cb,
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table_cb,
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table_ed,
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table_ed,
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table_xx,
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table_xx,
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use_ix,
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use_ix,
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use_ixiy,
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use_ixiy,
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in_alu,
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in_alu,
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repeat_en
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repeat_en
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);
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);
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input wire ctl_state_iy_set;
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input wire ctl_state_iy_set;
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input wire ctl_state_ixiy_clr;
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input wire ctl_state_ixiy_clr;
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input wire ctl_state_ixiy_we;
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input wire ctl_state_ixiy_we;
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input wire ctl_state_halt_set;
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input wire ctl_state_halt_set;
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input wire ctl_state_tbl_ed_set;
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input wire ctl_state_tbl_ed_set;
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input wire ctl_state_tbl_cb_set;
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input wire ctl_state_tbl_cb_set;
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input wire ctl_state_alu;
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input wire ctl_state_alu;
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input wire clk;
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input wire clk;
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input wire address_is_1;
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input wire address_is_1;
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input wire ctl_repeat_we;
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input wire ctl_repeat_we;
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input wire in_intr;
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input wire in_intr;
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input wire in_nmi;
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input wire in_nmi;
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input wire nreset;
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input wire nreset;
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input wire ctl_state_tbl_we;
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input wire ctl_state_tbl_we;
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input wire hold_clk_wait;
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input wire nhold_clk_wait;
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output reg in_halt;
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output reg in_halt;
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output wire table_cb;
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output wire table_cb;
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output wire table_ed;
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output wire table_ed;
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output wire table_xx;
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output wire table_xx;
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output wire use_ix;
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output wire use_ix;
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output wire use_ixiy;
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output wire use_ixiy;
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output wire in_alu;
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output wire in_alu;
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output wire repeat_en;
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output wire repeat_en;
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reg DFFE_instNonRep;
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reg DFFE_instNonRep;
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reg DFFE_instIY1;
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reg DFFE_instIY1;
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reg DFFE_inst4;
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reg DFFE_inst4;
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reg DFFE_instED;
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reg DFFE_instED;
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reg DFFE_instCB;
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reg DFFE_instCB;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_3;
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assign in_alu = ctl_state_alu;
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assign in_alu = ctl_state_alu;
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assign table_cb = DFFE_instCB;
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assign table_cb = DFFE_instCB;
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assign table_ed = DFFE_instED;
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assign table_ed = DFFE_instED;
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assign use_ix = DFFE_inst4;
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assign use_ix = DFFE_inst4;
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assign repeat_en = ~DFFE_instNonRep;
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assign repeat_en = ~DFFE_instNonRep;
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assign use_ixiy = DFFE_instIY1 | DFFE_inst4;
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assign use_ixiy = DFFE_instIY1 | DFFE_inst4;
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assign table_xx = ~(DFFE_instED | DFFE_instCB);
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assign table_xx = ~(DFFE_instED | DFFE_instCB);
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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DFFE_inst4 <= 0;
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DFFE_inst4 <= 0;
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end
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end
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else
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else
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if (ctl_state_ixiy_we)
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if (ctl_state_ixiy_we)
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begin
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begin
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DFFE_inst4 <= SYNTHESIZED_WIRE_0;
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DFFE_inst4 <= SYNTHESIZED_WIRE_0;
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end
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end
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end
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end
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assign SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
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assign SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
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assign SYNTHESIZED_WIRE_5 = ctl_state_tbl_we & SYNTHESIZED_WIRE_1;
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assign SYNTHESIZED_WIRE_4 = ctl_state_tbl_we & nhold_clk_wait;
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assign SYNTHESIZED_WIRE_4 = in_nmi | in_intr;
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assign SYNTHESIZED_WIRE_3 = in_nmi | in_intr;
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assign SYNTHESIZED_WIRE_1 = ~hold_clk_wait;
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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DFFE_instCB <= 0;
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DFFE_instCB <= 0;
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end
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end
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else
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else
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if (SYNTHESIZED_WIRE_5)
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if (SYNTHESIZED_WIRE_4)
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begin
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begin
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DFFE_instCB <= ctl_state_tbl_cb_set;
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DFFE_instCB <= ctl_state_tbl_cb_set;
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end
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end
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end
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end
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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DFFE_instED <= 0;
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DFFE_instED <= 0;
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end
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end
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else
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else
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if (SYNTHESIZED_WIRE_5)
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if (SYNTHESIZED_WIRE_4)
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begin
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begin
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DFFE_instED <= ctl_state_tbl_ed_set;
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DFFE_instED <= ctl_state_tbl_ed_set;
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end
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end
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end
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end
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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in_halt <= 0;
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in_halt <= 0;
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end
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end
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else
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else
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begin
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begin
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in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_4;
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in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3;
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end
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end
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end
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end
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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DFFE_instIY1 <= 0;
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DFFE_instIY1 <= 0;
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end
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end
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else
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else
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if (ctl_state_ixiy_we)
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if (ctl_state_ixiy_we)
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begin
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begin
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DFFE_instIY1 <= ctl_state_iy_set;
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DFFE_instIY1 <= ctl_state_iy_set;
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end
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end
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end
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end
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always@(posedge clk or negedge nreset)
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always@(posedge clk or negedge nreset)
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begin
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begin
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if (!nreset)
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if (!nreset)
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begin
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begin
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DFFE_instNonRep <= 0;
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DFFE_instNonRep <= 0;
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end
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end
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else
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else
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if (ctl_repeat_we)
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if (ctl_repeat_we)
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begin
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begin
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DFFE_instNonRep <= address_is_1;
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DFFE_instNonRep <= address_is_1;
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end
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end
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end
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end
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endmodule
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endmodule
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