// Automatically generated by genmatrix.py
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// Automatically generated by genmatrix.py
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// 8-bit Load Group
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// 8-bit Load Group
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if (pla[17] & ~pla[50]) begin
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if (pla[17] & ~pla[50]) begin
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if (M1 & T1) begin
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if (M1 & T1) begin
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_sw_2d=1;
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ctl_sw_2d=1;
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ctl_sw_1d=1;
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ctl_sw_1d=1;
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ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
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ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M2 & T1) begin fMRead=1;
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if (M2 & T1) begin fMRead=1;
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M2 & T2) begin fMRead=1;
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if (M2 & T2) begin fMRead=1;
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M2 & T3) begin fMRead=1; setM1=1; end
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if (M2 & T3) begin fMRead=1; setM1=1; end
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end
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end
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if (pla[61] & ~pla[58] & ~pla[59]) begin
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if (pla[61] & ~pla[58] & ~pla[59]) begin
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if (M1 & T1) begin
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if (M1 & T1) begin
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_sw_2u=1;
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ctl_sw_2u=1;
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ctl_alu_oe=1; /* Enable ALU onto the data bus */
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ctl_alu_oe=1; /* Enable ALU onto the data bus */
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ctl_alu_op1_oe=1; /* OP1 latch */ end
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ctl_alu_op1_oe=1; /* OP1 latch */ end
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if (M1 & T4) begin validPLA=1; setM1=1;
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if (M1 & T4) begin validPLA=1; setM1=1;
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ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
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ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
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ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
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ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
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ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
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ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
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ctl_alu_op1_sel_bus=1; /* Internal bus */ end
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ctl_alu_op1_sel_bus=1; /* Internal bus */ end
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end
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end
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if (use_ixiy & pla[58]) begin
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if (use_ixiy & pla[58]) begin
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if (M1 & T1) begin
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if (M1 & T1) begin
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_sw_2d=1;
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ctl_sw_2d=1;
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ctl_sw_1d=1;
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ctl_sw_1d=1;
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ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
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ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M2 & T1) begin fMRead=1;
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if (M2 & T1) begin fMRead=1;
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M2 & T2) begin fMRead=1;
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if (M2 & T2) begin fMRead=1;
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M2 & T3) begin fMRead=1; nextM=1; end
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if (M2 & T3) begin fMRead=1; nextM=1; end
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if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
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end
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end
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if (~use_ixiy & pla[58]) begin
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if (~use_ixiy & pla[58]) begin
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if (M1 & T1) begin
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if (M1 & T1) begin
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
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ctl_sw_2d=1;
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ctl_sw_2d=1;
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ctl_sw_1d=1;
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ctl_sw_1d=1;
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ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
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ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M2 & T1) begin fMRead=1;
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if (M2 & T1) begin fMRead=1;
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ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
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ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M2 & T2) begin fMRead=1; end
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if (M2 & T2) begin fMRead=1; end
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if (M2 & T3) begin fMRead=1; setM1=1; end
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if (M2 & T3) begin fMRead=1; setM1=1; end
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if (M4 & T1) begin fMRead=1;
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if (M4 & T1) begin fMRead=1;
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M4 & T2) begin fMRead=1; end
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if (M4 & T2) begin fMRead=1; end
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if (M4 & T3) begin fMRead=1; setM1=1; end
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if (M4 & T3) begin fMRead=1; setM1=1; end
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end
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end
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if (use_ixiy & pla[59]) begin
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if (use_ixiy & pla[59]) begin
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M2 & T1) begin fMRead=1;
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if (M2 & T1) begin fMRead=1;
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M2 & T2) begin fMRead=1;
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if (M2 & T2) begin fMRead=1;
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M2 & T3) begin fMRead=1; nextM=1; end
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if (M2 & T3) begin fMRead=1; nextM=1; end
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if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
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end
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end
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if (~use_ixiy & pla[59]) begin
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if (~use_ixiy & pla[59]) begin
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
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ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
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ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
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ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
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ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
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ctl_sw_1u=1;
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ctl_sw_1u=1;
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ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
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ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
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if (M2 & T1) begin fMWrite=1;
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if (M2 & T1) begin fMWrite=1;
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ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
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ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M2 & T2) begin fMWrite=1; end
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if (M2 & T2) begin fMWrite=1; end
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if (M2 & T3) begin fMWrite=1; setM1=1; end
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if (M2 & T3) begin fMWrite=1; setM1=1; end
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if (M4 & T1) begin fMWrite=1;
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if (M4 & T1) begin fMWrite=1;
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
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ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
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ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
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ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
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ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
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ctl_sw_1u=1;
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ctl_sw_1u=1;
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ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
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ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
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if (M4 & T2) begin fMWrite=1; end
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if (M4 & T2) begin fMWrite=1; end
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if (M4 & T3) begin fMWrite=1; setM1=1; end
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if (M4 & T3) begin fMWrite=1; setM1=1; end
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end
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end
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if (pla[40]) begin
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if (pla[40]) begin
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M2 & T1) begin fMRead=1;
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if (M2 & T1) begin fMRead=1;
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M2 & T2) begin fMRead=1;
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if (M2 & T2) begin fMRead=1;
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
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if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
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if (M3 & T1) begin fMRead=1;
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if (M3 & T1) begin fMRead=1;
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T2) begin fMRead=1;
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if (M3 & T2) begin fMRead=1;
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
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if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
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end
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end
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if (pla[50] & ~pla[40]) begin
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if (pla[50] & ~pla[40]) begin
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
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if (M2 & T1) begin fMRead=1;
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if (M2 & T1) begin fMRead=1;
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
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if (M2 & T2) begin fMRead=1;
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if (M2 & T2) begin fMRead=1;
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_inc_cy=~pc_inc_hold; /* Increment */
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
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if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end
|
if (M3 & T1) begin fMWrite=1;
|
if (M3 & T1) begin fMWrite=1;
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMWrite=1; end
|
if (M3 & T2) begin fMWrite=1; end
|
if (M3 & T3) begin fMWrite=1; setM1=1; end
|
if (M3 & T3) begin fMWrite=1; setM1=1; end
|
if (M4 & T1) begin fMWrite=1;
|
if (M4 & T1) begin fMWrite=1;
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T2) begin fMWrite=1; end
|
if (M4 & T2) begin fMWrite=1; end
|
if (M4 & T3) begin fMWrite=1; setM1=1; end
|
if (M4 & T3) begin fMWrite=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[8] & pla[13]) begin
|
if (pla[8] & pla[13]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M2 & T1) begin fMWrite=1;
|
if (M2 & T1) begin fMWrite=1;
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMWrite=1;
|
if (M2 & T2) begin fMWrite=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMWrite=1; setM1=1; end
|
if (M2 & T3) begin fMWrite=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[8] & ~pla[13]) begin
|
if (pla[8] & ~pla[13]) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; setM1=1; end
|
if (M2 & T3) begin fMRead=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[38] & pla[13]) begin
|
if (pla[38] & pla[13]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M4 & T1) begin fMWrite=1;
|
if (M4 & T1) begin fMWrite=1;
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M4 & T2) begin fMWrite=1;
|
if (M4 & T2) begin fMWrite=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin fMWrite=1; setM1=1; end
|
if (M4 & T3) begin fMWrite=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[38] & ~pla[13]) begin
|
if (pla[38] & ~pla[13]) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M4 & T1) begin fMRead=1;
|
if (M4 & T1) begin fMRead=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T2) begin fMRead=1;
|
if (M4 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin fMRead=1; setM1=1; end
|
if (M4 & T3) begin fMRead=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[83]) begin
|
if (pla[83]) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
|
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
|
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1;
|
if (M1 & T4) begin validPLA=1;
|
ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
|
ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
|
ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
|
ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
|
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
|
if (M1 & T5) begin setM1=1; end
|
if (M1 & T5) begin setM1=1; end
|
end
|
end
|
|
|
if (pla[57]) begin
|
if (pla[57]) begin
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1;
|
if (M1 & T4) begin validPLA=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
|
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_op1_oe=1; /* OP1 latch */ end
|
ctl_alu_op1_oe=1; /* OP1 latch */ end
|
if (M1 & T5) begin setM1=1; end
|
if (M1 & T5) begin setM1=1; end
|
end
|
end
|
|
|
// 16-bit Load Group
|
// 16-bit Load Group
|
if (pla[7]) begin
|
if (pla[7]) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; setM1=1; end
|
if (M3 & T3) begin fMRead=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[30] & pla[13]) begin
|
if (pla[30] & pla[13]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M4 & T1) begin fMWrite=1;
|
if (M4 & T1) begin fMWrite=1;
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M4 & T2) begin fMWrite=1;
|
if (M4 & T2) begin fMWrite=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M5 & T1) begin fMWrite=1;
|
if (M5 & T1) begin fMWrite=1;
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M5 & T2) begin fMWrite=1;
|
if (M5 & T2) begin fMWrite=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M5 & T3) begin fMWrite=1; setM1=1; end
|
if (M5 & T3) begin fMWrite=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[30] & ~pla[13]) begin
|
if (pla[30] & ~pla[13]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M4 & T1) begin fMRead=1;
|
if (M4 & T1) begin fMRead=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T2) begin fMRead=1;
|
if (M4 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M5 & T1) begin fMRead=1;
|
if (M5 & T1) begin fMRead=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M5 & T2) begin fMRead=1;
|
if (M5 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M5 & T3) begin fMRead=1; setM1=1;
|
if (M5 & T3) begin fMRead=1; setM1=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
end
|
end
|
|
|
if (pla[31] & pla[33]) begin
|
if (pla[31] & pla[33]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M4 & T1) begin fMWrite=1;
|
if (M4 & T1) begin fMWrite=1;
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
if (M4 & T2) begin fMWrite=1;
|
if (M4 & T2) begin fMWrite=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M5 & T1) begin fMWrite=1;
|
if (M5 & T1) begin fMWrite=1;
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
if (M5 & T2) begin fMWrite=1;
|
if (M5 & T2) begin fMWrite=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M5 & T3) begin fMWrite=1; setM1=1; end
|
if (M5 & T3) begin fMWrite=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[31] & ~pla[33]) begin
|
if (pla[31] & ~pla[33]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M4 & T1) begin fMRead=1;
|
if (M4 & T1) begin fMRead=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T2) begin fMRead=1;
|
if (M4 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
if (M5 & T1) begin fMRead=1;
|
if (M5 & T1) begin fMRead=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M5 & T2) begin fMRead=1;
|
if (M5 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M5 & T3) begin fMRead=1; setM1=1;
|
if (M5 & T3) begin fMRead=1; setM1=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
|
end
|
end
|
|
|
if (pla[5]) begin
|
if (pla[5]) begin
|
if (M1 & T4) begin validPLA=1;
|
if (M1 & T4) begin validPLA=1;
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M1 & T5) begin
|
if (M1 & T5) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M1 & T6) begin setM1=1; end
|
if (M1 & T6) begin setM1=1; end
|
end
|
end
|
|
|
if (pla[23] & pla[16]) begin
|
if (pla[23] & pla[16]) begin
|
if (M1 & T4) begin validPLA=1; end
|
if (M1 & T4) begin validPLA=1; end
|
if (M1 & T5) begin nextM=1; ctl_mWrite=1;
|
if (M1 & T5) begin nextM=1; ctl_mWrite=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T1) begin fMWrite=1;
|
if (M2 & T1) begin fMWrite=1;
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M2 & T2) begin fMWrite=1;
|
if (M2 & T2) begin fMWrite=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T1) begin fMWrite=1;
|
if (M3 & T1) begin fMWrite=1;
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M3 & T2) begin fMWrite=1;
|
if (M3 & T2) begin fMWrite=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMWrite=1; setM1=1; end
|
if (M3 & T3) begin fMWrite=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[23] & ~pla[16]) begin
|
if (pla[23] & ~pla[16]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1; setM1=1;
|
if (M3 & T3) begin fMRead=1; setM1=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
end
|
end
|
|
|
// Exchange, Block Transfer and Search Groups
|
// Exchange, Block Transfer and Search Groups
|
if (pla[2]) begin
|
if (pla[2]) begin
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_ex_de_hl=1; /* EX DE,HL */ end
|
ctl_reg_ex_de_hl=1; /* EX DE,HL */ end
|
if (M1 & T4) begin validPLA=1; setM1=1; end
|
if (M1 & T4) begin validPLA=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[39]) begin
|
if (pla[39]) begin
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_ex_af=1; /* EX AF,AF' */ end
|
ctl_reg_ex_af=1; /* EX AF,AF' */ end
|
if (M1 & T4) begin validPLA=1; setM1=1; end
|
if (M1 & T4) begin validPLA=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[1]) begin
|
if (pla[1]) begin
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_exx=1; /* EXX */ end
|
ctl_reg_exx=1; /* EXX */ end
|
if (M1 & T4) begin validPLA=1; setM1=1; end
|
if (M1 & T4) begin validPLA=1; setM1=1; end
|
end
|
end
|
|
|
if (pla[10]) begin
|
if (pla[10]) begin
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T1) begin fMRead=1;
|
if (M3 & T1) begin fMRead=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T2) begin fMRead=1;
|
if (M3 & T2) begin fMRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMRead=1;
|
if (M3 & T3) begin fMRead=1;
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
|
if (M3 & T4) begin nextM=1; ctl_mWrite=1;
|
if (M3 & T4) begin nextM=1; ctl_mWrite=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T1) begin fMWrite=1;
|
if (M4 & T1) begin fMWrite=1;
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M4 & T2) begin fMWrite=1;
|
if (M4 & T2) begin fMWrite=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M5 & T1) begin fMWrite=1;
|
if (M5 & T1) begin fMWrite=1;
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_apin_mux=1; /* Apin sourced from incrementer */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */
|
ctl_sw_1u=1;
|
ctl_sw_1u=1;
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
|
if (M5 & T2) begin fMWrite=1;
|
if (M5 & T2) begin fMWrite=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M5 & T3) begin fMWrite=1;
|
if (M5 & T3) begin fMWrite=1;
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M5 & T4) begin
|
if (M5 & T4) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M5 & T5) begin setM1=1; end
|
if (M5 & T5) begin setM1=1; end
|
end
|
end
|
|
|
if (pla[0]) begin
|
if (pla[0]) begin
|
begin nonRep=1; /* Non-repeating block instruction */ end
|
begin nonRep=1; /* Non-repeating block instruction */ end
|
end
|
end
|
|
|
if (pla[12]) begin
|
if (pla[12]) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
|
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
|
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
|
ctl_flags_use_cf2=1; end
|
ctl_flags_use_cf2=1; end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_cf2_we=1; end
|
ctl_flags_cf2_we=1; end
|
if (M3 & T1) begin fMWrite=1;
|
if (M3 & T1) begin fMWrite=1;
|
ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_use_cf2=1; end
|
ctl_flags_use_cf2=1; end
|
if (M3 & T2) begin fMWrite=1;
|
if (M3 & T2) begin fMWrite=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M3 & T3) begin fMWrite=1;
|
if (M3 & T3) begin fMWrite=1;
|
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T4) begin
|
if (M3 & T4) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
|
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
|
if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en; end
|
if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en; end
|
if (M4 & T1) begin
|
if (M4 & T1) begin
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T2) begin
|
if (M4 & T2) begin
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin
|
if (M4 & T3) begin
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T4) begin
|
if (M4 & T4) begin
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T5) begin setM1=1; end
|
if (M4 & T5) begin setM1=1; end
|
end
|
end
|
|
|
if (pla[11]) begin
|
if (pla[11]) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_op1_sel_zero=1; /* Zero */
|
ctl_alu_op1_sel_zero=1; /* Zero */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
|
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
|
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
|
ctl_flags_use_cf2=1; end
|
ctl_flags_use_cf2=1; end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_flags_hf_cpl=flags_nf; end
|
ctl_flags_hf_cpl=flags_nf; end
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1;
|
if (M2 & T3) begin fMRead=1; nextM=1;
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_cf2_we=1; end
|
ctl_flags_cf2_we=1; end
|
if (M3 & T1) begin
|
if (M3 & T1) begin
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_use_cf2=1; end
|
ctl_flags_use_cf2=1; end
|
if (M3 & T3) begin
|
if (M3 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M3 & T4) begin
|
if (M3 & T4) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
|
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
|
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
|
if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en | flags_zf; end
|
if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en | flags_zf; end
|
if (M4 & T1) begin
|
if (M4 & T1) begin
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T2) begin
|
if (M4 & T2) begin
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T3) begin
|
if (M4 & T3) begin
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M4 & T4) begin
|
if (M4 & T4) begin
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T5) begin setM1=1; end
|
if (M4 & T5) begin setM1=1; end
|
end
|
end
|
|
|
// 8-bit Arithmetic and Logic Group
|
// 8-bit Arithmetic and Logic Group
|
if (pla[65] & ~pla[52]) begin
|
if (pla[65] & ~pla[52]) begin
|
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
|
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
|
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1; setM1=1;
|
if (M1 & T4) begin validPLA=1; setM1=1;
|
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
|
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
|
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
|
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1; end
|
ctl_flags_hf_we=1; end
|
end
|
end
|
|
|
if (pla[64]) begin
|
if (pla[64]) begin
|
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
|
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
|
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;
|
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
|
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
|
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
|
ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1; end
|
ctl_flags_hf_we=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; setM1=1;
|
if (M2 & T3) begin fMRead=1; setM1=1;
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1; end
|
ctl_flags_hf_we=1; end
|
end
|
end
|
|
|
if (use_ixiy & pla[52]) begin
|
if (use_ixiy & pla[52]) begin
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; nextM=1; end
|
if (M2 & T3) begin fMRead=1; nextM=1; end
|
if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
|
if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
|
end
|
end
|
|
|
if (~use_ixiy & pla[52]) begin
|
if (~use_ixiy & pla[52]) begin
|
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
|
if (M1 & T1) begin /* Which register to be written is decided elsewhere */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
|
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
|
if (M1 & T3) begin
|
if (M1 & T3) begin
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_pf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
|
if (M2 & T1) begin fMRead=1;
|
if (M2 & T1) begin fMRead=1;
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
|
if (M2 & T2) begin fMRead=1;
|
if (M2 & T2) begin fMRead=1;
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_inc_cy=~pc_inc_hold; /* Increment */
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M2 & T3) begin fMRead=1; setM1=1;
|
if (M2 & T3) begin fMRead=1; setM1=1;
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1; end
|
ctl_flags_hf_we=1; end
|
if (M4 & T1) begin fMRead=1;
|
if (M4 & T1) begin fMRead=1;
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
|
if (M4 & T2) begin fMRead=1;
|
if (M4 & T2) begin fMRead=1;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_flags_bus=1; /* Load FLAGT from the data bus */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_alu_op1_sel_bus=1; /* Internal bus */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_hf_we=1;
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
|
ctl_flags_cf_we=1; end
|
ctl_flags_cf_we=1; end
|
if (M4 & T3) begin fMRead=1; setM1=1;
|
if (M4 & T3) begin fMRead=1; setM1=1;
|
ctl_sw_2d=1;
|
ctl_sw_2d=1;
|
ctl_sw_1d=1;
|
ctl_sw_1d=1;
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op2_sel_bus=1; /* Internal bus */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_hf_we=1; end
|
ctl_flags_hf_we=1; end
|
end
|
end
|
|
|
if (pla[66] & ~pla[53]) begin
|
if (pla[66] & ~pla[53]) begin
|
if (M1 & T1) begin
|
if (M1 & T1) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_sw_2u=1;
|
ctl_sw_2u=1;
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_flags_alu=1; /* Load FLAGT from the ALU */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_oe=1; /* Enable ALU onto the data bus */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_res_oe=1; /* Result latch */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
|
ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_flags_sz_we=1;
|
ctl_flags_sz_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_xy_we=1;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
|
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
|
ctl_flags_use_cf2=1; end
|
ctl_flags_use_cf2=1; end
|
if (M1 & T2) begin
|
if (M1 & T2) begin
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
|
ctl_flags_hf_cpl=flags_nf; end
|