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[/] [a-z80/] [trunk/] [cpu/] [control/] [memory_ifc.v] - Diff between revs 13 and 16

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Rev 13 Rev 16
Line 12... Line 12... 
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// applicable agreement for further details.
 
 
 
 
 
// PROGRAM              "Quartus II 64-Bit"
 
// PROGRAM              "Quartus II 64-Bit"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// CREATED              "Sun Dec 04 01:04:33 2016"
 
// CREATED              "Sat Dec 10 09:02:54 2016"
 
 
 
 
 
module memory_ifc(
 
module memory_ifc(
 
        clk,
 
        clk,
 
        nM1_int,
 
        nM1_int,
 
        ctl_mRead,
 
        ctl_mRead,
Line 27... Line 27... 
        fIOWrite,
 
        fIOWrite,
 
        setM1,
 
        setM1,
 
        ctl_iorw,
 
        ctl_iorw,
 
        timings_en,
 
        timings_en,
 
        iorq_Tw,
 
        iorq_Tw,
 
        hold_clk_wait,
 
        nhold_clk_wait,
 
        nM1_out,
 
        nM1_out,
 
        nRFSH_out,
 
        nRFSH_out,
 
        nMREQ_out,
 
        nMREQ_out,
 
        nRD_out,
 
        nRD_out,
 
        nWR_out,
 
        nWR_out,
Line 51... Line 51... 
input wire      fIOWrite;
 
input wire      fIOWrite;
 
input wire      setM1;
 
input wire      setM1;
 
input wire      ctl_iorw;
 
input wire      ctl_iorw;
 
input wire      timings_en;
 
input wire      timings_en;
 
input wire      iorq_Tw;
 
input wire      iorq_Tw;
 
input wire      hold_clk_wait;
 
input wire      nhold_clk_wait;
 
output wire     nM1_out;
 
output wire     nM1_out;
 
output wire     nRFSH_out;
 
output wire     nRFSH_out;
 
output wire     nMREQ_out;
 
output wire     nMREQ_out;
 
output wire     nRD_out;
 
output wire     nRD_out;
 
output wire     nWR_out;
 
output wire     nWR_out;
Line 80... Line 80... 
reg     wait_mrd;
 
reg     wait_mrd;
 
reg     wait_mwr;
 
reg     wait_mwr;
 
wire    SYNTHESIZED_WIRE_0;
 
wire    SYNTHESIZED_WIRE_0;
 
reg     DFFE_m1_ff3;
 
reg     DFFE_m1_ff3;
 
wire    SYNTHESIZED_WIRE_1;
 
wire    SYNTHESIZED_WIRE_1;
 
reg     SYNTHESIZED_WIRE_16;
 
reg     SYNTHESIZED_WIRE_15;
 
reg     DFFE_iorq_ff4;
 
reg     DFFE_iorq_ff4;
 
reg     SYNTHESIZED_WIRE_17;
 
reg     SYNTHESIZED_WIRE_16;
 
reg     DFFE_mrd_ff3;
 
reg     DFFE_mrd_ff3;
 
reg     DFFE_intr_ff3;
 
reg     DFFE_intr_ff3;
 
wire    SYNTHESIZED_WIRE_2;
 
wire    SYNTHESIZED_WIRE_2;
 
reg     SYNTHESIZED_WIRE_18;
 
reg     SYNTHESIZED_WIRE_17;
 
wire    SYNTHESIZED_WIRE_3;
 
wire    SYNTHESIZED_WIRE_3;
 
reg     SYNTHESIZED_WIRE_19;
 
reg     SYNTHESIZED_WIRE_18;
 
wire    SYNTHESIZED_WIRE_20;
 
wire    SYNTHESIZED_WIRE_19;
 
wire    SYNTHESIZED_WIRE_5;
 
 
 
reg     DFFE_iorq_ff1;
 
reg     DFFE_iorq_ff1;
 
reg     DFFE_m1_ff1;
 
reg     DFFE_m1_ff1;
 
reg     DFFE_mrd_ff1;
 
reg     DFFE_mrd_ff1;
 
reg     DFFE_mwr_ff1;
 
reg     DFFE_mwr_ff1;
 
reg     DFFE_mreq_ff2;
 
reg     DFFE_mreq_ff2;
Line 108... Line 107... 
 
 
 
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
 
 
 
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
 
 
 
 
assign  iorq = SYNTHESIZED_WIRE_16 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_17;
 
assign  iorq = SYNTHESIZED_WIRE_15 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_16;
 
 
 
 
 
assign  ioWrite = iorq & fIOWrite;
 
assign  ioWrite = iorq & fIOWrite;
 
 
 
 
 
assign  latch_wait = wait_mrd | wait_iorq | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
assign  latch_wait = wait_mrd | wait_iorq | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
 
 
 
Line 126... Line 125... 
 
 
 
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
 
 
 
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
 
 
 
 
assign  SYNTHESIZED_WIRE_5 =  ~hold_clk_wait;
 
 
 
 
 
 
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorq;
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorq;
 
 
 
 
 
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_18;
 
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_17;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_19);
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_18);
 
 
 
 
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_18);
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_17);
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_iorq <= 0;
 
        wait_iorq <= 0;
 
        end
 
        end
Line 157... Line 154... 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_intr_ff3 <= 0;
 
        DFFE_intr_ff3 <= 0;
 
        end
 
        end
 
else
 
else
 
if (SYNTHESIZED_WIRE_5)
 
if (nhold_clk_wait)
 
        begin
 
        begin
 
        DFFE_intr_ff3 <= wait_iorq;
 
        DFFE_intr_ff3 <= wait_iorq;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 182... Line 179... 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_17 <= 0;
 
        SYNTHESIZED_WIRE_16 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_17 <= DFFE_iorq_ff1;
 
        SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_16 <= 0;
 
        SYNTHESIZED_WIRE_15 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_17;
 
        SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_iorq_ff4 <= 0;
 
        DFFE_iorq_ff4 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_16;
 
        DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_18 <= 0;
 
        SYNTHESIZED_WIRE_17 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_18 <= nM1_int;
 
        SYNTHESIZED_WIRE_17 <= nM1_int;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_m1_ff1 <= 1;
 
        DFFE_m1_ff1 <= 1;
 
        end
 
        end
Line 248... Line 245... 
        DFFE_m1_ff1 <= setM1;
 
        DFFE_m1_ff1 <= setM1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
 
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
 
        end
 
        end
Line 290... Line 287... 
        DFFE_mrd_ff1 <= ctl_mRead;
 
        DFFE_mrd_ff1 <= ctl_mRead;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_mrd <= 0;
 
        wait_mrd <= 0;
 
        end
 
        end
Line 304... Line 301... 
        wait_mrd <= DFFE_mrd_ff1;
 
        wait_mrd <= DFFE_mrd_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_mrd_ff3 <= 0;
 
        DFFE_mrd_ff3 <= 0;
 
        end
 
        end
Line 318... Line 315... 
        DFFE_mrd_ff3 <= wait_mrd;
 
        DFFE_mrd_ff3 <= wait_mrd;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_19 <= 0;
 
        SYNTHESIZED_WIRE_18 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_19 <= SYNTHESIZED_WIRE_18;
 
        SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_17;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_mreq_ff2 <= 0;
 
        DFFE_mreq_ff2 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_19;
 
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_18;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 360... Line 357... 
        DFFE_mwr_ff1 <= ctl_mWrite;
 
        DFFE_mwr_ff1 <= ctl_mWrite;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_mwr <= 0;
 
        wait_mwr <= 0;
 
        end
 
        end
Line 374... Line 371... 
        wait_mwr <= DFFE_mwr_ff1;
 
        wait_mwr <= DFFE_mwr_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        mwr_wr <= 0;
 
        mwr_wr <= 0;
 
        end
 
        end
Line 387... Line 384... 
        begin
 
        begin
 
        mwr_wr <= wait_mwr;
 
        mwr_wr <= wait_mwr;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
assign  SYNTHESIZED_WIRE_20 =  ~clk;
 
assign  SYNTHESIZED_WIRE_19 =  ~clk;
 
 
 
 
 
assign  nq2 =  ~q2;
 
assign  nq2 =  ~q2;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
 
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
 
 
 
 
Line 405... Line 402... 
        q1 <= 0;
 
        q1 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        q1 <= SYNTHESIZED_WIRE_18;
 
        q1 <= SYNTHESIZED_WIRE_17;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)

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