OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [control/] [memory_ifc.v] - Diff between revs 16 and 18

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 16 Rev 18
Line 12... Line 12... 
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// applicable agreement for further details.
 
 
 
 
 
// PROGRAM              "Quartus II 64-Bit"
 
// PROGRAM              "Quartus II 64-Bit"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// CREATED              "Sat Dec 10 09:02:54 2016"
 
// CREATED              "Mon Dec 04 20:31:24 2017"
 
 
 
 
 
module memory_ifc(
 
module memory_ifc(
 
        clk,
 
        clk,
 
        nM1_int,
 
        nM1_int,
 
        ctl_mRead,
 
        ctl_mRead,
Line 73... Line 73... 
reg     mwr_wr;
 
reg     mwr_wr;
 
wire    nMEMRQ_int;
 
wire    nMEMRQ_int;
 
wire    nq2;
 
wire    nq2;
 
reg     q1;
 
reg     q1;
 
reg     q2;
 
reg     q2;
 
 
 
wire    wait_io;
 
reg     wait_iorq;
 
reg     wait_iorq;
 
 
 
reg     wait_iorqinta;
 
reg     wait_m_ALTERA_SYNTHESIZED1;
 
reg     wait_m_ALTERA_SYNTHESIZED1;
 
reg     wait_mrd;
 
reg     wait_mrd;
 
reg     wait_mwr;
 
reg     wait_mwr;
 
wire    SYNTHESIZED_WIRE_0;
 
wire    SYNTHESIZED_WIRE_0;
 
reg     DFFE_m1_ff3;
 
reg     DFFE_m1_ff3;
 
wire    SYNTHESIZED_WIRE_1;
 
wire    SYNTHESIZED_WIRE_1;
 
reg     SYNTHESIZED_WIRE_15;
 
 
 
reg     DFFE_iorq_ff4;
 
reg     DFFE_iorq_ff4;
 
reg     SYNTHESIZED_WIRE_16;
 
reg     SYNTHESIZED_WIRE_15;
 
reg     DFFE_mrd_ff3;
 
reg     DFFE_mrd_ff3;
 
reg     DFFE_intr_ff3;
 
reg     DFFE_intr_ff3;
 
wire    SYNTHESIZED_WIRE_2;
 
wire    SYNTHESIZED_WIRE_2;
 
reg     SYNTHESIZED_WIRE_17;
 
reg     SYNTHESIZED_WIRE_16;
 
wire    SYNTHESIZED_WIRE_3;
 
wire    SYNTHESIZED_WIRE_3;
 
reg     SYNTHESIZED_WIRE_18;
 
reg     SYNTHESIZED_WIRE_17;
 
wire    SYNTHESIZED_WIRE_19;
 
wire    SYNTHESIZED_WIRE_18;
 
reg     DFFE_iorq_ff1;
 
reg     DFFE_iorq_ff1;
 
reg     DFFE_m1_ff1;
 
reg     DFFE_m1_ff1;
 
reg     DFFE_mrd_ff1;
 
reg     DFFE_mrd_ff1;
 
reg     DFFE_mwr_ff1;
 
reg     DFFE_mwr_ff1;
 
reg     DFFE_mreq_ff2;
 
reg     DFFE_mreq_ff2;
Line 107... Line 108... 
 
 
 
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
 
 
 
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
 
 
 
 
assign  iorq = SYNTHESIZED_WIRE_15 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_16;
 
assign  iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;
 
 
 
 
 
assign  ioWrite = iorq & fIOWrite;
 
assign  ioWrite = iorq & fIOWrite;
 
 
 
 
 
assign  latch_wait = wait_mrd | wait_iorq | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
assign  latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
 
 
 
 
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
 
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
 
 
 
 
 
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
 
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
 
 
 
 
Line 125... Line 126... 
 
 
 
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
 
 
 
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
 
 
 
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorq;
 
assign  wait_io = wait_iorqinta | wait_iorq;
 
 
 
 
 
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_17;
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorqinta;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_18);
 
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;
 
 
 
 
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_17);
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);
 
 
 
 
 
 
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_iorq <= 0;
 
        wait_iorqinta <= 0;
 
        end
 
        end
 
else
 
else
 
 
 
if (timings_en)
 
        begin
 
        begin
 
        wait_iorq <= iorq_Tw;
 
        wait_iorqinta <= iorq_Tw;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 156... Line 160... 
        DFFE_intr_ff3 <= 0;
 
        DFFE_intr_ff3 <= 0;
 
        end
 
        end
 
else
 
else
 
if (nhold_clk_wait)
 
if (nhold_clk_wait)
 
        begin
 
        begin
 
        DFFE_intr_ff3 <= wait_iorq;
 
        DFFE_intr_ff3 <= wait_iorqinta;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 179... Line 183... 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_16 <= 0;
 
        SYNTHESIZED_WIRE_15 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1;
 
        SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_15 <= 0;
 
        wait_iorq <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16;
 
        wait_iorq <= SYNTHESIZED_WIRE_15;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_iorq_ff4 <= 0;
 
        DFFE_iorq_ff4 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15;
 
        DFFE_iorq_ff4 <= wait_iorq;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_17 <= 0;
 
        SYNTHESIZED_WIRE_16 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_17 <= nM1_int;
 
        SYNTHESIZED_WIRE_16 <= nM1_int;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_m1_ff1 <= 1;
 
        DFFE_m1_ff1 <= 1;
 
        end
 
        end
Line 245... Line 249... 
        DFFE_m1_ff1 <= setM1;
 
        DFFE_m1_ff1 <= setM1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
 
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
 
        end
 
        end
Line 287... Line 291... 
        DFFE_mrd_ff1 <= ctl_mRead;
 
        DFFE_mrd_ff1 <= ctl_mRead;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_mrd <= 0;
 
        wait_mrd <= 0;
 
        end
 
        end
Line 301... Line 305... 
        wait_mrd <= DFFE_mrd_ff1;
 
        wait_mrd <= DFFE_mrd_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_mrd_ff3 <= 0;
 
        DFFE_mrd_ff3 <= 0;
 
        end
 
        end
Line 315... Line 319... 
        DFFE_mrd_ff3 <= wait_mrd;
 
        DFFE_mrd_ff3 <= wait_mrd;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_18 <= 0;
 
        SYNTHESIZED_WIRE_17 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_17;
 
        SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_mreq_ff2 <= 0;
 
        DFFE_mreq_ff2 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_18;
 
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 357... Line 361... 
        DFFE_mwr_ff1 <= ctl_mWrite;
 
        DFFE_mwr_ff1 <= ctl_mWrite;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_mwr <= 0;
 
        wait_mwr <= 0;
 
        end
 
        end
Line 371... Line 375... 
        wait_mwr <= DFFE_mwr_ff1;
 
        wait_mwr <= DFFE_mwr_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        mwr_wr <= 0;
 
        mwr_wr <= 0;
 
        end
 
        end
Line 384... Line 388... 
        begin
 
        begin
 
        mwr_wr <= wait_mwr;
 
        mwr_wr <= wait_mwr;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
assign  SYNTHESIZED_WIRE_19 =  ~clk;
 
assign  SYNTHESIZED_WIRE_18 =  ~clk;
 
 
 
 
 
assign  nq2 =  ~q2;
 
assign  nq2 =  ~q2;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
 
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
 
 
 
 
Line 402... Line 406... 
        q1 <= 0;
 
        q1 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        q1 <= SYNTHESIZED_WIRE_17;
 
        q1 <= SYNTHESIZED_WIRE_16;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.