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[/] [a-z80/] [trunk/] [cpu/] [control/] [test_reset.sv] - Diff between revs 13 and 16
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Rev 13 |
Rev 16 |
Line 21... |
Line 21... |
logic reset_in = 0;
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logic reset_in = 0;
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logic M1 = 0;
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logic M1 = 0;
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logic T2 = 0;
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logic T2 = 0;
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wire clrpc; // Load 0 to PC
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wire clrpc; // Load 0 to PC
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wire hold_clk_wait; // Hold clrpc
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wire nhold_clk_wait; // Hold clrpc
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wire nreset; // Internal inverted reset signal
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wire nreset; // Internal inverted reset signal
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assign hold_clk_wait = 0; // Will not test this case
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assign nhold_clk_wait = 1; // Will not test this case
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// ----------------- TEST -------------------
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// ----------------- TEST -------------------
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initial begin
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initial begin
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// Test normal reset sequence - 3 clocks long
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// Test normal reset sequence - 3 clocks long
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`T reset_in = 1;
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`T reset_in = 1;
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