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[/] [a-z80/] [trunk/] [cpu/] [control/] [test_reset.sv] - Diff between revs 3 and 8

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//==============================================================
//==============================================================
// Test reset circuit
// Test reset circuit
//==============================================================
//==============================================================
`timescale 100 ns/ 100 ns
`timescale 100 ns/ 100 ns
module test_reset;
module test_reset;
// ----------------- CLOCKS AND RESET -----------------
// ----------------- CLOCKS AND RESET -----------------
`define T #2
`define T #2
bit clk = 1;
bit clk = 1;
initial repeat (30) #1 clk = ~clk;
initial repeat (40) #1 clk = ~clk;
 
 
// Specific to FPGA, some modules in the schematic need to be pre-initialized
// Specific to FPGA, some modules in the schematic need to be pre-initialized
reg fpga_reset = 1;
reg fpga_reset = 1;
always_latch
always_latch
    if (clk) fpga_reset <= 0;
    if (clk) fpga_reset <= 0;
//----------------------------------------------------------
//----------------------------------------------------------
// Input reset from the pin; state from the sequencer
// Input reset from the pin; state from the sequencer
//----------------------------------------------------------
//----------------------------------------------------------
logic reset_in = 0;
logic reset_in = 0;
logic M1 = 0;
logic M1 = 0;
logic T2 = 0;
logic T2 = 0;
wire clrpc;            // Load 0 to PC
wire clrpc;            // Load 0 to PC
wire nreset;           // Internal inverted reset signal
wire nreset;           // Internal inverted reset signal
// ----------------- TEST -------------------
// ----------------- TEST -------------------
initial begin
initial begin
    // Test normal reset sequence - 3 clocks long
    // Test normal reset sequence - 3 clocks long
    `T reset_in = 1;
    `T reset_in = 1;
    `T `T `T reset_in = 0;
    `T `T `T reset_in = 0;
    `T assert(nreset==0 && clrpc==0);
    `T assert(nreset==0);
 
    // Out of the reset for several more cycles
 
    // Check that the clrpc is set for the next 2 1/2 cycles (see waveform)
 
    `T assert(nreset==1 && clrpc==1);
 
    `T assert(nreset==1 && clrpc==1);
 
    `T assert(nreset==1 && clrpc==0);
 
    `T assert(nreset==1 && clrpc==0);
 
    `T assert(nreset==1 && clrpc==0);
 
 
    // Test special reset sequence: a reset pin is briefly
    // Test special reset sequence: a reset pin is briefly
    // asserted at M1/T1 and CLRPC should hold until the next
    // asserted at M1/T1 and CLRPC should hold until the next
    // M1/T2
    // M1/T2
    `T reset_in = 1; M1=1;
    `T reset_in = 1; M1=1;
    `T reset_in = 0; M1=1; T2=1;
    `T reset_in = 0; M1=1; T2=1;
    `T               M1=1; T2=0;
    `T               M1=1; T2=0;
    `T `T
    `T `T
    `T assert(nreset==1 && clrpc==1);
    `T assert(nreset==1 && clrpc==1);
    `T               M1=1; T2=1;
    `T               M1=1; T2=1;
    `T               M1=1; T2=0;
    `T               M1=1; T2=0;
    `T assert(nreset==1 && clrpc==0);
    `T assert(nreset==1 && clrpc==0);
    `T $display("End of test");
    `T $display("End of test");
end
end
//--------------------------------------------------------------
//--------------------------------------------------------------
// Instantiate DUT
// Instantiate DUT
//--------------------------------------------------------------
//--------------------------------------------------------------
resets reset_block ( .* );
resets reset_block ( .* );
endmodule
endmodule
 
 

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