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//=========================================================================================
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//=========================================================================================
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// This file contains substitute strings for macros used in the Excel timing table and
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// This file contains substitute strings for macro expansions. Macros are defined in an
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// is read and processed by genmatrix.py script to generate exec_matrix.vh include file.
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// Excel timing spreadsheet 'Timings.xlsm' and exported to a .csv file which is then read
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// and processed by genmatrix.py script to generate exec_matrix.vh include file.
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//
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//
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// Format of the file:
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// Macro format:
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//
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//
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// * Each key is prefixed by ':' and corresponds to a spreadsheet column name.
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// * Each key is prefixed by ':' and corresponds to a spreadsheet *column* name.
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// * A column (key) contains a number of macros, each starting at its own line.
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// * A key may contain several different macros, one per line.
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// * A macro may span multiple lines, in which case use the '\' character after the name to
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// * A macro may span multiple lines; use the '\' character to continue on the next line.
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// continue on the next line.
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// * Multi-line macros end when a line does not start with a space character.
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// * Multiline macros end when a line does not _start_ with a space character.
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// //-style comments are wrapped within /* ... */ if they don't start a line.
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// //-style comments are wrapped within /* ... */ if they don't start a line.
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//=========================================================================================
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//=========================================================================================
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:Function
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// CPU machine state
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:Function
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//Fetch is M1
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//Fetch is M1
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fMFetch
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fMFetch
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fMRead fMRead=1;
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fMRead fMRead=1;
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fMWrite fMWrite=1;
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fMWrite fMWrite=1;
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fIORead fIORead=1;
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fIORead fIORead=1;
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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// Basic timing control
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// Basic timing control
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:valid
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:valid
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1 validPLA=1;
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Y validPLA=1;
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:nextM
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:nextM
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1 nextM=1;
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Y nextM=1;
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mr nextM=1; ctl_mRead=1;
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mr nextM=1; ctl_mRead=1;
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mw nextM=1; ctl_mWrite=1;
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mw nextM=1; ctl_mWrite=1;
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ior nextM=1; ctl_iorw=1;
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ior nextM=1; ctl_iorw=1;
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iow nextM=1; ctl_iorw=1;
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iow nextM=1; ctl_iorw=1;
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CC nextM=!flags_cond_true;
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CC nextM=~flags_cond_true;
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INT nextM=1; ctl_mRead=in_intr & im2; // RST38 interrupt extension
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INT nextM=1; ctl_mRead=in_intr & im2; // RST38 interrupt extension
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:setM1
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:setM1
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1 setM1=1;
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Y setM1=1;
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SS setM1=!flags_cond_true;
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SS setM1=~flags_cond_true;
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CC setM1=!flags_cond_true;
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CC setM1=~flags_cond_true;
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ZF setM1=flags_zf; // Used in DJNZ
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ZF setM1=flags_zf; // Used in DJNZ
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BR setM1=nonRep | !repeat_en;
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BR setM1=nonRep | ~repeat_en;
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BRZ setM1=nonRep | !repeat_en | flags_zf;
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BRZ setM1=nonRep | ~repeat_en | flags_zf;
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BZ setM1=nonRep | flags_zf;
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BZ setM1=nonRep | flags_zf;
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INT setM1=!(in_intr & im2); // RST38 interrupt extension
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INT setM1=~(in_intr & im2); // RST38 interrupt extension
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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// Register file, address (downstream) endpoint
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// Register file, address (downstream) endpoint
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:A:reg rd
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:A:reg rd
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IR ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit IR
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IR ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit IR
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I* ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; // Select 8-bit I register
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I* ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; // Select 8-bit I register
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PC ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit PC
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PC ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit PC
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// Conditional assertions of WZ, HL instead of PC
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// Conditional assertions of WZ, HL instead of PC
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WZ? \
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WZ? ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true;
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if (flags_cond_true) begin // If cc is true, use WZ instead of PC (for jumps)
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// Alternate format:
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ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;
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// if (flags_cond_true) begin // If cc is true, use WZ instead of PC (for jumps)
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end
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// ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;
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// end
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:A:reg wr
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:A:reg wr
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// General purpose registers
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// General purpose registers
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r16 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit general purpose register, enable SW4 upstream
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r16 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit general purpose register, enable SW4 upstream
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BC ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream
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BC ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream
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SP ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; // Write 16-bit SP, enable SW4 upstream
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SP ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; // Write 16-bit SP, enable SW4 upstream
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// System registers
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// System registers
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WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit WZ, enable SW4 upstream
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WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit WZ, enable SW4 upstream
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IR ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Write 16-bit IR
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IR ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Write 16-bit IR
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// PC will not be incremented if we are in HALT, INTR or NMI state
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// PC will not be incremented if we are in HALT, INTR or NMI state
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PC ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); // Write 16-bit PC and control incrementer
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PC ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); // Write 16-bit PC and control incrementer
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> ctl_sw_4u=1;
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> ctl_sw_4u=1;
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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// Controls the address latch incrementer, the address latch and the address pin mux
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// Controls the address latch incrementer, the address latch and the address pin mux
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:inc/dec
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:inc/dec
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+ ctl_inc_cy=pc_inc; // Increment
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+ ctl_inc_cy=~pc_inc_hold; // Increment
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- ctl_inc_cy=pc_inc; ctl_inc_dec=1; // Decrement
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- ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; // Decrement
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op3 ctl_inc_cy=pc_inc; ctl_inc_dec=op3; // Decrement if op3 is set; increment otherwise
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op3 ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; // Decrement if op3 is set; increment otherwise
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:A:latch
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:A:latch
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W ctl_al_we=1; // Write a value from the register bus to the address latch
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W ctl_al_we=1; // Write a value from the register bus to the address latch
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R ctl_bus_inc_oe=1; // Output enable incrementer to the register bus
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R ctl_bus_inc_oe=1; // Output enable incrementer to the register bus
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P ctl_apin_mux=1; // Apin sourced from incrementer
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P ctl_apin_mux=1; // Apin sourced from incrementer
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Line 107... |
A ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
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A ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
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AF ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
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AF ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
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B ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
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B ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
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H ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
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H ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
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L ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
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L ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
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r8 \ // r8 addressing does not allow reading F register (A and F are also indexed as swapped) (ex. in OUT (c),r)
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r8 ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};// Read 8-bit GP register selected by op[2:0]
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if (op4 & op5 & !op3) ctl_bus_zero_oe=1; // Trying to read flags? Put 0 on the bus instead.
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r8' \ // r8 addressing does not allow reading F register (indices of A and F are also swapped) (ex. in OUT (c),r)
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else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end // Read 8-bit GP register
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if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end // Trying to read flags? Put 0 on the bus instead.
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r8' ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};// Read 8-bit GP register selected by op[2:0]
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if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end // Read 8-bit GP register
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rh ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Read 8-bit GP register high byte
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rh ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Read 8-bit GP register high byte
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rl ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Read 8-bit GP register low byte
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rl ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Read 8-bit GP register low byte
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//----- System registers -----
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//----- System registers -----
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WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;
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WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;
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Z ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; // Selecting strictly Z
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Z ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; // Selecting strictly Z
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I/R ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4u=1; // Read either I or R based on op3 (0 or 1)
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I/R ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; // Read either I or R based on op3 (0 or 1)
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PCh ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
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PCh ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
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PCl ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
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PCl ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
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:D:reg wr
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:D:reg wr
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? // Which register to be written is decided elsewhere
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? // Which register to be written is decided elsewhere
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//----- General purpose registers -----
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//----- General purpose registers -----
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A ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
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A ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
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F ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
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F ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
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B ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
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B ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
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r8 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; // Write 8-bit GP register
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r8 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; // Write 8-bit GP register
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r8' ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; // Write 8-bit GP register selected by op[2:0]
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r8' ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; // Write 8-bit GP register selected by op[2:0]
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rh ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Write 8-bit GP register high byte
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rh ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Write 8-bit GP register high byte
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rl ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Write 8-bit GP register low byte
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rl ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Write 8-bit GP register low byte
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//----- System registers -----
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//----- System registers -----
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I/R ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4d=1; // Write either I or R based on op3 (0 or 1)
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I/R ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; // Write either I or R based on op3 (0 or 1)
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WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;
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WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;
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W ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; // Selecting only W
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W ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Selecting only W
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W? ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; // Conditionally selecting only W
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W? ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Conditionally selecting only W
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Z ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; // Selecting only Z
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Z ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; // Selecting only Z
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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// Controls the register file gate connecting it with the ALU and data bus
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// Controls the register file gate connecting it with the ALU and data bus
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:Reg gate
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:Reg gate
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< ctl_reg_in_hi=1; ctl_reg_in_lo=1; // From the ALU side into the register file
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< ctl_reg_in_hi=1; ctl_reg_in_lo=1; // From the ALU side into the register file
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> ctl_reg_out_hi=1; ctl_reg_out_lo=1; // From the register file into the ALU
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>l ctl_reg_out_lo=1; // From the register file into the ALU low byte only
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> ctl_reg_out_hi=1; ctl_reg_out_lo=1; // From the register file into the FLAGT and ALU
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>h ctl_reg_out_hi=1; // From the register file into the ALU high byte only
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// Enables a register gate (high/low) corresponding to the selected 8-bit register
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>r8 ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; // Enable register gate based on the rsel0
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>r8' ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; // Enable register gate based on the rsel3
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>l ctl_reg_out_lo=1; // From the register file onto the db1 (sw2 + FLAGT + sw1)
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>h ctl_reg_out_hi=1; // From the register file onto the db2 (sw2 + ALU)
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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// Switches on the data bus for each direction (upstream, downstream)
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// Switches on the data bus for each direction (upstream, downstream)
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//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:SW2
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:SW2
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d ctl_sw_2d=1;
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d ctl_sw_2d=1;
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u ctl_sw_2u=1;
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u ctl_sw_2u=1;
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- // Controlled by register gate
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:SW1
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:SW1
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< ctl_sw_1d=1;
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< ctl_sw_1d=1;
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> ctl_sw_1u=1;
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> ctl_sw_1u=1;
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| Line 173... |
Line 182... |
//-----------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------
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:ALU
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:ALU
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// Controls the master ALU output enable and the ALU input, only one can be active at a time
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// Controls the master ALU output enable and the ALU input, only one can be active at a time
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// >bs if set, will override >s0 which is used by bit instructions to override default M1/T3 load
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// >bs if set, will override >s0 which is used by bit instructions to override default M1/T3 load
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< ctl_alu_oe=1; // Enable ALU onto the data bus
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< ctl_alu_oe=1; // Enable ALU onto the data bus
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>s0 ctl_alu_shift_oe=!ctl_alu_bs_oe; // Shifter unit without shift-enable
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>s0 ctl_alu_shift_oe=~ctl_alu_bs_oe; // Shifter unit without shift-enable
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>s1 ctl_alu_shift_oe=1; ctl_shift_en=1; // Shifter unit AND shift enable!
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>s1 ctl_alu_shift_oe=1; ctl_shift_en=1; // Shifter unit AND shift enable!
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>bs ctl_alu_bs_oe=1; // Bit-selector unit
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>bs ctl_alu_bs_oe=1; // Bit-selector unit
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:ALU bus
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:ALU bus
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// Controls the writer to the internal ALU bus
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// Controls the writer to the internal ALU bus
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| Line 196... |
Line 205... |
bus ctl_alu_op1_sel_bus=1; // Internal bus
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bus ctl_alu_op1_sel_bus=1; // Internal bus
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low ctl_alu_op1_sel_low=1; // Write low nibble with a high nibble
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low ctl_alu_op1_sel_low=1; // Write low nibble with a high nibble
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0 ctl_alu_op1_sel_zero=1; // Zero
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0 ctl_alu_op1_sel_zero=1; // Zero
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:operation
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:operation
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// Sets the ALU core operation
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// Defines the ALU core compute operation
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//--------------------------------------------------------------------------------------------------------------------------
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// The listing is also showing their alternate formats (using if/then)
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CP \
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//-----------------------------------------------------------------------------------------
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ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
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CP ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
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if (ctl_alu_op_low) begin
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// ctl_alu_sel_op2_neg=1;
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ctl_flags_cf_set=1;
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// if (ctl_alu_op_low) begin
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end else begin
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// ctl_flags_cf_set=1;
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ctl_alu_core_hf=1;
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// end else begin
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end
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// ctl_alu_core_hf=1;
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//--------------------------------------------------------------------------------------------------------------------------
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// end
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SUB \
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//-----------------------------------------------------------------------------------------
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SUB ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
|
// ctl_alu_sel_op2_neg=1;
|
if (ctl_alu_op_low) begin
|
// if (ctl_alu_op_low) begin
|
ctl_flags_cf_set=1;
|
// ctl_flags_cf_set=1;
|
end else begin
|
// end else begin
|
ctl_alu_core_hf=1;
|
// ctl_alu_core_hf=1;
|
end
|
// end
|
//--------------------------------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------
|
SBC \
|
SBC ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
|
// ctl_alu_sel_op2_neg=1;
|
if (ctl_alu_op_low) begin
|
// if (ctl_alu_op_low) begin
|
ctl_flags_cf_cpl=1;
|
// ctl_flags_cf_cpl=1;
|
end else begin
|
// end else begin
|
ctl_alu_core_hf=1;
|
// ctl_alu_core_hf=1;
|
end
|
// end
|
//--------------------------------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------
|
SBCh \
|
SBCh ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
|
// ctl_alu_sel_op2_neg=1;
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if (!ctl_alu_op_low) begin
|
// if (~ctl_alu_op_low) begin
|
ctl_alu_core_hf=1;
|
// ctl_alu_core_hf=1;
|
end
|
// end
|
//--------------------------------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------
|
ADC \
|
ADC ctl_alu_core_hf|=~ctl_alu_op_low;
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
|
// if (~ctl_alu_op_low) begin
|
if (!ctl_alu_op_low) begin
|
// ctl_alu_core_hf=1;
|
ctl_alu_core_hf=1;
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// end
|
end
|
//-----------------------------------------------------------------------------------------
|
//--------------------------------------------------------------------------------------------------------------------------
|
ADD ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;
|
ADD \
|
// if (ctl_alu_op_low) begin
|
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
|
// ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
if (ctl_alu_op_low) begin
|
// end else begin
|
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
// ctl_alu_core_hf=1;
|
end else begin
|
// end
|
ctl_alu_core_hf=1;
|
//-----------------------------------------------------------------------------------------
|
end
|
AND ctl_alu_core_S=1; ctl_flags_cf_set=1;
|
//--------------------------------------------------------------------------------------------------------------------------
|
|
AND ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
|
|
OR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
OR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
XOR ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
XOR ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
|
|
NAND ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1;
|
NAND ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1;
|
|
NOR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; ctl_alu_sel_op2_neg=1;
|
NOR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; ctl_alu_sel_op2_neg=1;
|
//--------------------------------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------
|
|
|
PLA ctl_state_alu=1; // Assert the ALU PLA modifier to determine operation
|
PLA ctl_state_alu=1; // Assert the ALU PLA modifier to determine operation
|
|
|
:nibble
|
:nibble
|
// ALU computational phase: low nibble or high nibble
|
// ALU compute phase: working on low nibble or high nibble
|
L ctl_alu_op_low=1; // Activate ALU operation on low nibble
|
L ctl_alu_op_low=1; // Activate ALU operation on low nibble
|
H ctl_alu_sel_op2_high=1; // Activate ALU operation on high nibble
|
H ctl_alu_sel_op2_high=1; // Activate ALU operation on high nibble
|
|
|
//-----------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------
|
// FLAGT
|
// FLAGT
|
| Line 295... |
Line 301... |
0 ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; // Clear CF going into the ALU core
|
0 ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; // Clear CF going into the ALU core
|
1 ctl_flags_cf_set=1; // Set CF going into the ALU core
|
1 ctl_flags_cf_set=1; // Set CF going into the ALU core
|
^ ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; // CCF
|
^ ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; // CCF
|
:CF2
|
:CF2
|
R ctl_flags_use_cf2=1;
|
R ctl_flags_use_cf2=1;
|
W ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0;
|
W ctl_flags_cf2_we=1;
|
W.sh ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1;
|
W.sh ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1;
|
W.daa ctl_flags_cf2_we=1; ctl_flags_cf2_sel=2;
|
W.daa ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;
|
W.0 ctl_flags_cf2_we=1; ctl_flags_cf2_sel=3;
|
|
|
//------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------
|
// Macros for some special cases; also simplifies control logic for a number of instructions
|
// Special sequence macros for some instructions make it simpler for all other entries
|
//------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------
|
|
:Special
|
:Special
|
USE_SP ctl_reg_use_sp=1; // For 16-bit loads: use SP instead of AF
|
USE_SP ctl_reg_use_sp=1; // For 16-bit loads: use SP instead of AF
|
|
|
// A few more specific states and instructions:
|
// A few more specific states and instructions:
|
Ex_DE_HL ctl_reg_ex_de_hl=1; // EX DE,HL
|
Ex_DE_HL ctl_reg_ex_de_hl=1; // EX DE,HL
|
| Line 316... |
Line 321... |
DI_EI ctl_iffx_bit=op3; ctl_iffx_we=1; // DI/EI
|
DI_EI ctl_iffx_bit=op3; ctl_iffx_we=1; // DI/EI
|
IM ctl_im_we=1; // IM n ('n' is read by opcode[4:3])
|
IM ctl_im_we=1; // IM n ('n' is read by opcode[4:3])
|
|
|
WZ=IX+d ixy_d=1; // Compute WZ=IX+d
|
WZ=IX+d ixy_d=1; // Compute WZ=IX+d
|
IX_IY ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; // IX/IY prefix
|
IX_IY ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; // IX/IY prefix
|
CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; // Clear IX/IY flag
|
CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; // Clear IX/IY flag
|
|
|
CB ctl_state_tbl_cb_set=1; setCBED=1; // CB-table prefix
|
CB ctl_state_tbl_cb_set=1; setCBED=1; // CB-table prefix
|
ED ctl_state_tbl_ed_set=1; setCBED=1; // ED-table prefix
|
ED ctl_state_tbl_ed_set=1; setCBED=1; // ED-table prefix
|
CLR_CB_ED ctl_state_tbl_clr=!setCBED; // Clear CB/ED prefix
|
CLR_CB_ED ctl_state_tbl_clr=~setCBED; // Clear CB/ED prefix
|
|
|
// If the NF is set, complement HF and CF on the way out to the bus
|
// If the NF is set, complement HF and CF on the way out to the bus
|
// This is used to correctly set those flags after subtraction operations
|
// This is used to correctly set those flags after subtraction operations
|
?NF_HF_CF ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf;
|
?NF_HF_CF ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf;
|
?NF_HF ctl_flags_hf_cpl=flags_nf;
|
?NF_HF ctl_flags_hf_cpl=flags_nf;
|
?~CF_HF ctl_flags_hf_cpl=!flags_cf; // Used for CCF
|
?~CF_HF ctl_flags_hf_cpl=~flags_cf; // Used for CCF
|
?SF_NEG ctl_alu_sel_op2_neg=flags_sf;
|
?SF_NEG ctl_alu_sel_op2_neg=flags_sf;
|
NEG_OP2 ctl_alu_sel_op2_neg=1;
|
NEG_OP2 ctl_alu_sel_op2_neg=1;
|
?NF_SUB ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf;
|
?NF_SUB ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf;
|
|
|
// M1 opcode read cycle and the refresh register increment cycle
|
// M1 opcode read cycle and the refresh register increment cycle
|
// Write opcode into the instruction register through internal db0 bus:
|
// Write opcode into the instruction register through internal db0 bus:
|
OpcodeToIR ctl_ir_we=1;
|
OpcodeToIR ctl_ir_we=1;
|
|
|
// At the common instruction load M1/T3, override opcode byte when servicing interrupts:
|
// At the common instruction load M1/T3, override opcode byte when servicing interrupts:
|
// 1. We are in HALT mode: push NOP (0x00) instead
|
// 1. We are in HALT mode: push NOP (0x00) instead
|
// 2. We are in INTR mode (IM1 or IM2): push RST38 (0xFF) instead
|
// 2. We are in INTR mode (IM1 or IM2): push RST38 (0xFF) instead
|
// 3. We are in NMI mode: push RST38 (0xFF) instead
|
// 3. We are in NMI mode: push RST38 (0xFF) instead
|
OverrideIR ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi;
|
OverrideIR ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi;
|
|
|
// RST instruction uses opcode[5:3] to specify a vector and this control passes those 3 bits through
|
// RST instruction uses opcode[5:3] to specify a vector and this macro passes those 3 bits through
|
MASK_543 ctl_sw_mask543_en=!((in_intr & im2) | in_nmi);
|
MASK_543 ctl_sw_mask543_en=~((in_intr & im2) | in_nmi);
|
// Based on the in_nmi state, several things are set:
|
// Based on the in_nmi state:
|
// 1. Disable SW1 so the opcode will not get onto db1 bus
|
// 1. Disable SW1 so the opcode will not get onto db1 bus
|
// 2. Generate 0x66 on the db1 bus which will be used as the target vector address
|
// 2. Generate 0x66 on the db1 bus which will be used as the target vector address
|
// 3. Clear IFF1 (done by the nmi logic on posedge of in_nmi)
|
// 3. Clear IFF1 (done by the nmi logic on posedge of in_nmi)
|
RST_NMI ctl_sw_1d=!in_nmi; ctl_66_oe=in_nmi;
|
RST_NMI ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi;
|
// Based on the in_intr state, several things are set:
|
// Based on the in_intr state:
|
// 1. IM1 mode, force 0xFF on the db0 bus
|
// 1. IM1 mode, force 0xFF on the db0 bus
|
// 2. Clear IFF1 and IFF2 (done by the intr logic on posedge of in_intr)
|
// 2. Clear IFF1 and IFF2 (done by the intr logic on posedge of in_intr)
|
RST_INT ctl_bus_ff_oe=in_intr & im1;
|
RST_INT ctl_bus_ff_oe=in_intr & im1;
|
RETN ctl_iff1_iff2=1; // RETN copies IFF2 into IFF1
|
RETN ctl_iff1_iff2=1; // RETN copies IFF2 into IFF1
|
NO_INTS ctl_no_ints=1; // Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD)
|
NO_INTS ctl_no_ints=1; // Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD)
|
