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[/] [a-z80/] [trunk/] [cpu/] [registers/] [reg_control.v] - Diff between revs 13 and 16

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Rev 13 Rev 16
Line 12... Line 12... 
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// applicable agreement for further details.
 
 
 
 
 
// PROGRAM              "Quartus II 64-Bit"
 
// PROGRAM              "Quartus II 64-Bit"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// CREATED              "Thu Dec 08 22:19:25 2016"
 
// CREATED              "Sat Dec 10 09:05:10 2016"
 
 
 
 
 
module reg_control(
 
module reg_control(
 
        ctl_reg_exx,
 
        ctl_reg_exx,
 
        ctl_reg_ex_af,
 
        ctl_reg_ex_af,
 
        ctl_reg_ex_de_hl,
 
        ctl_reg_ex_de_hl,
Line 32... Line 32... 
        ctl_reg_sys_we_lo,
 
        ctl_reg_sys_we_lo,
 
        ctl_reg_sys_we_hi,
 
        ctl_reg_sys_we_hi,
 
        ctl_reg_sys_we,
 
        ctl_reg_sys_we,
 
        clk,
 
        clk,
 
        ctl_sw_4d,
 
        ctl_sw_4d,
 
        hold_clk_wait,
 
        nhold_clk_wait,
 
        ctl_reg_gp_hilo,
 
        ctl_reg_gp_hilo,
 
        ctl_reg_gp_sel,
 
        ctl_reg_gp_sel,
 
        ctl_reg_sys_hilo,
 
        ctl_reg_sys_hilo,
 
        reg_sel_bc,
 
        reg_sel_bc,
 
        reg_sel_bc2,
 
        reg_sel_bc2,
Line 79... Line 79... 
input wire      ctl_reg_sys_we_lo;
 
input wire      ctl_reg_sys_we_lo;
 
input wire      ctl_reg_sys_we_hi;
 
input wire      ctl_reg_sys_we_hi;
 
input wire      ctl_reg_sys_we;
 
input wire      ctl_reg_sys_we;
 
input wire      clk;
 
input wire      clk;
 
input wire      ctl_sw_4d;
 
input wire      ctl_sw_4d;
 
input wire      hold_clk_wait;
 
input wire      nhold_clk_wait;
 
input wire      [1:0] ctl_reg_gp_hilo;
 
input wire      [1:0] ctl_reg_gp_hilo;
 
input wire      [1:0] ctl_reg_gp_sel;
 
input wire      [1:0] ctl_reg_gp_sel;
 
input wire      [1:0] ctl_reg_sys_hilo;
 
input wire      [1:0] ctl_reg_sys_hilo;
 
output wire     reg_sel_bc;
 
output wire     reg_sel_bc;
 
output wire     reg_sel_bc2;
 
output wire     reg_sel_bc2;
Line 111... Line 111... 
 
 
 
 
reg     bank_af;
 
reg     bank_af;
 
reg     bank_exx;
 
reg     bank_exx;
 
reg     bank_hl_de1;
 
reg     bank_hl_de1;
 
reg     bank_hl_de2;
 
reg     bank_hl_de2;
 
wire    n_hold_clk_wait;
 
 
 
wire    reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
wire    reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
wire    SYNTHESIZED_WIRE_52;
 
wire    SYNTHESIZED_WIRE_52;
 
wire    SYNTHESIZED_WIRE_53;
 
wire    SYNTHESIZED_WIRE_53;
 
wire    SYNTHESIZED_WIRE_2;
 
wire    SYNTHESIZED_WIRE_2;
 
wire    SYNTHESIZED_WIRE_54;
 
wire    SYNTHESIZED_WIRE_54;
Line 241... Line 240... 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        bank_af <= 0;
 
        bank_af <= 0;
 
        end
 
        end
 
else
 
else
 
if (n_hold_clk_wait)
 
if (nhold_clk_wait)
 
        begin
 
        begin
 
        bank_af <= bank_af ^ ctl_reg_ex_af;
 
        bank_af <= bank_af ^ ctl_reg_ex_af;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 271... Line 270... 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        bank_hl_de2 <= 0;
 
        bank_hl_de2 <= 0;
 
        end
 
        end
 
else
 
else
 
if (n_hold_clk_wait)
 
if (nhold_clk_wait)
 
        begin
 
        begin
 
        bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
 
        bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 291... Line 290... 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        bank_hl_de1 <= 0;
 
        bank_hl_de1 <= 0;
 
        end
 
        end
 
else
 
else
 
if (n_hold_clk_wait)
 
if (nhold_clk_wait)
 
        begin
 
        begin
 
        bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
 
        bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 305... Line 304... 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        bank_exx <= 0;
 
        bank_exx <= 0;
 
        end
 
        end
 
else
 
else
 
if (n_hold_clk_wait)
 
if (nhold_clk_wait)
 
        begin
 
        begin
 
        bank_exx <= bank_exx ^ ctl_reg_exx;
 
        bank_exx <= bank_exx ^ ctl_reg_exx;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 317... Line 316... 
 
 
 
 
assign  SYNTHESIZED_WIRE_30 =  ~ctl_reg_gp_sel[0];
 
assign  SYNTHESIZED_WIRE_30 =  ~ctl_reg_gp_sel[0];
 
 
 
 
 
assign  SYNTHESIZED_WIRE_31 =  ~ctl_reg_gp_sel[1];
 
assign  SYNTHESIZED_WIRE_31 =  ~ctl_reg_gp_sel[1];
 
 
 
 
 
assign  n_hold_clk_wait =  ~hold_clk_wait;
 
 
 
 
 
 
 
assign  reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
assign  reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
 
 
 
 
assign  reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
assign  reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
 
 
 
 
endmodule
 
endmodule

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