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// Altera or its authorized distributors. Please refer to the
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Fri Nov 07 10:28:48 2014"
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// CREATED "Tue Mar 08 06:12:46 2016"
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module reg_file(
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module reg_file(
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reg_sel_sys_lo,
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reg_sel_sys_lo,
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reg_sel_gp_lo,
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reg_sel_gp_lo,
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reg_sel_sys_hi,
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reg_sel_sys_hi,
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reg_sel_gp_hi,
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reg_sel_gp_hi,
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reg_sel_ir,
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reg_sel_ir,
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reg_sel_pc,
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reg_sel_pc,
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ctl_sw_4d,
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ctl_sw_4u,
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ctl_sw_4u,
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reg_sel_wz,
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reg_sel_wz,
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reg_sel_sp,
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reg_sel_sp,
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reg_sel_iy,
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reg_sel_iy,
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reg_sel_ix,
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reg_sel_ix,
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ctl_reg_in_hi,
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ctl_reg_in_hi,
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ctl_reg_in_lo,
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ctl_reg_in_lo,
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ctl_reg_out_lo,
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ctl_reg_out_lo,
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ctl_reg_out_hi,
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ctl_reg_out_hi,
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clk,
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clk,
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reg_sw_4d_lo,
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reg_sw_4d_hi,
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db_hi_as,
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db_hi_as,
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db_hi_ds,
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db_hi_ds,
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db_lo_as,
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db_lo_as,
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db_lo_ds
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db_lo_ds
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);
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);
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input wire reg_sel_gp_lo;
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input wire reg_sel_gp_lo;
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input wire reg_sel_sys_hi;
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input wire reg_sel_sys_hi;
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input wire reg_sel_gp_hi;
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input wire reg_sel_gp_hi;
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input wire reg_sel_ir;
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input wire reg_sel_ir;
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input wire reg_sel_pc;
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input wire reg_sel_pc;
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input wire ctl_sw_4d;
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input wire ctl_sw_4u;
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input wire ctl_sw_4u;
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input wire reg_sel_wz;
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input wire reg_sel_wz;
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input wire reg_sel_sp;
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input wire reg_sel_sp;
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input wire reg_sel_iy;
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input wire reg_sel_iy;
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input wire reg_sel_ix;
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input wire reg_sel_ix;
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input wire ctl_reg_in_hi;
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input wire ctl_reg_in_hi;
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input wire ctl_reg_in_lo;
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input wire ctl_reg_in_lo;
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input wire ctl_reg_out_lo;
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input wire ctl_reg_out_lo;
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input wire ctl_reg_out_hi;
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input wire ctl_reg_out_hi;
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input wire clk;
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input wire clk;
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input wire reg_sw_4d_lo;
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input wire reg_sw_4d_hi;
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inout wire [7:0] db_hi_as;
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inout wire [7:0] db_hi_as;
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inout wire [7:0] db_hi_ds;
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inout wire [7:0] db_hi_ds;
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inout wire [7:0] db_lo_as;
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inout wire [7:0] db_lo_as;
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inout wire [7:0] db_lo_ds;
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inout wire [7:0] db_lo_ds;
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assign gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz;
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assign gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz;
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assign gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz;
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assign gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz;
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assign gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz;
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assign gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz;
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assign gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz;
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assign gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz;
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assign db_lo_as[7] = ctl_sw_4d ? gdfx_temp0[7] : 1'bz;
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assign db_lo_as[7] = reg_sw_4d_lo ? gdfx_temp0[7] : 1'bz;
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assign db_lo_as[6] = ctl_sw_4d ? gdfx_temp0[6] : 1'bz;
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assign db_lo_as[6] = reg_sw_4d_lo ? gdfx_temp0[6] : 1'bz;
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assign db_lo_as[5] = ctl_sw_4d ? gdfx_temp0[5] : 1'bz;
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assign db_lo_as[5] = reg_sw_4d_lo ? gdfx_temp0[5] : 1'bz;
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assign db_lo_as[4] = ctl_sw_4d ? gdfx_temp0[4] : 1'bz;
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assign db_lo_as[4] = reg_sw_4d_lo ? gdfx_temp0[4] : 1'bz;
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assign db_lo_as[3] = ctl_sw_4d ? gdfx_temp0[3] : 1'bz;
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assign db_lo_as[3] = reg_sw_4d_lo ? gdfx_temp0[3] : 1'bz;
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assign db_lo_as[2] = ctl_sw_4d ? gdfx_temp0[2] : 1'bz;
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assign db_lo_as[2] = reg_sw_4d_lo ? gdfx_temp0[2] : 1'bz;
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assign db_lo_as[1] = ctl_sw_4d ? gdfx_temp0[1] : 1'bz;
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assign db_lo_as[1] = reg_sw_4d_lo ? gdfx_temp0[1] : 1'bz;
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assign db_lo_as[0] = ctl_sw_4d ? gdfx_temp0[0] : 1'bz;
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assign db_lo_as[0] = reg_sw_4d_lo ? gdfx_temp0[0] : 1'bz;
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assign gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz;
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assign gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz;
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assign gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz;
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assign gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz;
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assign gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz;
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assign gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz;
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assign gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz;
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assign gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz;
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assign gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz;
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assign gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz;
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assign gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz;
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assign gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz;
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assign gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz;
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assign gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz;
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assign gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz;
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assign gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz;
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assign db_hi_as[7] = ctl_sw_4d ? gdfx_temp1[7] : 1'bz;
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assign db_hi_as[7] = reg_sw_4d_hi ? gdfx_temp1[7] : 1'bz;
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assign db_hi_as[6] = ctl_sw_4d ? gdfx_temp1[6] : 1'bz;
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assign db_hi_as[6] = reg_sw_4d_hi ? gdfx_temp1[6] : 1'bz;
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assign db_hi_as[5] = ctl_sw_4d ? gdfx_temp1[5] : 1'bz;
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assign db_hi_as[5] = reg_sw_4d_hi ? gdfx_temp1[5] : 1'bz;
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assign db_hi_as[4] = ctl_sw_4d ? gdfx_temp1[4] : 1'bz;
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assign db_hi_as[4] = reg_sw_4d_hi ? gdfx_temp1[4] : 1'bz;
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assign db_hi_as[3] = ctl_sw_4d ? gdfx_temp1[3] : 1'bz;
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assign db_hi_as[3] = reg_sw_4d_hi ? gdfx_temp1[3] : 1'bz;
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assign db_hi_as[2] = ctl_sw_4d ? gdfx_temp1[2] : 1'bz;
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assign db_hi_as[2] = reg_sw_4d_hi ? gdfx_temp1[2] : 1'bz;
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assign db_hi_as[1] = ctl_sw_4d ? gdfx_temp1[1] : 1'bz;
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assign db_hi_as[1] = reg_sw_4d_hi ? gdfx_temp1[1] : 1'bz;
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assign db_hi_as[0] = ctl_sw_4d ? gdfx_temp1[0] : 1'bz;
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assign db_hi_as[0] = reg_sw_4d_hi ? gdfx_temp1[0] : 1'bz;
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assign db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz;
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assign db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz;
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assign db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz;
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assign db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz;
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assign db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz;
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assign db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz;
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assign db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz;
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assign db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz;
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