| Line 47... |
Line 47... |
logic ctl_reg_sys_we_lo_sig=0; // Write to low byte of a system register
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logic ctl_reg_sys_we_lo_sig=0; // Write to low byte of a system register
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logic ctl_reg_sys_we_hi_sig=0; // Write to high byte of a system register
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logic ctl_reg_sys_we_hi_sig=0; // Write to high byte of a system register
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logic ctl_reg_sys_we_sig=0; // Write to system register
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logic ctl_reg_sys_we_sig=0; // Write to system register
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logic use_ixiy_sig=0; // Use IX or IY
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logic use_ixiy_sig=0; // Use IX or IY
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logic use_ix_sig=0; // Use IX and not IY
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logic use_ix_sig=0; // Use IX and not IY
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logic hold_clk_wait_sig=0; // Hold all transitions
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logic nhold_clk_wait_sig=1; // Enable transitions due to nWAIT
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logic ctl_reg_exx_sig=0; // Exchange register banks
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logic ctl_reg_exx_sig=0; // Exchange register banks
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logic ctl_reg_ex_af_sig=0; // Exchange AF banks
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logic ctl_reg_ex_af_sig=0; // Exchange AF banks
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logic ctl_reg_ex_de_hl_sig=0; // Exchange HL/DE banks
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logic ctl_reg_ex_de_hl_sig=0; // Exchange HL/DE banks
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logic ctl_reg_use_sp_sig=0; // Use SP register
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logic ctl_reg_use_sp_sig=0; // Use SP register
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| Line 181... |
Line 181... |
.ctl_reg_sys_we_lo(ctl_reg_sys_we_lo_sig),// input ctl_reg_sys_we_lo_sig
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.ctl_reg_sys_we_lo(ctl_reg_sys_we_lo_sig),// input ctl_reg_sys_we_lo_sig
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.ctl_reg_sys_we_hi(ctl_reg_sys_we_hi_sig),// input ctl_reg_sys_we_hi_sig
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.ctl_reg_sys_we_hi(ctl_reg_sys_we_hi_sig),// input ctl_reg_sys_we_hi_sig
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.ctl_reg_sys_we(ctl_reg_sys_we_sig) , // input ctl_reg_sys_we_sig
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.ctl_reg_sys_we(ctl_reg_sys_we_sig) , // input ctl_reg_sys_we_sig
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.clk(clk) , // input clk
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.clk(clk) , // input clk
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.ctl_sw_4d (ctl_sw_4d_sig) , // input ctl_sw_4d
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.ctl_sw_4d (ctl_sw_4d_sig) , // input ctl_sw_4d
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.hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig
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.nhold_clk_wait(nhold_clk_wait_sig) , // input nhold_clk_wait_sig
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.reg_sel_bc(reg_sel_bc_sig) , // output reg_sel_bc_sig
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.reg_sel_bc(reg_sel_bc_sig) , // output reg_sel_bc_sig
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.reg_sel_bc2(reg_sel_bc2_sig) , // output reg_sel_bc2_sig
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.reg_sel_bc2(reg_sel_bc2_sig) , // output reg_sel_bc2_sig
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.reg_sel_ix(reg_sel_ix_sig) , // output reg_sel_ix_sig
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.reg_sel_ix(reg_sel_ix_sig) , // output reg_sel_ix_sig
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.reg_sel_iy(reg_sel_iy_sig) , // output reg_sel_iy_sig
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.reg_sel_iy(reg_sel_iy_sig) , // output reg_sel_iy_sig
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.reg_sel_de(reg_sel_de_sig) , // output reg_sel_de_sig
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.reg_sel_de(reg_sel_de_sig) , // output reg_sel_de_sig
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