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#!/usr/bin/env python
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#!/usr/bin/env python3
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#
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#
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# This script generates a test include file from a set of "Fuse" test vectors.
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# This script generates a test include file from a set of "Fuse" test vectors.
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#
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#
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# Three common testing configurations are:
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# Three common testing configurations are:
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#
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#
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t1 = f1.read().splitlines()
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t1 = f1.read().splitlines()
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# Remove all tests until the one we need to start with. Tests are separated by empty lines.
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# Remove all tests until the one we need to start with. Tests are separated by empty lines.
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while t1[0].split(" ")[0]!=start_test:
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while t1[0].split(" ")[0]!=start_test:
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while len(t1.pop(0))>0:
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while len(t1.pop(0))>0:
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pass
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pass
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t1 = filter(None, t1) # Filter out empty lines
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t1 = list(filter(None, t1)) # Filter out empty lines
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with open(tests_expected) as f2:
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with open(tests_expected) as f2:
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t2 = f2.read().splitlines()
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t2 = f2.read().splitlines()
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while t2[0].split(" ")[0]!=start_test:
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while t2[0].split(" ")[0]!=start_test:
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while len(t2.pop(0))>0:
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while len(t2.pop(0))>0:
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# Create a file that should be included in the test_fuse source
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# Create a file that should be included in the test_fuse source
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ftest = open('test_fuse.vh', 'w')
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ftest = open('test_fuse.vh', 'w')
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ftest.write("// Automatically generated by genfuse.py\n\n")
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ftest.write("// Automatically generated by genfuse.py\n\n")
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# Initial pre-test state is reset and control signals asserted
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# Initial pre-test state is reset and control signals asserted
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ftest.write("force dut.resets_.clrpc=0;\n")
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ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
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ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
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ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
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ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
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ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
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ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
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ftest.write("#2\n")
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ftest.write("#2\n")
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total_clks = total_clks + 2
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total_clks = total_clks + 2
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if len(t1)==0 or run_tests==0:
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if len(t1)==0 or run_tests==0:
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break
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break
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run_tests = run_tests-1
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run_tests = run_tests-1
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# Clear opcode register before starting a new instruction
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# Clear opcode register before starting a new instruction
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ftest.write(" force dut.instruction_reg_.ctl_ir_we=1;\n")
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ftest.write(" force dut.ir_.ctl_ir_we=1;\n")
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ftest.write(" force dut.instruction_reg_.db=0;\n")
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ftest.write(" force dut.ir_.db=0;\n")
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ftest.write("#2 release dut.instruction_reg_.ctl_ir_we;\n")
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ftest.write("#2 release dut.ir_.ctl_ir_we;\n")
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ftest.write(" release dut.instruction_reg_.db;\n")
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ftest.write(" release dut.ir_.db;\n")
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total_clks = total_clks + 2
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total_clks = total_clks + 2
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# Format of the test.in file:
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# Format of the test.in file:
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# <arbitrary test description>
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# <arbitrary test description>
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# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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# I R IFF1 IFF2 IM <halted> <tstates>
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# I R IFF1 IFF2 IM <halted> <tstates>
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name = t1.pop(0)
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name = t1.pop(0)
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ftest.write("$fdisplay(f,\"Testing opcode " + name + "\");\n")
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ftest.write("$fdisplay(f,\"Testing opcode " + name + "\");\n")
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name = name.split(" ")[0]
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name = name.split(" ")[0]
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r = t1.pop(0).split(' ')
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r = t1.pop(0).split(' ')
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r = filter(None, r)
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r = list(filter(None, r))
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# 0 1 2 3 4 5 6 7 8 9 10 11 (index)
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# 0 1 2 3 4 5 6 7 8 9 10 11 (index)
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# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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# AF BC DE HL AF' BC' DE' HL' IX IY SP PC
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RegWrite("af", r[0])
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RegWrite("af", r[0])
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RegWrite("bc", r[1])
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RegWrite("bc", r[1])
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RegWrite("de", r[2])
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RegWrite("de", r[2])
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RegWrite("sp", r[10])
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RegWrite("sp", r[10])
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RegWrite("wz", "0000") # Initialize WZ with 0
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RegWrite("wz", "0000") # Initialize WZ with 0
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RegWrite("pc", r[11])
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RegWrite("pc", r[11])
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s = t1.pop(0).split(' ')
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s = t1.pop(0).split(' ')
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s = filter(None, s)
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s = list(filter(None, s))
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# 0 1 2 3 4 5 6 (index)
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# 0 1 2 3 4 5 6 (index)
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# I R IFF1 IFF2 IM <halted> <tstates?>
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# I R IFF1 IFF2 IM <halted> <tstates?>
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RegWrite("ir", s[0]+s[1])
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RegWrite("ir", s[0]+s[1])
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# TODO: Store IFF1/IFF2, IM, in_halt
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# TODO: Store IFF1/IFF2, IM, in_halt
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# used below after the opcode has executed (for IO writes)
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# used below after the opcode has executed (for IO writes)
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check_io = [] # List of check statements (for OUT instructions)
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check_io = [] # List of check statements (for OUT instructions)
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t2b = list(t2)
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t2b = list(t2)
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while True:
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while True:
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m = t2b.pop(0).split(' ')
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m = t2b.pop(0).split(' ')
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m = filter(None, m)
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m = list(filter(None, m))
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if len(m)==0 or m[0]=="-1":
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if len(m)==0 or m[0]=="-1":
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break
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break
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if len(m)==4 and m[1]=="PR":
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if len(m)==4 and m[1]=="PR":
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address = int(m[2],16)
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address = int(m[2],16)
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ftest.write(" io.IO[" + str(address) + "] = 8'h" + m[3] + ";\n")
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ftest.write(" io.IO[" + str(address) + "] = 8'h" + m[3] + ";\n")
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# Due to the instruction execution overlap, first 2T of an instruction may be writing
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# Due to the instruction execution overlap, first 2T of an instruction may be writing
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# value back to a general purpose register (like AF) and we need to prevent that.
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# value back to a general purpose register (like AF) and we need to prevent that.
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# Similarly, we let the execution continues 2T into the next instruction but we prevent
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# Similarly, we let the execution continues 2T into the next instruction but we prevent
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# it from writing to system registers so it cannot update PC and IR.
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# it from writing to system registers so it cannot update PC and IR.
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ftest.write(" force dut.z80_top_ifc_n.fpga_reset=0;\n")
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ftest.write(" force dut.z80_top_ifc_n.fpga_reset=0;\n")
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ftest.write(" force dut.address_latch_.abus=16'h" + r[11] +";\n")
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ftest.write(" force dut.address_latch_.Q=16'h" + r[11] +";\n") # Force PC into the address latch
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ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
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ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
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ftest.write(" release dut.reg_file_.reg_gp_we;\n")
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ftest.write(" release dut.reg_file_.reg_gp_we;\n")
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ftest.write("#3\n") # 1T (#2) overlaps the reset cycle
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ftest.write("#3\n") # 1T (#2) overlaps the reset cycle
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total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
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total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
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ftest.write(" release dut.address_latch_.abus;\n")
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ftest.write(" release dut.address_latch_.Q;\n")
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ftest.write("#1\n")
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ftest.write("#1\n")
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total_clks = total_clks + 1
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total_clks = total_clks + 1
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# Read and parse the tests expected list which contains the expected results of our run,
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# Read and parse the tests expected list which contains the expected results of our run,
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# including the number of clocks for a particular instruction
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# including the number of clocks for a particular instruction
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while True:
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while True:
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l = t2.pop(0)
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l = t2.pop(0)
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if l[0]!=' ':
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if l[0]!=' ':
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break
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break
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r = l.split(' ')
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r = l.split(' ')
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r = filter(None, r)
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r = list(filter(None, r))
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s = t2.pop(0).split(' ')
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s = t2.pop(0).split(' ')
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s = filter(None, s)
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s = list(filter(None, s))
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ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
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ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
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total_clks = total_clks + ticks
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total_clks = total_clks + ticks
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ftest.write("#" + str(ticks) + " // Execute\n")
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ftest.write("#" + str(ticks) + " // Execute\n")
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RegRead("ir", s[0]+s[1])
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RegRead("ir", s[0]+s[1])
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# Read memory configuration until an empty line or -1 at the end
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# Read memory configuration until an empty line or -1 at the end
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while True:
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while True:
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m = t2.pop(0).split(' ')
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m = t2.pop(0).split(' ')
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m = filter(None, m)
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m = list(filter(None, m))
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if len(m)==0 or m[0]=="-1":
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if len(m)==0 or m[0]=="-1":
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break
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break
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address = int(m.pop(0),16)
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address = int(m.pop(0),16)
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while True:
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while True:
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d = m.pop(0)
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d = m.pop(0)
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