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https://opencores.org/ocsvn/a-z80/a-z80/trunk
[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [globals.vh] - Diff between revs 6 and 8
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| Rev 6 |
Rev 8 |
| Line 78... |
Line 78... |
wire ctl_flags_hf_cpl;
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wire ctl_flags_hf_cpl;
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wire ctl_flags_use_cf2;
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wire ctl_flags_use_cf2;
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wire ctl_flags_hf2_we;
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wire ctl_flags_hf2_we;
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wire ctl_flags_nf_clr;
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wire ctl_flags_nf_clr;
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wire ctl_alu_zero_16bit;
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wire ctl_alu_zero_16bit;
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wire [1:0] ctl_flags_cf2_sel;
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wire ctl_flags_cf2_sel_shift;
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wire ctl_sw_4d;
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wire ctl_flags_cf2_sel_daa;
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wire ctl_sw_4u;
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wire ctl_sw_4u;
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wire ctl_reg_in_hi;
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wire ctl_reg_in_hi;
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wire ctl_reg_in_lo;
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wire ctl_reg_in_lo;
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wire ctl_reg_out_lo;
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wire ctl_reg_out_lo;
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wire ctl_reg_out_hi;
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wire ctl_reg_out_hi;
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| Line 97... |
Line 97... |
wire ctl_reg_gp_we;
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wire ctl_reg_gp_we;
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wire ctl_reg_not_pc;
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wire ctl_reg_not_pc;
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wire ctl_reg_sys_we_lo;
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wire ctl_reg_sys_we_lo;
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wire ctl_reg_sys_we_hi;
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wire ctl_reg_sys_we_hi;
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wire ctl_reg_sys_we;
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wire ctl_reg_sys_we;
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wire ctl_sw_4d;
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wire [1:0] ctl_reg_gp_hilo;
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wire [1:0] ctl_reg_gp_hilo;
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wire [1:0] ctl_reg_gp_sel;
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wire [1:0] ctl_reg_gp_sel;
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wire [1:0] ctl_reg_sys_hilo;
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wire [1:0] ctl_reg_sys_hilo;
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wire ctl_inc_cy;
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wire ctl_inc_cy;
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wire ctl_inc_dec;
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wire ctl_inc_dec;
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wire ctl_inc_zero;
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wire ctl_al_we;
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wire ctl_al_we;
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wire ctl_inc_limit6;
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wire ctl_inc_limit6;
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wire ctl_bus_inc_oe;
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wire ctl_bus_inc_oe;
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wire ctl_apin_mux;
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wire ctl_apin_mux;
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wire ctl_apin_mux2;
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wire ctl_apin_mux2;
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wire ctl_bus_ff_oe;
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wire ctl_bus_ff_oe;
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wire ctl_bus_zero_oe;
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wire ctl_bus_zero_oe;
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wire ctl_bus_db_oe;
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wire ctl_sw_1u;
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wire ctl_sw_1u;
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wire ctl_sw_1d;
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wire ctl_sw_1d;
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wire ctl_sw_2u;
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wire ctl_sw_2u;
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wire ctl_sw_2d;
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wire ctl_sw_2d;
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wire ctl_sw_mask543_en;
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wire ctl_sw_mask543_en;
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wire ctl_bus_db_we;
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wire ctl_bus_db_we;
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wire ctl_bus_db_oe;
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// Module: control/execute.sv
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// Module: control/execute.v
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wire nextM;
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wire nextM;
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wire setM1;
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wire setM1;
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wire fFetch;
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wire fFetch;
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wire fMRead;
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wire fMRead;
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wire fMWrite;
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wire fMWrite;
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wire fIORead;
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wire fIORead;
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wire fIOWrite;
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wire fIOWrite;
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// Module: control/interrupts.v
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// Module: control/interrupts.v
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wire iff1;
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wire iff2;
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wire iff2;
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wire im1;
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wire im1;
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wire im2;
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wire im2;
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wire in_nmi;
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wire in_nmi;
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wire in_intr;
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wire in_intr;
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| Line 143... |
Line 142... |
// Module: control/pin_control.v
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// Module: control/pin_control.v
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wire bus_ab_pin_we;
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wire bus_ab_pin_we;
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wire bus_db_pin_oe;
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wire bus_db_pin_oe;
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wire bus_db_pin_re;
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wire bus_db_pin_re;
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// Module: control/pla_decode.sv
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// Module: control/pla_decode.v
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wire [104:0] pla;
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wire [104:0] pla;
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// Module: control/resets.v
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// Module: control/resets.v
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wire clrpc;
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wire clrpc;
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wire nreset;
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wire nreset;
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| Line 165... |
Line 164... |
wire M1;
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wire M1;
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wire M2;
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wire M2;
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wire M3;
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wire M3;
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wire M4;
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wire M4;
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wire M5;
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wire M5;
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wire M6;
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wire T1;
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wire T1;
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wire T2;
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wire T2;
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wire T3;
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wire T3;
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wire T4;
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wire T4;
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wire T5;
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wire T5;
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| Line 254... |
Line 252... |
wire reg_sel_sys_lo;
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wire reg_sel_sys_lo;
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wire reg_sel_sys_hi;
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wire reg_sel_sys_hi;
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wire reg_gp_we;
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wire reg_gp_we;
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wire reg_sys_we_lo;
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wire reg_sys_we_lo;
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wire reg_sys_we_hi;
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wire reg_sys_we_hi;
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wire reg_sw_4d_lo;
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wire reg_sw_4d_hi;
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// Module: bus/address_latch.v
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// Module: bus/address_latch.v
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wire address_is_1;
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wire address_is_1;
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wire [15:0] address;
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wire [15:0] address;
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// Module: bus/address_pins.v
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// Module: bus/address_pins.v
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wire [15:0] abus;
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wire [15:0] abus;
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// Module: bus/bus_control.v
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// Module: bus/bus_switch.v
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wire bus_db_oe;
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// Module: bus/bus_switch.sv
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wire bus_sw_1u;
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wire bus_sw_1u;
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wire bus_sw_1d;
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wire bus_sw_1d;
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wire bus_sw_2u;
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wire bus_sw_2u;
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wire bus_sw_2d;
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wire bus_sw_2d;
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wire bus_sw_mask543_en;
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wire bus_sw_mask543_en;
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